Abstract: A periodic multi-bit digital signal is synthesized having a frequency that is specified by the frequency of a periodic reference signal that is asynchronous with respect to a sampling clock of the periodic digital signal. In a digital video system, for example, a digital color subcarrier is synthesized and synchronized to a reference frequency of a crystal oscillator that is asynchronous with respect to a digital system clock for the digital video system. The periodic digital signal is generated by an adjustable digital oscillator clocked by the sampling clock. The frequency or phase of the periodic digital signal is compared to the frequency or phase of the periodic reference signal to produce an adjustment value for adjusting the periodic digital signal to synchronize the periodic digital signal with the periodic reference signal. The digital oscillator, for example, generates the periodic digital signal at the sampling rate by periodically incrementing an accumulator with the adjustment value.

Abstract: An apparatus for performing a generator locking for a video signal including a first video processing circuit for processing an input video signal, an expansion module having a second video processing circuit and a delay circuit having a delay time introduced by said second video processing circuit, a synchronizing signal separating circuit for separating a synchronizing signal from an external reference signal, and a phase-lock loop circuit for generating a reference control signal for said first video processing circuit as well as a phase comparison signal. Said phase comparison signal is fed-back to the phase-lock loop circuit by means of said delay circuit. Although the expansion module is connected to the expansion slot, a phase of a finally obtained video signal is remained in a same fixed relationship as a phase relationship when a connection board is connected to the expansion slot.

Abstract: An apparatus and method for controlling and detecting the alignment of a color frame phase from a composite analog video signal decodes the composite analog video signal to produce a component digital video signal and to generate a color frame signal that represents the start of each color frame for the composite analog video signal. Based upon the color frame signal a flag signal is inserted into the component digital video signal. The component digital video signal is captured by an analyzer based upon the flag signal so that the captured component digital video signal is in color frame phase with a stored reference component digital video signal. Preferably the stored reference component digital video signal represents a test sequence having an integer number of color frames plus or minus one video frame.

Abstract: A method and apparatus for phase-locking a plurality of display devices and multi-level driver for use therewith. Each of the display devices displays an image under the control of a distinct clock having a distinct clock rate. Each of the images contains a predetermined periodic indexing event. One of the clocks is designated as a master clock. The times of occurrence of the indexing events are compared, and the times of occurrence are caused to fall within a predetermined amount of time of one another so that each of the other clocks is phase-locked with the master clock.

Abstract: A compact, inexpensive circuit for generating several stable reference signals from several burst signals is provided.

Abstract: A novel method effectively adjusts the amplitude of a color burst signal in a chrominance of a composite video signal read by a reproducing head from a magnetic tape. A low pass filtered chrominance signal of 629 KHz obtained from the composite video signal is filtered to detect an original chrominance signal of 3.58 MHz. Also an original color burst signal is extracted from the chrominance signal by using a burst gate pulse generated by a burst gate pulse generator in a video cassette recorder system. The color burst signal is converted to that of a digital value corresponding thereto and comparing an amplitude of the converted color burst signal with a predetermined threshold value to provide a device control signal corresponding to the comparison result. In response to the device control signal, the color burst signal is selectively deemphasized to a predetermined level; and either one of the deemphasized color signal and the extracted color burst signal is selectively outputted.

Abstract: A color system determination circuit for use with an input video signal having a frequency component is disclosed. The circuit includes a color trap filter for attenuating the frequency component in the input video signal with the color trap filter providing a color burst output signal, a comparator for comparing the color burst output signal of the color trap filter and the frequency component of the input video signal, a maximum value detector which receives the color burst output signal of the color trap filter and a color burst sampling signal and detects a maximum value of the color burst output signal of the color trap filter during a period of the color burst sampling signal, and another maximum value detector which receives the video signal and the color burst sampling signal and detects a maximum value of the video signal during the period of the color burst sampling signal.

Abstract: An arrangement for desynchronizing video signals transported in virtual containers in frames over a synchronous network comprises a feedback loop incorporating a FIFO buffer store and a tuneable oscillator adapted to provide a video line clock from demapped video information. Each virtual container is identified within a frame by a pointer introduced by the synchronous transport process, and the loop is arranged to overcome the interference of these pointers with the color subcarrier in the desynchronized signal. The loop has a bandwidth sufficiently narrow to effectively ignore phase noise created by the pointers. The oscillator frequency is controlled such that the rate of information flow around the loop is substantially constant. Video bytes are written into the buffer store and are then read at a controlled rate determined by the oscillator frequency.

Abstract: A tuner circuit comprising a first frequency conversion means 14 for converting a high frequency input signal into a first intermediate frequency signal according to a first local oscillation signal, a second frequency conversion means 19 for converting the first intermediate frequency signal from the first frequency conversion means 14 into a second intermediate frequency signal according to a second local oscillation signal, a first PLL means 24 for controlling the first local oscillation signal so as to synchronize the phase of the signal with that of a reference oscillation signal having a fixed frequency, a second PLL means 31 for controlling the second local oscillation signal so as to synchronize the phase of the signal with that of a reference oscillation signal. In the first PLL means 24, a phase comparison frequency is set to a frequency higher than a specified value. In the second PLL means 31, a phase comparison frequency is set to a frequency lower than a specified value.

Abstract: An analog signal, for example, a video signal is divided into a high frequency signal and a low frequency signal by a high-pass filter and a low-pass filter. A high speed analog-to-digital converter (ADC) converts the high frequency signal to a first digital code while a low speed but high precision ADC converts the low frequency signal to a second digital code. A synthesizer combines the first and second digital codes and outputs a digital code as the result of the conversion. Therefore, analog-to-digital conversion with a high speed, high precision, and high resolution can be realized.

Abstract: A burst gate pulse generator generates a burst gate signal representative of a time period during which a burst signal is present within an input composite video signal. Each period of the input composite video signal includes a horizontal synchronization pulse, a burst signal and a video information signal. The burst gate pulse generator detects the end of the horizontal synchronization signal and begins the burst pulse at the end of the horizontal synchronization signal. A timing circuit including a charge storage device and a charge delivery device controls the duration of the burst pulse. When the burst pulse is activated the charge delivery device begins building a charge across the charge storage device until a threshold value is reached. Once the charge stored across the charge storage device equals the threshold value the burst pulse is deactivated. During the time when the burst pulse is active, the burst signal will be present on the input composite video signal.

Abstract: A burst gate pulse generator circuit generates a burst gate pulse signal representative of a time period during which a burst signal is present within a composite video signal without requiring external components. Each period of the composite video signal includes a horizontal synchronization signal pulse, a burst signal and a video information signal. A pair of integrated capacitors are discharged during the horizontal synchronization pulse. The capacitors are charged at different rates by two current sources after the horizontal synchronization pulse. A first amount of charge across a first capacitor rises above a predetermined threshold level in a first time period. The burst gate pulse signal is activated when the first amount of charge rises above the predetermined threshold level. This occurs before the burst signal is present within the composite video signal. A second amount of charge across a second capacitor rises above the predetermined threshold level in a second time period.

Abstract: A clock generation circuit for a digital video processing apparatus which has a simple structure and can be stably worked in both luminance and color signal systems. A color burst phase error signal indicative of phase difference of a color burst signal is produced on the basis of two color difference signals, a sampling clock signal is generated in accordance with the color burst phase error signal, the sampling clock is divided in order to produce a chrominance subcarrier signal, and the phase of the chrominance subcarrier signal is adjusted in accordance with the color burst phase error signal.

Abstract: A video/graphics overlay integrated circuit receives an analog composite video signal and a digital composite video signal and combines them in a predetermined format into an output composite video signal which is transmitted to a display device such as a television set. The digital video signal may be comprised of digital video, graphics data or a combination of digital video and graphics data. The digital video and graphics data are encoded by a digital encoder integrated circuit into a digital composite video signal. The digital composite video signal is coupled to the video/graphics overlay integrated circuit. An automatic phase correction circuit detects any phase difference between the burst signals of the analog composite video signal and the digital composite video signal.

Abstract: An image data processing apparatus is described that prevents the period of a horizontal timing signal from being shifted. The apparatus includes a separator, a phase-locked loop, a detector, a compensator and a timing signal generator. The detector delays a reference clock signal in a shorter period than the period of the reference clock signal, in a step-like manner, to produce a plurality of delayed timing signals having step-like phase differences. The detector further contrasts the plurality of delayed timing signals with a horizontal sync signal and the reference clock signal to measure the phase difference and the period of the horizontal sync signal. The compensator sets a ratio for combining consecutive luminance data in accordance with the phase difference and the period of the reference clock signal and combines consecutive luminance data in accordance with the ratio to generate compensated luminance data.

Abstract: A video signal level detector is configured to avoid the erroneous recognition of channels adjacent to normal channels as those which are to be stored during performance of an automatic channel detection and storage function. The video signal level detector separates at least two target signals whose levels are to be detected from an input composite video signal; detects signal levels of the target signals; compares each of the detected levels with a reference voltage level; and logic-operates the result to obtain a final detection so that a storage possibility of automatically detected channels is determined.

Abstract: An image information processing apparatus is described that suppresses noise generated in digital signal processing while preventing the circuit scale from enlarging. The apparatus includes a separator, a first detector, a second detector, a phase-locked loop, an A/D converter, a phase difference detector, a chrominance data processor and a luminance data processor. The phase difference detector detects a phase difference between the reference clock signal and the scan sync signal. The luminance data processor combines the luminance data in Units of two pieces to produce compensated luminance data in accordance with the phase difference.

Abstract: A video transmission system and method including a technique for deriving clock information in a receiver from a transmitted analog video signal to decipher digital data encoded on the video signal. A phase-locked loop in the transmitter is used to phase-lock a color burst subcarrier in the video signal to a local oscillator in the phase-locked loop to phase-lock a data clock to the subcarrier. A phase-locked loop in the receiver is also used to phase-lock the subearrier of the transmitted video signal to a local oscillator in the phase-locked loop to again phase-lock a data clock to the subcarrier. By phase-locking a data clock to the subcarrier in both the transmitter and receiver, the data clock and the receiver can be synchronized to the data clock and the transmitter to provide for effective digital data recovery without the use of additional data bits for clock phase information.

Abstract: A solid state color image pickup apparatus easily converts an output from a solid state image sensor to a television signal with a simple structure, thereby facilitating the reduction of the size, weight, power consumption and cost of the image pickup apparatus. A color filter, which has a plurality of color filter elements respectively facing light receiving elements of a solid state image sensor, modulates optical information so that an image pickup signal output from the solid state image sensor is composed of a luminance signal component and modulated color signal components, which are obtained by modulating, with two color-difference signals, two carrier waves having phases different from each other by .pi./2, the phases of the two carrier waves are different by .pi.

Abstract: A phase-locked loop circuit generates a clock signal synchronized with a color burst signal contained in a composite color picture signal. The phase-locked loop circuit contains a phase synchronization loop having a loop gain, extracts the color burst signal from the composite color picture signal, compares the phases of the generated clock signal and the color burst signal, and controls the phase of the generated clock signal to reduce the difference between the above phases. The phase-locked loop circuit further detects the vertical blanking signal, and reduces the loop gain for the duration of the vertical blanking signal. Alternatively, a horizontal synchronizing signal is used instead of the color burst signal. Another phase-locked loop circuit generates a clock signal synchronized with a reference clock signal based on first frequency information indicating a frequency of the reference clock signal.

Abstract: A burst gate pulse generator generates a burst gate signal representative of a time period during which a burst signal is present within an input composite video signal. Each period of the input composite video signal includes a horizontal synchronization pulse, a burst signal and a video information signal. The burst gate pulse generator detects the end of the horizontal synchronization signal and begins the burst pulse at the end of the horizontal synchronization signal. A timing circuit including a charge storage device and a charge delivery device controls the duration of the burst pulse. When the burst pulse is activated the charge delivery device begins building a charge across the charge storage device until a threshold value is reached. Once the charge stored across the charge storage device equals the threshold value the burst pulse is deactivated. During the time when the burst pulse is active, the burst signal will be present on the input composite video signal.

Abstract: A phase detector provides angular phase error measurements of the color burst component of a video input signal. Burst phase errors exceeding a given angular threshold are detected and the number occurring within a given period of time are counted. From the accumulated count, a noise indicating signal is derived and applied to a video picture processor for controlling a parameter of displayed images.

Abstract: A burst separator and slicer circuit separates the burst signal from an input composite video signal. Each period of the input composite video signal includes a horizontal synchronization signal, a burst signal and a video information signal. A burst gate pulse signal representing the presence of the burst signal within the input composite video signal is received by the burst separator and slicer circuit. During the burst period, when the burst gate pulse is active, the burst signal is extracted from the input composite video signal and converted to a square waveform. A differential pair and comparator circuit monitors the input composite video signal and compares it to a constant level reference voltage signal. A constant high voltage level is output when the burst signal is greater than the constant level reference signal. A constant low voltage level is output when the burst signal is less than the constant level reference signal.

Abstract: A digital amplitude and phase detector for detecting the amplitude and phase of a color burst digital signal used in television systems is provided. The detector comprises a phase lock loop circuit for detecting the phase of said color burst signal and for generating a synchronous constant amplitude sinusoidal signal; multiplying circuit for generating a product signal by multiplying the color burst signal by the constant amplitude sinusoidal signal, wherein said product signal has a high-frequency component and a low-frequency component having an amplitude substantially proportional to that of the color burst signal; and low pass filter circuit coupled to said multiplying circuit for filtering said product signal such that the high-frequency component is substantially suppressed relative to that of the low-frequency component. A video encoder using the digital amplitude and phase detector is also provided.

Abstract: When a continuous wave signal synchronized with a first color subcarrier signal is generated by a color subcarrier extracting circuit, a phase error detecting circuit, an A/D converting circuit, and a digital oscillating circuit from an analog video signal containing a first color sub carrier signal supplied to a first input terminal and a digital video signal containing a color signal component supplied to a second input terminal is converted by a digital video signal converting circuit into a composite video signal containing a carrier chrominance signal, a color signal component is converted into a carrier chrominance signal by using the continuous wave signal and a phase of a first color subcarrier signal contained in the analog video signal and a phase of a second color subcarrier signal of a composite video signal formed from the digital video signal are synchronized with each other.

Abstract: A chroma lock detector circuit monitors charge pump control signals within a phase-lock loop to determine when two input signals to the phase-lock loop are locked together in phase and generates an output signal which is active when the two input signals are locked together in phase and inactive when the two input signals are not locked together in phase. The charge pump control signals are generated in response to a difference in phase between the two input signals and will become inactive once the two input signals are locked together in phase. When the charge pump control signals are inactive for a predetermined period of time, the output of the chroma lock detector circuit is activated and will remain active until the charge pump control signals are again active. A current source is enabled when either of the control signals are active. The current source builds up a first level of charge on a first capacitor during the burst period.

Abstract: A color burst gate pulse forming circuit has a first counter, a second counter, a logic circuit, and a decoding circuit. The first counter counts a chrominance subcarrier supplied in a form of a clock. The second counter starts counting said chrominance subcarrier in synchronization with a horizontal synchronizing signal, and resets itself in a period longer than half a horizontal scanning period and shorter than one horizontal scanning period. The logic circuit controls the operating period of the first counter based on an output from the second counter and said horizontal synchronizing signal. The decoding circuit decodes a count output from the first counter, and outputs color burst gate pulses based on a predetermined count output.

Abstract: A phase-lock-loop circuit includes a digital-to-analog converter of the bit rate multiplier type. The input word to the converter is updated once each horizontal period of a television signal. Phase information contained in an output signal of the bit rate multiplier is obtained in one horizontal period and is retained for affecting the phase in the immediately following horizontal period.

Abstract: An oscillator includes a frequency-controllable clock generator, and a digital oscillator responsive to a clock generated by the clock generator for oscillating a data sequence at a period in proportion to the clock and also discretely controllable in accordance with a frequency switching signal.

Abstract: The present invention is a system for inexpensive phase coherent subcarrier generation. The subcarrier sequence has a fairly short periodicity (two lines), allowing a relatively short lookup table to hold coded values precisely representing the sampled subcarrier. A variety of modulation techniques may be employed to minimize the error between the reconstructed subcarrier sine wave and an "ideal" subcarrier sine wave. The SCH phase may be easily varied by using a different table of subcarrier sine wave values.

Abstract: An interactive audio-visual (A/V) transceiver is advantageously coupled to a television and/or telephone (T/T) cable, a TV, a video recorder (VCR), and other A/V devices. The A/V transceiver switches data between a program/service provider and the connected A/V devices. In one embodiment, the transceiver includes three primary modules, a main module including a CPU, a system bus, system memory, an infra-red (IR) control unit, an audio-visual bus, an A/V decoder, an A/V processor, and an A/V encoder, an A/V connect module including a number of tuner/demodulators and a switch, and an optional CD ROM module. The A/V transceiver hardware is complemented with an operating system and software program which supports the functions provided in the A/V user interface.

Abstract: A digital clock generation system provides both a digital composite clock and a digital component clock synchronized with an input synchronization video signal. The digital composite clock is generated from the burst portion of the input synchronization video signal, and the digital component clock is synthesized from the digital composite clock. A frame timing pulse is generated at regular intervals from the composite sync of the input video signal for resetting the digital component clock to establish a defined phase relationship between the digital composite and component clocks according to an offset constant.

Abstract: Chrominance signals of a digitized composite video signal are processed by including automatic phase control and automatic chroma control operations that use circuit elements that are concurrently available for both operations as well as for other signal processing operations. The automatic phase control operation calculates a phase error corresponding to a phase difference between a reference clock signal and a burst synchronization signal of the chrominance signal. The reference clock signal is generated in response to the phase error data, such that the phase error is minimized and the reference clock signal coincides with the burst synchronization signal. The automatic chroma control operation multiplies the chrominance signal by coefficient data corresponding to the difference between the chrominance signal and a reference value to generate a constant level chrominance signal.

Abstract: Composite video timing adjustments using digital resampling provides precise sub-pixel timing relative to a timing reference with a single video master clock. A digital resampler interpolates an input digital composite video signal as a function of a phase offset input which defines a fractional clock period of the video master clock derived from the timing reference. The sub-pixel offset digital composite video signal also may be adjusted by integer multiples of the video master clock period using a FIFO memory. The final timing adjusted digital composite video signal then is input to an analog reconstruction circuit to provide an output analog composite video signal that is precisely timed to the timing reference.

Abstract: The invention relates to a video signal memory equipment comprising a FIFO memory for storing video data of video signals, and a control unit for controlling writing and reading in the FIFO memory, wherein the control unit receives a horizontal synchronizing signal of video signal in video data writing action, writes a specified number of video data from the beginning of video data of brightness signals of the horizontal scanning period sequentially into the FIFO memory, and reads out the specified number of video data upon every input of horizontal synchronizing signal, in video data reading action, in the written sequence as video data of that horizontal scanning period, thereby storing and producing the video data of video signals, whereby video data of each horizontal scanning period of video signals are continuously written into the FIFO memory by every specified number of pieces from the beginning, and are read out by every specified number of pieces upon every input of horizontal synchronizing signal,

Abstract: In a video processing system, a burst signal generating circuit receives a discontinuous burst signal and generates a continuous burst signal by using a phase locked loop. In the conventional video processing system, it is difficult to select a loop gain and loop bandwidth for generating a burst signal, since the performance characteristics of a phase locked loop are directly influenced by the presence of a sample and hold circuit in the phase locked loop. In order to solve this problem, in processing a digital video, a discontinuous burst signal is detected, and then during a burst signal, the phase locked loop operates by the discontinuous burst signal detected so that the continuous burst signal may be generated. When the burst signal is not present, the phase locked loop operates by a constant error value according to the continuous burst signal shifted 90 degrees in phase. Thereby, the continuous burst signal is generated.

Abstract: A Y/C separation circuit includes a first adder by which a carrier-multiplexed composite video signal is produced by multiplexing a color sub-carrier signal which is in synchronization with a color burst signal on a composite video signal during a vertical blanking period. The carrier-multiplexed composite video signal inputted to a 1H delay line and outputted from the 1H delay line. The carrier-multiplexed composite video signals at the input and the output of the 1H delay line are inputted to a second adder, and a subtracter, respectively. A luminance signal component and a chrominance signal component are respectively outputted from the second adder and the subtracter.

Abstract: A secondary signal is processed and injected into a primary color video signal. The timing of the subsequent transmission of the secondary signal is controlled by timing signals. The timing signals also control the transmission of a carrier burst prior to the transmission of the secondary data signal. This carrier burst is used by a receiver to synchronize with the transmitter, reduce transmission errors and to indicate that a data transmission is to follow.

Abstract: A synchronous demodulator is controlled by a phase locked loop for tuning to a pilot in a television signal. A start-up interval is commenced upon initiation of tuning (either after power-up or a channel change) during which a substitute signal at the pilot frequency is supplied to the phase locked loop to rapidly bring the VCO close to its lock-up frequency. Thereafter the IF signal is supplied. The start-up interval is defined by an AFC Defeat signal from a microprocessor and controls an IF switch. The substitute signal is from a crystal oscillator.

Abstract: A synchronizing signal regenerating circuit for standard video signals in a digital video signal processing system includes a circuit for regenerating stable horizontal synchronizing signals, a circuit for generating double horizontal synchronizing signals, a circuit for generating horizontal synchronizing signals, a circuit for generating vertical synchronizing signals and an output circuit. The circuit for regenerating stable horizontal synchronizing signals regenerates the horizontal synchronizing signals in response to quadruple burst signals, and the circuit for generating double horizontal synchronizing signals is connected to the output terminal of the circuit for regenerating stable horizontal synchronizing signals. The circuit for generating horizontal synchronizing signals is connected to an output terminal of the circuit for regenerating stable horizontal synchronizing signals.

Abstract: Different from typical signal processing which employs a feedback control, by adopting a demodulating circuit employing AFC, which is not affected by a comb filter, the response characteristic against jitter is improved and a down converted chrominance signal can be demodulated with a good accuracy. Therefore, the noise rejection effect by a comb filter is improved, the detecting accuracy of the residual phase error is also improved, and the S/N ratio of the phase is improved by combining feedforward APC compensation with a velocity error, and this results in a much improved picture quality.

Abstract: A video signal processor comprising: a device defining a color pallet for converting a color code specifying the color of each pixel of a display picture into digital RGB color data; and a conversion system for converting the RGB color data into a luminance signal and two color-difference signals represented by analog values, wherein the conversion system includes: a memory storing digital values constituting a conversion system for converting the digital RGB color data into a luminance signal and two color-difference signals represented by digital values; and a digital-analog converter connected to the conversion system for converting the luminance signal and two color-difference signals represented by digital values into the luminance signal and two color-difference signals represented by analog values.

Abstract: A digital oscillator including an integrator for cumulatively integrating a specified signal and a controller responsive to a control signal for maintaining the output frequency of the integrator within a limit corresponding to the amplitude of the control signal.

Abstract: A method and an apparatus for sampling a reference signal so as to generate an error signal indicative of a phase error between an actual sampling phase and a desired sampling phase. The desired sampling phase is displaceable from an optimum sampling phase, so as to facilitate the sampling of an NTSC color burst signal or to effect hue control during sampling of the modulated chroma sub-carrier. The reference signal is sampled at the frequency of said signal and a plurality of said samples are accumulated. After said samples have been accumulated, said accumulation is multiplied by the sine or by the cosine of the phase displacement angle between the optimum sampling phase and the derived sampling phase.

Abstract: A method and circuit for preventing the deterioration of picture quality in a video processor is disclosed in which, when an input color video signal is input, a clock signal for a combfilter is locked with a phase-locked loop (PLL) by a burst signal and when a monochrome video signal without the burst signal is input, the clock signal is locked by the output (quasi-burst signal) of a voltage-controlled oscillator of the PLL circuit, before the lapse of one horizontal period, so that the clock signal is constantly locked by a multiple (4 fsc) of the burst signal regardless of the presence or absence of the burst signal of the input video signal. According to a color/mono signal discriminating result, either the burst signal or the quasi-burst signal is selected as a reference signal so that the reference signal is locked to provide a clock signal having a constant phase and frequency, thereby preventing aliasing due to clock variations when the monochrome signal is input and thus improving picture quality.

Abstract: A video signal processing device comprises: a unit for extracting a first color burst signal from a first video signal; a unit for generating a first subcarrier in synchronism with the first color burst signal extracted from the first video signal; a unit for extracting a second chrominance signal and a second color burst signal from a second video signal; a unit for demodulating the second chrominance signal and the second color burst signal on the basis of the first subcarrier to obtain a demodulated second color signal and a demodulated second color burst signal; and an operating unit for performing operation process of the demodulated second color signal on the basis of the demodulated second color burst signal in a manner such that the demodulated second color signal is converted into a corrected color signal which is substantially the same as an imaginal second color signal which is obtained on the assumption that the second chrominance signal is demodulated on the basis of a second subcarrier synchroni

Abstract: A burst phase correcting circuit includes a first all-pass filter which receives a chrominance sign inputted from a terminal. A phase reference signal from an oscillator is applied to a first phase-comparator together with an output signal from the first all-pass filter, after the same is phase-shifted by 90 degrees by a first phase-shifter. A signal according to a phase difference of the both signals is outputted from the first phase-comparator and applied to the first all-pass filter via a first low-pass filter and a capacitor. Therefore, in the first all-pass filter, a delay time is varied in accordance with the phase difference between the chrominance signal and the phase reference signal. Therefore, a jitter component of the chrominance signal can be removed.

Abstract: An analog-to-digital converter. The VCO 111 generates a sampling clock with a frequency four times that of a subcarrier. The A/D conversion circuit 103 converts an analog composite signal on the basis of the sampling clock thus generated. The BPF 113 extracts an input subcarrier from the digital composite signal. The local subcarrier reference generator 112 generates a local subcarrier. The multiplier 114 detects the phase differences between the input subcarrier and the local subcarrier. The averaging (I) circuit 115 averages consecutive 4 n phase differences. The averaging (II) circuit 116 further averages the averages thus obtained over a plurality of lines. The pulse generator 117 generates a pulse signal with a width corresponding to the averages thus obtained. The integrator 118 integrates the pulse signal thus generated thereby to control the oscillating frequency and phase of the VCO 111.

Abstract: An apparatus for recording a video signal onto tracks of a recording tape includes circuitry for producing a first time-base reference signal which is a color burst signal composed of a first predetermined number of sinewave cycles and a second time-base reference signal which is a burst signal composed of a second predetermined number of sinewave signals. The second predetermined number of cycles is larger than the first predetermined number of cycles. The apparatus further includes superimposing circuitry for superimposing the first time base reference signal on an input video signal at intervals of a horizontal scanning period of the video signal and for superimposing the second time base reference signal on the input video signal at intervals of a predetermined number of horizontal scanning periods of the video signal.

Abstract: A method and apparatus is disclosed for controlling the sampling of a composite analog color video signal so that the analog signal is sampled at precise locations relative to the phase of the color subcarrier of the color video signal in the absence of modulation. The invention thereby enables a digitized signal having a constant phase relationship relative to the unmodulated subcarrier phase to be provided which can be advantageously used in magnetic recording and reproducing apparatus. Since the constancy of the location of the samples relative to the phase of the color burst is maintained prior to recording, there is no phase error that would pose a problem during reproducing of the signal.