Abstract: A display device according to one aspect of the disclosure includes a liquid crystal panel, a backlight including at least one light source to irradiate light to the liquid crystal panel, a timing controller to scan, in each frame period based on a synchronization signal which is input, the liquid crystal panel at a scan rate faster than a frame rate based on the synchronization signal, and a backlight control unit to turn on the backlight till a second time point, which is a scan time point of a next frame, from a first time point when a specified time elapses from a time point in which scan of the liquid crystal panel is finished in each frame period.

Abstract: A monitoring apparatus includes a detection circuit, a filter circuit, an amplifying circuit, a regulation circuit, a delay and charging circuit, and a driving circuit. The detection circuit receives a video signal, and performs an operation to obtain an image signal from the video signal. The filter circuit obtains an average intensity of a luminance signal corresponding to the image signal. The delay and charging circuit charges an input capacitor when receiving a low level regulated signal from the amplifying circuit. The driving circuit activates an alarm when a charging voltage of the chargeable capacitor exceeds a predetermined value.

Abstract: A PLL circuit (1a, 1b) for generating a pixel-clock signal based on a hsync signal. The PLL circuit comprises a phase-frequency detector arranged to receive the hsync signal and a frequency divided pixel-clock signal, and generate up and down signals based on the hsync signal and the frequency-divided pixel-clock signal. A charge pump (20) is arranged to generate an output signal based on the up and down signals and a loop filter (30) is arranged to generate a frequency-control signal based on the output signal of the charge pump (20). Furthermore, a VCO (40a, 40b) is arranged to generate an oscillating signal and adjust the frequency of the oscillating signal in response to the frequency-control signal. The VCO (40a, 40b) is adapted to have a tuning range with a center frequency which is larger than or equal to 4 GHz.

Abstract: A frequency adjusting method comprises steps of: generating a first adjusting signal according to a frequency of a first output signal; adjusting a frequency of an input signal by using the first adjusting signal to generate the first output signal, so as to adjust the frequency of the first output signal into a first range; generating a second adjusting signal according to a frequency of a second output signal; adjusting the frequency of the first output signal by using the second adjusting signal to generate the second output signal, so as to adjust the frequency of the second output signal into a second range; and adjusting the first adjusting signal and the second adjusting signal according to the second adjusting signal.

Abstract: A synchronizing signal control circuit includes: a phase detecting section configured to detect a phase difference between a display synchronizing signal and an input synchronizing signal; an adding section configured to add a set value for setting a synchronization compensation period and the detected phase difference; a synchronization phase correcting section configured to correct the phase of the input synchronizing signal on the basis of the output signal of the adding section; a gate signal generating section configured to generate a gate signal representing the synchronization compensation period based on the display synchronizing signal; a synchronization determining section configured to determine whether the synchronization can be effected, by detecting whether the input synchronizing signal exists within the synchronization compensation period; and a selecting section configured to perform switching to the corrected input synchronizing signal on the basis of the determination result of the synchron

Abstract: Video signal processing systems and methods for detecting horizontal synchronization signals within video signals. Digital filtering methods are implemented for processing analog video signals to determine time varying characteristics of video signals to detect the starting and ending positions of horizontal synchronization pulses in a video signal with increased accuracy. In addition, adaptive methods are implemented for dynamically determining various video signal parameters over time, such as blanking level BL, threshold value (slice) level and synchronization level SL using information extracted from digitally filtered video signals.

Abstract: A clock generation apparatus is provided with a frequency phase error calculation circuit 120, whereby a clock synchronized with burst lock and a line lock clock can be simultaneously generated by a DTO 121 on the basis of frequency information of a DTO 10 and phase error information from a phase comparator 7 and a digital LPF 8. Therefore, the clock generation apparatus can cope with a system that required plural clocks, and frequency spread is easily carried out by generating spread information by a frequency spread information generation circuit 90, and adding it in the DTO 121. As a result, interference to a video terminal from the clock can be reduced, and performance of a video terminal such as a television receiver can be exploited.

Abstract: The invention is a circuit and method for automatically adjusting the phase and frequency of a pixel clock derived from analog image data. The circuit includes a phase locked loop circuit adapted to generate a phase locked loop clock responsive to a reference signal and an edge detector circuit adapted to generate an edge pulse signal corresponding to a transition of an analog data signal. A phase detector circuit is adapted to identify a phase of the phase locked loop clock associated to the transition of the analog data and thereby generate a phase adjust signal. A phase adjust circuit is adapted to generate a pixel clock by adjusting the phase of the phase locked loop clock responsive to the phase adjust signal.

Abstract: A video signal processor and a video signal processing method which can prevent the length of one period of a clock from being shortened and can output a video signal that is in phase with a reference signal. When a video data signal that has been processed using a first clock signal is processed using a second clock signal, this video signal processor does not utilize as the second clock signal, a clock signal that is in phase with a reference signal but a clock signal that is employed in a later stage signal processor, and interpolates the video data signal by an interpolation circuit so as to make the signal in phase with the reference signal.

Abstract: A first PLL circuit (100) receives a flyback pulse (VFB) as a reference signal and outputs a clock signal (CLK1), and a delay circuit (200) outputs a flyback delay signal (VFBD) having a predetermined delay time corresponding to the amount of horizontal movement on a screen. A second PLL circuit (300) receives a horizontal synchronizing signal (VHSYNC) and the flyback delay signal (VFBD) as a reference signal and a compared signal, respectively, and generates a horizontal drive pulse (VHD). A deflection yoke (12) receives the horizontal drive pulse (VHD) and generates a flyback pulse, and a step-down transformer circuit (16) outputs the flyback pulse (VFB) whose voltage is lowered. With this constitution, it becomes possible to generate a stable horizontal drive pulse which causes no jitter on the screen when a PIN balance correction, a KEY balance correction and a horizontal position adjustment of a CRT are performed by digital processing.

Abstract: An apparatus for generating a sync of a digital television in which an analog signal inputted to a digital television constantly provides stabilized synchronization regardless of a standard or a nonstandard so as to be processed.

Abstract: A PLL circuit according avoids any large change in a frequency in a VCO (5) even if an input horizontal synchronization signal suddenly changes or a level of the frequency decreases to a predetermined value or less, or disappears. The PLL circuit comprises a switch (3) to be provided on an output side of a phase comparator (2) to control an output voltage of the VCO by connecting to an AFC filter (4) and supplying a phase difference current according to a phase difference, during the time the horizontal synchronization signal is supplied. The comparator (2) compares a phase of an Hin signal through a delay circuit (1) with a phase of a return (RET) signal through a dividing circuit (6) and a delay circuit (7) from the VCO. With this structure, the comparator does not supply any phase difference current and does not make the VCO change at the time when the Hin signal is disappeared.

Abstract: A method is provided for generating a diversified-shaped image frame and fixing a keystone image frame problem. The method includes steps of repeatedly determining a specific pixel frequency of one of the plurality of image signal lines and outputting the one image signal line according to the specific pixel frequency until all of the plurality of image signal lines are outputted. A shape of the image frame is diversified by assigning diversified pixel frequencies to the plurality of image signal lines respectively.

Abstract: Disclosed is a HOUT position control circuit used to control the horizontal position of display image in a multisync monitor. The circuit has: a first PLL circuit that is phase-locked with input horizontal synchronous signal; a second PLL circuit that is phase-locked with output of the first PLL circuit; and a circuit for generating a delay between outputs of the first PLL circuit and the second PLL circuit to control the delay amount from the input horizontal synchronous signal to output horizontal drive signal.

Abstract: A method of recovering a pixel clock for generating a digital image from an analog video signal is presented. The on and off-transition times for the active video portion of a digital image and the image size defined in a video standard are used to generate a pixel clock. The analog video signal is digitized according to the pixel clock and the image size of the resulting digital image is compared with the image size defined in the video standard. The pixel clock frequency is adjusted in response to the image size comparison. The optimum phase of the pixel clock relative to the analog video signal is determined through a repetitive phase adjustment technique. A first image coordinate is determined for a pixel clock at one phase and a subsequent image coordinate is determined for a pixel clock after decrementing the phase of the pixel clock. The first image coordinate and the subsequent image are compared.

Abstract: A clock generation circuit for use in a television system displaying images encoded in television signals and images represented by network application data. The clock generation circuit generates a clock signal synchronized with HSYNC signals of the television signals. The clock generation circuit includes a phase-lock-loop (PLL) circuit and a tracking block. PLL circuit includes an oscillator (e.g., VCO) driven by an error signal to generate an internal periodic signal having frequency substantially equal to the frequency of the desired clock signal. The tracking block includes a resettable VCO (RVCO) driven by the error signal. A restart signal is asserted prior to the expected arrival time of the HSYNC edge to cause the RVCO to stop generating the desired clock signal. The restart signal is deasserted on receiving the HSYNC edge to cause the RVCO to start generating the clock signal. Accordingly, the clock signal is synchronized with the HSYNC signal.

Abstract: A digital horizontal flyback control circuit for controlling the horizontal position of a video signal on a monitor screen receives a horizontal drive signal (21) and a flyback signal (22) generated when a video display beam is caused to move from the end of one line of the display to the beginning of a next line by an edge of a pulse of the horizontal drive signal, the flyback pulse being delayed with respect to the horizontal drive signal pulse by a flyback delay period. A measuring circuit (15) measures the flyback delay period and a subtractor circuit (17) subtracts the flyback delay from a set horizontal position (18) representing a desired delay between the flyback pulse and a reference pulse (11). A comparator (19) compares the subtraction value with the value of a clock counter (23) whose count value is reset by the reference pulse (11) and produces a set signal at an output when the subtraction value and the clock count value are the same so as to generate the horizontal drive signal pulse (21).

Abstract: A control circuit (100) which receives horizontal synchronising pulses (265) and generates a horizontal drive output signal (455) for a cathode ray tube (CRT) display. The horizontal control circuit (100) generates two ramp signals. A first ramp signal (410) for horizontal position adjustment of an image on the CRT display, and a second ramp signal (440) for propagation delay compensation of a deflection circuit (155) coupled to the CRT display. The control circuit (100) also provides digital of control of the duty cycle of the horizontal drive signal (455).

Abstract: The invention presents a dot clock reproducing apparatus for automatically reproducing the dot clock easily, by setting the dot clock frequency of a video signal source, and correcting the phase difference of the dot clock occurring in the transmission route or the like, and also presents a dot clock reproducing method comprising, in dot clock reproduction, a step of sampling at a frequency different from the dot clock of video signal, a step of detecting the aliasing frequency component occurring at this time, and a step of reproducing the dot clock so as not to cause this aliasing frequency component, and as an apparatus employing such method, the invention further provides a dot clock reproducing apparatus comprising A/D converting means for receiving an adjusting signal delivered from a video signal source, and sampling this adjusting signal to convert into a digital signal, PLL means for dividing a specified synchronizing signal and generating a sampling clock for the A/D converting means, frequency anal

Abstract: A matrix addressable display includes a delay locked loop formed from a delay chain formed from several variable delay blocks and a comparator. The delay locked loop receives a horizontal sync portion of an image signal and propagates the horizontal sync through the chain of delay blocks. The output of the last delay block drives the comparator that also receives an undelayed horizontal sync component. The comparator compares the undelayed horizontal sync to the delayed horizontal sync component and produces an error signal corresponding to the phase difference. The error signal is input to each of the delay blocks. In response to the error signal, the delay of the respective delay blocks increases or decreases to reduce the phase difference between the undelayed horizontal sync component and the delayed sync component. In addition to driving the delay chain, the horizontal sync component also walks a "1" through a row driver to sequentially activate rows of the array.

Abstract: A horizontal synchronizing apparatus includes a source for providing a horizontal synch. signal, a horizontal deflection circuit for generating a deflection current having scanning intervals and blanking intervals repetitively successing in response to driving pulses and having retrace pulses which delay from the driving pulses as a function of a load on the horizontal deflection circuit, a phase locked loop having an input, an output and a first feedback path, for producing from the output a substantial bi-level signal synchronized to the horizontal synch. signal applied to the input, and a phase controlled loop having an input, an output and a second feedback path, for maintaining the retrace pulses synchronous with the bi-level signals.

Abstract: A first phase locked loop has an oscillator operating at a first frequency and synchronized with a video signal. A counter in the first phase locked loop generates a plurality of timing signals. A second phase locked loop has an oscillator operating at a second frequency, less than the first frequency, and synchronized with a first one of the timing signals. A switch in a controller selects one of the first and second frequencies as an output. A memory for the video signal has a write clock input coupled to the slower oscillator, a read clock input coupled to the switch, and write and read reset inputs coupled respectively to second and third ones of the timing signals. The controller operates the switch responsive to an input signal. An analog to digital converter has a clamp signal input coupled to a fourth one of the timing signals.

Abstract: Adjustment and maintenance of a phase relationship between a video signal and a scan synchronizing signal to assure proper horizontal centering is provided in a horizontal deflection system. A first phase locked loop generates a first timing signal at a first frequency, synchronously with a horizontal synchronizing component in a video signal. A presettable counting circuit operates synchronously with the first timing signal for dividing a clock signal to generate a second timing signal at a second frequency. A second phase locked loop generates a scan synchronizing signal from the second timing signal. A microprocessor may supply different numbers to a register, the output of the register being coupled to the presettable counting circuit. Different numbers change the relative phase between the first and second timing signals by incremental steps.

Abstract: There is disclosed a horizontal synchronizing signal generating circuit for generating a horizontal synchronizing signal which has no frequency variations and which is in phase with an entered composite synchronizing signal if the entered composite synchronizing signal is a nonstandard signal having a varying horizontal frequency. A horizontal counter circuit (5) counts a reference clock (V.sub.CL), and a window pulse generating circuit (4) outputs a window pulse signal (V.sub.W) which is low for a fixed time period when a counter output (V.sub.CT) equals a counter value (878) indicative of a standard output timing. A horizontal synchronizing signal separating circuit (1) outputs a horizontal synchronizing signal (V.sub.2) only when the composite synchronizing signal (V.sub.1) falls within the fixed time period. Then a horizontal phase judging circuit (2) outputs a standard signal flag (V.sub.3) and a synchronizing signal generating circuit (3) outputs the horizontal synchronizing signal (V.sub.

Abstract: A television receiver is subject to certain operational conditions which result in poor, unreliable or unusable separated sync pulse signals. During such conditions the use of unsuitable sync signals for synchronization and the like is inhibited to prevent mis-triggering or spurious synchronization. A television receiver contains circuitry for extracting a sync signal, a voltage controlled oscillator (VCO) for generating a scanning signal, and a comparator comparing the scanning signal to the separated sync signal. A microprocessor is used to verify the separate sync signal for invalid or unusable signals and has an output activated during such conditions. The phase comparator has a current output coupled to a integrating capacitor or LPF which develops a varying positive or negative voltage to raise or lower the frequency of the VCO for scanning in phase with the separated sync.