Abstract: An interface is realized that can prevent video signals from being copied easily and which uses a luminance/color difference signal transmission scheme with an excellent harmony with a television circuit. In a video transmission using a digital interface, colorimetry information for defining the conversion from the luminance/color difference signal into a primary color signal and video aspect ratio information are transmitted along with the luminance/color difference type video signal. This allows reproduction of video with high quality and high resolution and also realizes a copyright protection which allows only the users authorized by key information to use the content of the video. With this transmission scheme, it is possible to provide a transmitting apparatus, a receiving apparatus and an interface which highly harmonize with a rationalized television-based circuit.

Abstract: A pixel clock generator is provided. The pixel clock generator includes a phase-locked-loop (PLL) circuit that generates, from an oscillation signal having a first frequency of tens of MHz, a multi-phase oscillation signal having a second frequency of several GHz; and a frequency/phase adjusting circuit that synchronizes the multi-phase oscillation signal with a horizontal sync signal to generate a first oscillation signal, frequency-divides the first oscillation signal to generate a second oscillation signal, and adjusts a phase of the second oscillation signal to generate the pixel clock.

Abstract: A measuring device for measuring a response speed of a display panel is provided. The measuring device includes a microcontroller and at least one photo sensor. The microcontroller provides a control command, according to which a display controller of the display panel provides test pattern to the display panel. The photo sensor senses a test frame displayed corresponding to the test pattern by the display panel, and provides a corresponding sensing signal associated with brightness and a response signal. According to the response signal, the response speed of the display panel is calculated.

Abstract: A video signal output device and method are capable of easily displaying moving images while synchronizing transmission-side data and reception-side data even if video data is asynchronously transferred to the reception side from the transmission side. A video signal output device for receiving video data transmitted from a transmitter in sync with a first clock through a communication unit, storing the video data in a storage unit, reading the video data from the storage unit in sync with a second clock, and displaying moving images on a display unit, includes a synchronization adjustment unit for detecting a video data correction amount in accordance with a reference video data amount in one vertical synchronous period and a video data amount of the second clock in one vertical synchronous period to adjust a predetermined horizontal scanning period in accordance with the video data correction amount.

Abstract: A method of operating a pixel clock generator (PCG), the method including generating N clock signals according to a control voltage signal, the N clock signals having different phases and N being a natural number; generating M frequency-divided clock signals based on the N clock signals, the M frequency-divided clock signals having different phases and M being a natural number greater than N; and generating a pixel clock signal based on at least two selected ones of the M frequency-divided clock signals.

Abstract: A monitoring apparatus includes a detection circuit, a filter circuit, an amplifying circuit, a regulation circuit, a delay and charging circuit, and a driving circuit. The detection circuit receives a video signal, and performs an operation to obtain an image signal from the video signal. The filter circuit obtains an average intensity of a luminance signal corresponding to the image signal. The delay and charging circuit charges an input capacitor when receiving a low level regulated signal from the amplifying circuit. The driving circuit activates an alarm when a charging voltage of the chargeable capacitor exceeds a predetermined value.

Abstract: A PLL circuit (1a, 1b) for generating a pixel-clock signal based on a hsync signal. The PLL circuit comprises a phase-frequency detector arranged to receive the hsync signal and a frequency divided pixel-clock signal, and generate up and down signals based on the hsync signal and the frequency-divided pixel-clock signal. A charge pump (20) is arranged to generate an output signal based on the up and down signals and a loop filter (30) is arranged to generate a frequency-control signal based on the output signal of the charge pump (20). Furthermore, a VCO (40a, 40b) is arranged to generate an oscillating signal and adjust the frequency of the oscillating signal in response to the frequency-control signal. The VCO (40a, 40b) is adapted to have a tuning range with a center frequency which is larger than or equal to 4 GHz.

Abstract: A horizontal synchronization signal detection system includes a coarse period estimator and a fine period time estimator. The coarse period estimator estimates a minimum value and corresponding position of each period of a CVBS signal to calculate a coarse period of a horizontal synchronization signal. The fine period time estimator divides the horizontal synchronization signal into a first part and a second part so as to generate a first sum and a second sum by adding signals of the first part and the second part, and detects a middle point of the horizontal synchronization signal when the first sum equals the second sum. The steps of fine-tuning the coarse period to generate a fine-tuned coarse period, extracting the horizontal synchronization signal according to the fine-tuned coarse period, and determining whether the first sum is equal to the second sum are repeatedly executed until the first sum equals the second sum.

Abstract: A display control device includes an image data generating section and a control section. The image data generating section is configured to perform generation processing for generating image data in a predetermined processing sequence for each of a plurality of predetermined data units of the image data. The control section is configured to control a display unit to execute display processing based on the image data in the processing sequence for each of the predetermined data units. The control section is configured to control the display unit so that the longer a first time relating to the generation processing for one of the predetermined data units of the image data is, the longer a second time until the display processing starts for the one of the predetermined data units of the image data is.

Abstract: Provided is a video display device that quickly determines, when a video signal of unknown resolution is input from the outside, the resolution of the video signal to correctly display a video.

Abstract: A video device to generate analog video signals to a plurality of display devices comprises a video processing chip, a plurality of video output interface circuits and a plurality of detection circuits. The video processing chip converts input video data into the analog video signals and comprises at least one video decoder and a plurality of analog to digital convertors. The video output interface circuit transmits the analog video signals to the plurality of display devices. The detection circuit detects voltage of horizontal sync signals of the analog video signals to determine connection of the video output interface circuit to the display device, and generates a feedback signal to the video processing chip to control the video decoder and the analog to digital convertor accordingly.

Abstract: Systems and methods are disclosed for automatic gain control (AGC) for analog television signals using feed-forward signal path delay. Adjustments to the AGC frequency response are achieved by introducing an intentional delay in the signal path of sufficient length to allow time for measurement of a horizontal sync pulse level and for application of a feed-forward amplitude correction based upon this measurement to the same horizontal line.

Abstract: A method for recovering pixel clocks based on an iDP interface includes selecting a prime factor closest to VA or HA from prime factors of X, and selecting a value obtained by subtracting VA from the selected prime factor, as VB, in Mvid = ( HA + HB ) × ( VA + VB ) X , where HA indicates a horizontal active period, HB indicates a horizontal blank interval, VA indicates a vertical active period, and VB indicates a vertical blank interval, fixing the selected VB value, and selecting a total of HB within one frame period and the number of lanes under a condition that Mvid has an integer value, and recovering pixel clocks by multiplying a frequency of link symbol clocks of data received via the lanes by a multiplication of Mvid/48.

Abstract: A display apparatus includes a signal input unit through which an image signal is input, the image signal comprising a synchronization signal and an active signal; an adjustment signal generating unit that generates an adjustment signal; a signal processing unit that receives the adjustment signal and adjusts the image signal based on the received adjustment signal; and a controller which analyzes the input signal and controls the adjustment signal generating unit to change characteristics of the adjustment signal if the adjustment signal does not lie within a blanking interval between the synchronization signal and the active signal. With this configuration, even when an image signal having a reduced blanking interval between the synchronization signal and the active signal is input, the adjustment signal can be generated within the blanking interval of the image signal, not within the active signal interval.

Abstract: A method provides a bidirectional communication protocol for data communication between a first device and a second device. The method includes: during a first time interval, transmitting data from the first device to the second device; and during a second time interval, (a) after the occurrence of a first event, (i) suspending data transmission from the first device to the second device; and (ii) transmitting control data from the second device to the first device; and (b) after the occurrence of a second event, transmitting control data from the first device to the second device.

Abstract: A horizontal synchronization detection device includes a pulse detection portion that detects a pulse in a horizontal synchronization signal contained in a video signal and acquires a pulse width of the detected pulse, a synchronization pulse decision portion that determines the pulse satisfying a condition that a difference between its pulse width and a reference pulse width is within a first predetermined range as a synchronization pulse, a mean pulse width acquisition portion that averages out a pulse width of the synchronization pulse for each field and obtains a mean pulse width thereof, and a reference pulse width correction portion that determines, for each synchronization pulse in a current field, whether a difference between its pulse width and the mean pulse width in a previous field is within a second predetermined range, and corrects the reference pulse width and/or the first predetermined range based on the determination result.

Abstract: A method, and apparatus, and logic encoded in one or more computer-readable media to carry out a method. The method is to sample analog video at a sample clock rate and at a phase selected from a set of phases based on a quality measure determined from the sampled video. The quality measure is based on statistics of pixel to pixel differences in a coordinate of the generated digital video that have a magnitude exceeding a pre-determined threshold.

Abstract: Adjust a vertical blanking interval of a display horizontal synchronization signal, according to a difference between an external horizontal synchronization signal and the display horizontal synchronization signal, for synchronizing the display horizontal synchronization signal to the external horizontal synchronization signal. This only requires one or two frames to synchronize the display horizontal synchronization signal to the external horizontal synchronization signal, and will not cause the user to perceive display pauses or flickers.

Abstract: A horizontal synchronization signal detection system includes a coarse period estimator and a fine period time estimator. The coarse period estimator estimates a minimum value and corresponding position of each period of a CVBS signal to calculate a coarse period of a horizontal synchronization signal. The fine period time estimator divides the horizontal synchronization signal into a first part and a second part so as to generate a first sum and a second sum by adding signals of the first part and the second part, and detects a middle point of the horizontal synchronization signal when the first sum equals the second sum. The steps of fine-tuning the coarse period to generate a fine-tuned coarse period, extracting the horizontal synchronization signal according to the fine-tuned coarse period, and determining whether the first sum is equal to the second sum are repeatedly executed until the first sum equals the second sum.

Abstract: Pulse detection portion detects pulses in a horizontal synchronization signal and acquires the occurrence period and the pulse width of the detected pulses. Synchronization pulse decision portion determines pulses, for which the differences between the occurrence period and the reference period and between the pulse width and the reference pulse width are within their respective error tolerance ranges, as synchronization pulses. Mean period acquisition portion obtains the mean period by averaging occurrence periods of the synchronization pulses. Reference period correction portion carries out either or both of correcting the reference period so as to get closer to the mean period and correcting the error tolerance range of the reference period so as to get narrower, under the condition that the occurrence frequency of the synchronization pulses for which the difference between the occurrence period and the mean period is outside of a predetermined tolerance range exceeds a predetermined threshold.

Abstract: A multimedia device generates and outputs video signals to a display component and an external display device, and includes a video output circuit and a load detection circuit. The load detection circuit isolates and buffers the video output circuit and the load detection circuit, and retrieves horizontal sync signals from the video signals. The load detection circuit further amplifies and integrates the retrieved horizontal sync signals to output direct current signals, and finally compares the direct current signals with a predetermined voltage to output a control signal indicating a connection between the video output circuit and the external display device. The multimedia device turns off the display component according to the control signal indicating that the video output circuit has been connected to the external display device.

Abstract: A signal transmission system includes a transmitting device and a receiving device. The transmitting device includes a superimposition portion that superimposes at least one synchronizing signal on at least one video signal among a plurality of video signals, and outputs the synchronizing signal and the video signal as a superimposition signal to a receiving device. The receiving device includes a separation portion that separates the superimposition signal into the synchronizing signal and the video signal, a first adjustment portion that adjusts an amount of delay of the separated video signal to another video signal, and a second adjustment portion that adjusts an amount of delay of the separated synchronizing signal.

Abstract: A video horizontal synchronizer outputting a line timing signal and an indicating flag of a received video signal for use in a video signal post-processing unit, including a filter outputting a wide bandwidth filtered and a narrow bandwidth filtered signals of the received video signal, a dynamic slicer threshold generator generating a slicer threshold, a timing recovery circuit generating a phase error and the line timing signal, a phase error statistics circuit averaging the phase error to generate a average phase error, a HSYNC checker generating a matching flag indicating whether a periodic pattern appears in the narrow bandwidth filtered signal according to the line timing signal, and a finite state machine controlling the dynamic slicer threshold generator, the timing recovery circuit, the phase error statistics circuit and the HSYNC checker and generating an indicating flag when the average phase error is small enough and the matching flag is confirmed.

Abstract: A digital image converting apparatus with auto-correcting phase and a method thereof are provided. The digital image converting apparatus includes a phase controller, a delay locked loop (DLL), an analog-to-digital converter (ADC) and a position adjuster. The phase controller selects one of preset phases for outputting and continuously changes the output preset phase for controlling a clock signal produced by the delay locked loop. The ADC converts an analog display frame according to the adjusted clock signal. After all the preset phases are output in sequence, the phase controller can obtain an optimal phase for converting the display frame according to the smallest front porch of horizontal scan line and the smallest back porch of horizontal scan line of a digital display frame produced by the position adjuster.

Abstract: A synchronizing signal control circuit includes: a phase detecting section configured to detect a phase difference between a display synchronizing signal and an input synchronizing signal; an adding section configured to add a set value for setting a synchronization compensation period and the detected phase difference; a synchronization phase correcting section configured to correct the phase of the input synchronizing signal on the basis of the output signal of the adding section; a gate signal generating section configured to generate a gate signal representing the synchronization compensation period based on the display synchronizing signal; a synchronization determining section configured to determine whether the synchronization can be effected, by detecting whether the input synchronizing signal exists within the synchronization compensation period; and a selecting section configured to perform switching to the corrected input synchronizing signal on the basis of the determination result of the synchron

Abstract: A data recovery device and a method thereof for processing a television signal having a plurality of horizontal scan signals are disclosed. The data recovery device includes a reference level processing unit and a data processing circuit. The method for data recovery is by means of the reference level processing unit to generate a plurality of reference levels according to a reference component of each of the horizontal scan signals. And the data processing circuit is used to process the N+1th horizontal scan signal in accordance with the Nth reference level.

Abstract: A signal generator for use in producing a video top-of-frame signal based upon an input video signal with an input video frame including one or more input video fields and having an input video frame rate for an output video signal with an output video frame having a plurality of output video frame lines, each with a plurality of output video pixels, and an output video frame rate.

Abstract: A method and system of automatically correcting a sampling clock in a digital video system are disclosed. Sampling clocks with different phases are generated and subjected in turn to analog-to-digital conversion (ADC). A difference of at least a pair of neighboring data out of the ADC with respect to each phase is determined. A maximum difference is determined, and the sampling clock with the phase corresponding to the maximum difference is thus generated.

Abstract: In one embodiment, a method for synchronizing a plurality of video signals received from one or more video sources is provided. The method includes providing one or more video sources and providing a codec including an internal reference oscillator. The method also includes generating a plurality of horizontal and vertical synchronization pulses based on the reference frequency of the internal reference oscillator, generating a composite synchronization pulse based on the plurality of horizontal and vertical synchronization pulses, and transmitting the composite synchronization pulse to the one or more video sources via a communication link.

Abstract: A H-sync phase locked loop device for TV video signal is provided herein. After the TV video signal is digitalized, clamping and slicing operations are performed on the digitalized TV video signal to respectively generate a clamped signal and a sliced signal. According to the clamped signal and the sliced signal, an H-sync frequency calculator can calculate the falling and rising transients of the H-sync signal and an H-sync frequency is obtained therefrom. Because the H-sync frequency is dynamically adjusted according to the input TV video signal, the phase locking of the input TV video signal can tolerate more deviations of the H-sync by replacing a predetermined H-sync frequency.

Abstract: A circuit is used to process video signal from a video sensor. The video signal includes video content signal and synchronization signals. The circuit includes a status register, a data register, and a processor. The status register provides a sampling clock signal to the data register and the video sensor. The sampling clock signal is synchronized with the synchronization signals to sample the video signal. The status register stores the synchronization signals. The data register storing the video content signal. The processor is coupled to the status register and the data register. The processor reads the video content signal from the data register according to the synchronization signals in the status register.

Abstract: A driver for driving a display panel and a method for reading/writing in a memory thereof and thin film transistor liquid crystal display (TFT-LCD) using the same are provided. The method of the present invention is a reading timing of memory which different than the prior reading timing of memory, so that, if using the method of the present invention in the driver even having only one memory, the tearing effect of the prior TFT-LCD can be solved and the whole power consumption thereof can also be reduced.

Abstract: A signal synchronization device and signal synchronization method are provided. The method comprises determining whether a receiving device can receive data output from an output device synchronously and adjusting the dummy period of the signal, which will be received by the receiving device, when the data output from the output device cannot be received by the receiving device synchronously.

Abstract: An integrated video clock signal generator in which a master phase-locked loop (PLL) control circuit uses an off-chip voltage-controlled oscillator (VCO) to produce an on-chip oscillator signal in synchronization with a horizontal reference signal related to a horizontal video synchronization signal. This on-chip oscillator signal drives one or more slave PLL circuits which provide respective one or more on-chip PLL signals synchronized with the on-chip oscillator signal. In accordance with a preferred embodiment, each on-chip PLL signal is a pixel clock signal with a plurality of clock signal pulses which is synchronized with a vertical reference signal related to a vertical video synchronization signal.

Abstract: According to an aspect of the present invention, there is provided an electronic apparatus including: a detection unit configured to detect a start of a reproducing of a motion picture to be displayed on a display unit; a change unit configured to change a refresh rate of the display unit when the start of the reproducing of the motion picture is detected, the refresh rate being changed not by changing an operating frequency of the display unit, the refresh rate being changed by changing a blanking period, the blanking period being a period during which a drawing operation of a screen on the display unit is not performed; and a control unit configured to control the display unit to display the motion picture based on the changed refresh rate.

Abstract: A video horizontal synchronizer outputting a line timing signal and an indicating flag of a received video signal for use in a video signal post-processing unit, including a filter outputting a wide bandwidth filtered and a narrow bandwidth filtered signals of the received video signal, a dynamic slicer threshold generator generating a slicer threshold, a timing recovery circuit generating a phase error and the line timing signal, a phase error statistics circuit averaging the phase error to generate a average phase error, a HSYNC checker generating a matching flag indicating whether a periodic pattern appears in the narrow bandwidth filtered signal according to the line timing signal, and a finite state machine controlling the dynamic slicer threshold generator, the timing recovery circuit, the phase error statistics circuit and the HSYNC checker and generating an indicating flag when the average phase error is small enough and the matching flag is confirmed.

Abstract: An image signal processing device, which uses a horizontal synchronizing signal detector to find a frequency (period) of an original horizontal synchronizing signal from an external input horizontal synchronizing signal and provide an internal reference horizontal synchronizing signal with the same frequency same as the original horizontal synchronizing signal to a horizontal synchronizing signal output controller for determining to output the external input horizontal synchronizing signal according to the frequency of the internal reference horizontal synchronizing signal and filtering out the original horizontal synchronizing signal.

Abstract: A format of an inputted video signal is estimated to be based on the total number of vertical lines, and a frequency dividing ratio of a PLL unit is provisionally set at a predetermined value corresponding to the estimated format. Next, the frequency dividing ratio is calculated so that a measured value of a horizontal display width that is measured by a video detecting unit matches a capture width which is the horizontal display width capturable by a frame memory, and the calculated frequency dividing ratio is converted to a multiple of 4. A phase adjustment of the regenerative dot clock is performed against the video signal based on the converted frequency dividing ratio by using the regenerative dot clock generated by the PLL unit.

Abstract: A frame-based phase-locked display controller used in a display system and method thereof are described. The frame-based phase-locked display controller for displaying a plurality of image frames in a video signal comprises a frame-based phase-locked loop and a synchronization signal generator. The frame-based phase-locked loop receives an oscillating signal and an input vertical synchronous signal to generate an output clock signal by phase-lock loop based on the frames. The synchronization signal generator, coupled to the frame-based phase-locked loop, receives the output clock signal to generate an output horizontal synchronous signal, an output vertical synchronous signal and an output display enable (DE) signal. The frame-based phase-locked loop comprises a first PLL, a frequency synthesizer, a second PLL, a fast phase detector, a phase frequency detector and an active pixel region generator.

Abstract: A method is provided for accurately sampling pixels in a fixed-format display, which is connected to a host computer through an analog video display adapter. The method comprises the step of confirming that the fixed-format display is able to receive a pixel clock signal from the analog video display adapter. Another step is sending the pixel clock signal across an analog video sync line so that synchronization data and the pixel clock signal will be contained on the analog video sync line. An additional step is receiving the pixel clock signal in the fixed-format display. A further step is applying the pixel clock signal in the fixed-format display to sample pixels.

Abstract: We describe and claim a system and method for horizontal and vertical sync detection and processing. A method comprises detecting synchronization information within a video signal, estimating stability of the video signal according to the detected synchronization information, and generating one or more synchronization signals according to the detected synchronization information and the estimated stability of the video signal.

Abstract: Video signal processing systems and methods for detecting horizontal synchronization signals within video signals. Digital filtering methods are implemented for processing analog video signals to determine time varying characteristics of video signals to detect the starting and ending positions of horizontal synchronization pulses in a video signal with increased accuracy. In addition, adaptive methods are implemented for dynamically determining various video signal parameters over time, such as blanking level BL, threshold value (slice) level and synchronization level SL using information extracted from digitally filtered video signals.

Abstract: An apparatus, system, and method for determining an operational threshold level for distinguishing between video data and synchronization data in a video signal, are described herein.

Abstract: Apparatus and methods for synchronizing a plurality of image sensors in a video camera system. In one embodiment, a method includes generating a video sync signal, and resetting at least one internal clock divider in each image sensor in synchronization with the video sync signal at the beginning of each video frame. Another embodiment of a method of synchronizing a plurality of image sensors in a video camera system includes detecting a phase state of a signal of at least one internal clock divider in each sensor, wherein the phase state is relative to a system sync signal, and selecting a video output signal for each sensor based on the detected phase state of the at least one internal divider. In a third embodiment, the method includes asserting an asynchronous reset signal, stopping the system clocks in the system, de-asserting the asynchronous reset signal, while the system clocks are stopped, and restarting the system clocks.

Abstract: A system for overlaying a motion video signal onto an analog signal on a display. The system includes a motion video processing unit for receiving and processing the motion video signal into a signal having an analog video format, a video format analyzer and synchronizer device for receiving the analog signal and for determining video timing parameters and a corresponding original pixel clock of the analog signal and for controlling video timing parameters of the motion video signal to match the video timing parameters of the analog signal determined by the video format analyzer and synchronizer device so as to provide an output motion video signal which is synchronized with the analog signal and a display determining device for determining the display of the analog output signal or the synchronized output motion video signal on the display.

Abstract: A pedestal level of each of the R-Y and B-Y signals (color-difference signals) in a horizontal synchronization time T1 of a horizontal synchronizing signal is detected, and a pedestal level adjustment value for adjustment of the pedestal level of each of the R-Y and B-Y signals is determined based on the pedestal level determined in such a manner that a difference in pedestal level of each of the R-Y and B-Y signals between in the horizontal synchronization time T1 and in a horizontal scanning time T2 of the horizontal synchronizing signal is lessen. The pedestal level adjustment value determined is stored and video amplification-chroma circuit 130 adjusts the pedestal level of each of the R-Y signal and the B-Y signal in the horizontal synchronization time T1 of the horizontal synchronizing signal by an amount of adjustment value stored in.

Abstract: A method, apparatus, and system for determining a horizontal resolution and a phase of an analog video signal arranged to display a number of scan lines each formed of a number of pixels is described. A number of initialization values are set where at least one of the initialization values is a current horizontal resolution and then a difference value for each immediately adjacent ones of the pixels is determined. Next, an edge flag value based upon the difference value is stored in at least one of a number of accumulators such that when at least one of the accumulators has a stored edge flag value that is substantially greater than those stored edge flag values in the other accumulators, then the horizontal resolution is set to the current resolution.

Abstract: To acquire much accurate image information having no noise, without increasing load in the post-processing of the image information, a receiving apparatus 3 includes: a synchronization signal detector 34 that detects a horizontal synchronization signal and a vertical synchronization signal; an image processor 35 that performs an image generation process of each frame based on the horizontal synchronization signal and the vertical synchronization signal detected by the synchronization signal detector 34; and an image deletion controller 36a that controls to delete an image of the current frame, when a horizontal synchronization signal within one frame detected by the synchronization signal detector 34 is not continuously detected by a first predetermined number or more, or when a horizontal synchronization signal within one frame detected by the synchronization signal detector 34 is not detected by a second predetermined number or more, or when a vertical synchronization signal detected by the synchronization

Abstract: A display system comprising a video signal supplier supplying a video signal with a first video signal standard comprising a predetermined sync signal and a data range; a display apparatus supporting one of the first video signal standard and a second video signal standard comprising a sync signal and a data range which are at least being partially different to the first video signal standard and a data range being equal to the first video signal standard and outputting the video signal from the video signal supplier; a selector selecting the display apparatus supporting one of the first video signal standard and the second video signal standard; and a sync signal converter receiving a sync signal in the video signal from the video signal supplier according to a selection of the selector and converts the received sync signal into either the first video signal standard or the second video signal standard, which the selected display apparatus supports, to output the selected display apparatus.

Abstract: A method An apparatus and system for producing a digital video signal from an analog video signal, the analog video signal including an analog video data signal that is raster scanned in lines across a CRT screen to form consecutive frames of video information, the raster scanning controlled by use of a horizontal synchronizing signal (Hsnyc) (Hsync) that controls a line scan rate, and a vertical synchronizing signal (Vsnyc) (Vsync) that controls a frame refresh rate, to produce consecutive frames of video information, wherein the digital signal is produced by generating a pixel clock signal with pixel clocks for repetitively sampling instantaneous values of the analog video data signal, and digitizing the analog video data signal based on the pixel clock sampling.