Abstract: An exemplary apparatus for controlling display devices writes pixel data in a buffer in synchronous with an input clock signal. A differential value that represents a change of timing difference between input and output sides is calculated in each of a plurality of frames, and a timing correction based on the differential value calculated during the previous frame is performed within the vertical blanking period. Thereafter, the pixel data is read and output from the buffer to the display device in synchronous with an output clock signal.

Abstract: In an embodiment, there is provided a video processing component comprising a compensation engine configured to generate pixels of a first video frame from a second video frame based at least in part on specified pixel motion; and an access buffer configured to store pixel data corresponding to pixels of the second video frame for reference by the compensation engine, wherein the pixel data is stored by the access buffer at different vertical resolutions depending on vertical distances of the pixels corresponding to the pixel data from a target pixel that is indicated by the compensation engine.

Abstract: A monitoring apparatus includes a detection circuit, a filter circuit, an amplifying circuit, a regulation circuit, a delay and charging circuit, and a driving circuit. The detection circuit receives a video signal, and performs an operation to obtain an image signal from the video signal. The filter circuit obtains an average intensity of a luminance signal corresponding to the image signal. The delay and charging circuit charges an input capacitor when receiving a low level regulated signal from the amplifying circuit. The driving circuit activates an alarm when a charging voltage of the chargeable capacitor exceeds a predetermined value.

Abstract: An image processor includes a memory calculating unit, a storing unit, a mode selecting unit, and a Retinex process performing unit. The memory amount calculating unit calculates, based on an original size of an original image having an original pixels, a required memory amount required for performing a Retinex process on the original image. The storing unit has a usable memory area that can be used in performing the Retinex process on the original image. The usable memory area has a usable memory amount. The mode selecting unit selects a mode from among a plurality of modes based on both the usable memory amount and the required memory amount. The Retinex process performing unit performs the Retinex process on the original image in the selected mode.

Abstract: A method, and apparatus, and logic encoded in one or more computer-readable media to carry out a method. The method is to sample analog video at a sample clock rate and at a phase selected from a set of phases based on a quality measure determined from the sampled video. The quality measure is based on statistics of pixel to pixel differences in a coordinate of the generated digital video that have a magnitude exceeding a pre-determined threshold.

Abstract: A method of sampling phase calibration and a device thereof is suitable for an analog-to-digital converter and phase lock loop (ADC-PLL). The ADC-PLL conducts sampling on a periodic analog signal according to a sampling phase so as to produce a plurality of digital signals. The sampling phase calibration device includes a storage unit, a motion-detecting unit and a control unit. The motion-detecting unit is to calculate the number of motion data corresponding to a sampling phase. The control unit is coupled to the motion-detecting unit for changing the sampling phase so as to obtain the number of motion data corresponding to each sampling phase and selecting the sampling phase corresponding to the minimum number of motion data as an optimal sampling phase. The ADC-PLL can correctly sample an analog signal by using the optimal sampling phase and reduce the influence of clock jitter to the minimum.

Abstract: A video horizontal synchronizer outputting a line timing signal and an indicating flag of a received video signal for use in a video signal post-processing unit, including a filter outputting a wide bandwidth filtered and a narrow bandwidth filtered signals of the received video signal, a dynamic slicer threshold generator generating a slicer threshold, a timing recovery circuit generating a phase error and the line timing signal, a phase error statistics circuit averaging the phase error to generate a average phase error, a HSYNC checker generating a matching flag indicating whether a periodic pattern appears in the narrow bandwidth filtered signal according to the line timing signal, and a finite state machine controlling the dynamic slicer threshold generator, the timing recovery circuit, the phase error statistics circuit and the HSYNC checker and generating an indicating flag when the average phase error is small enough and the matching flag is confirmed.

Abstract: A display timing generator is provided for selecting line types and providing synchronization timing signals for video signals. The display timing generator provides programmability for the user to select line types for a frame to be displayed on a display. The line types defining rise and fall times, synchronization shapes, blanking levels and horizontal and vertical timings for providing a desired display format to different display types. A plurality of programmable parameters for pulse width, horizontal timing and voltage amplitude allow a user to define timing variations associated with a given line type. The display timing generator also includes a generic mode for allowing a programmer to select line types for particular groupings of lines.

Abstract: The present invention is directed to a display device such as a liquid crystal display including: a horizontal clock counter and a vertical clock counter which count each clock signal every horizontal cycle and every vertical cycle for a valid data period of a data enable input signal; and an input signal generating section for holding a count value and generating an input signal in a driver IC and a driving circuit corresponding to a resolution of the display device which is obtained at that time by utilizing a count value held at a last time for a next horizontal cycle or a next vertical cycle, the display device being applicable to the driver IC and the driving circuit which can be used for the display device having various resolutions.

Abstract: The present invention is directed to a display device such as a liquid crystal display including: a horizontal clock counter and a vertical clock counter which count each clock signal every horizontal cycle and every vertical cycle for a valid data period of a data enable input signal; and an input signal generating section for holding a count value and generating an input signal in a driver IC and a driving circuit corresponding to a resolution of the display device which is obtained at that time by utilizing a count value held at a last time for a next horizontal cycle or a next vertical cycle, the display device being applicable to the driver IC and the driving circuit which can be used for the display device having various resolutions.

Abstract: A method and apparatus for converting a digital video signal, to a signal having a resolution that matches a display device, by using simple hardware alone. When a digital video signal is input together with a data enable (DE) signal and a dot clock (DCLK) signal, the number of clocks of the DCLK signal generated during an active period of the DE signal is counted and, based on the thus counted number of clocks, the resolution of the input video image is identified; then, based on the resolution thus identified, the pixel density of the input video signal is converted so as to form a video signal having a resolution that matches the display device. Alternatively, the resolution of the input video signal may be identified by counting the number of pulses of the DE signal generated during one vertical synchronization period.

Abstract: An apparatus displays pictures from sources having a plurality of horizontal frequencies. A scanning generator is operable at the plurality of frequencies and comprises an oscillator generating a signal. A divider with two selectable counts is coupled to the oscillator and divides the signal by a first count to generate a horizontal drive signal. A horizontal scanning amplifier generates a scanning signal responsive to the horizontal drive signal coupled thereto. A controller is coupled to the scanning amplifier and to the divider. In response to selecting another of the plurality of frequencies, the controller monitors the scanning signal and responsive to its presence inhibits selection of a second of the selectable counts. In the absence of the scanning signal the controller enables selection of the second of selectable counts and the divider generates a horizontal drive signal representative of the another one of the plurality of horizontal scanning frequencies.

Abstract: A video display apparatus for pictures from broadcast sources having standard or high definition, which may also display computer generated images. To display this range of sources a horizontal frequency signal generator is selectably operable at a plurality of frequencies. The generator comprises an oscillator controlled for synchronized oscillation at a plurality of horizontal frequencies. A source of synchronizing pulses is coupled to an input of a phase detector which has another input coupled to the oscillator. The phase detector generates an output signal representative of a phase difference between the inputs. A processor is coupled to the phase detector for processing the output signal and generating a control signal for controlling the oscillator. The processor gain is controlled responsive to selected ones of the plurality of frequencies.

Abstract: A clock generation circuit for use in a television system displaying images encoded in television signals and images represented by network application data. The clock generation circuit generates a clock signal synchronized with HSYNC signals of the television signals. The clock generation circuit includes a phase-lock-loop (PLL) circuit and a tracking block. PLL circuit includes an oscillator (e.g., VCO) driven by an error signal to generate an internal periodic signal having frequency substantially equal to the frequency of the desired clock signal. The tracking block includes a resettable VCO (RVCO) driven by the error signal. A restart signal is asserted prior to the expected arrival time of the HSYNC edge to cause the RVCO to stop generating the desired clock signal. The restart signal is deasserted on receiving the HSYNC edge to cause the RVCO to start generating the clock signal. Accordingly, the clock signal is synchronized with the HSYNC signal.

Abstract: A scan converter receives VGA or SVGA graphics data and outputs NTSC or PAL TV data. The scan converter is integrated inside a personal computer's graphics controller, allowing the digital-to-analog converter (DAC) to be used for either CRT-pixel conversion or TV encoding. The VGA timing is altered to better match with TV scan-conversion. The horizontal rate is not constant but can be increased or decreased during the vertical blanking period. A second register is provided for the total number of pixels in a line during vertical blanking, while a first register contains the total number of pixels in a displayable line not during the vertical blanking period. Since lines with fewer pixels require less time to display, the period of time or rate for blanked lines is changed. An extra horizontal line is added during vertical blanking for every second frame for SVGA conversion to better match the asymmetry of TV standards.

Abstract: A circuit arrangement for automatically recognizing the line number of a video sync signal in accordance with the 525 or 625 line standard, this circuit arrangement automatically generating a control signal corresponding to one of the relevant line numbers. To recognize the line number, a line counter (14) clocked with horizontal frequency pulses is provided, this line counter receiving the frame-frequency sync pulse signal as a reset signal. Moreover, a decoding stage (15) is arranged at the output of the line counter (14), which supplies a signal for changing the line standard hitherto used and a signal characterizing the corresponding line standard. In a subsequent signal evaluation circuit (16), these two signals are checked and a control signal either corresponding to the current line standard or to the new line standard is applied to the output (17).

Abstract: A display apparatus capable of receiving and displaying video signals which differ in scanning frequencies or resolutions. The display apparatus includes an input section for receiving at least one video signal and a conversion unit for converting at least one of the frequency and resolution of the at least one received video signal so as to be within predetermined higher ranges thereof. A display unit enables display of the converted received at least one video signal.

Abstract: Disclosed is a horizontal oscillation circuit for a monitor performing a stable oscillation even at the start input such as a power input or a mode change. The horizontal oscillation circuit for a monitor includes an operation voltage delaying part for delaying a time period for an operating voltage to reach a voltage level and for outputting a delayed operating voltage, and a horizontal oscillator for inputting the voltage corresponding to the operating mode, the horizontal synchronizing signal and the delayed operating voltage and for outputting a stable oscillation voltage corrresponding to the operating mode. With an output of a stable oscillation voltage from the horizontal oscillation circuit, the horizontal output circuit of a monitor can be protected from being damaged by heat and a stable display can be obtained even at the start input such as a power input or a mode change.

Abstract: An apparatus for automatically synchronizing a video system to one of a plurality of composite synchronizing signals in accordance with a plurality of known video formats, includes a number of synchronizing signal stripper circuits, corresponding, respectively, to a number of types of composite synchronizing signals, a horizontal analyzer, having a plurality of horizontal standard identification circuits corresponding to a identification circuits for each known horizontal synchronizing signal rate for each type of composite synchronizing signal, for determining an approximate horizontal synchronizing signal rate and, a vertical analyzer, having a plurality of vertical rate identification circuits corresponding to the number of different known vertical rates, for determining the vertical synchronizing signal rate.

Abstract: Apparatus and method for automatically adjusting a picture size of a video appliance such as a monitor. According to the apparatus and method, since electrical characteristic data of the video appliance employing the apparatus of the present invention is preset therein, regardless of input of any external data, a user's one time input or automatic picture-adjusting mode selection makes external input data and preset characteristic data be compared, and the horizontal and vertical picture size of the video appliance in the video appliance is automatically adjusted. Therefore, the adjusting step is simplified in the manufacturing process of monitor, promoting productivity, and decreasing the cost thereof.

Abstract: A circuit arrangement for the digital identification of television transmission standards, particularly PAL, SECAM and NTSC. Provision is made for transmission standard demodulation stages connected in parallel to which a signal composed of a chromaticity signal and a synchronizing character is directed and which are each cyclically activated by control signals for a certain period of time. A trigger is also provided, together with an up-down counter, a circuit arrangement for the evaluation of the value delivered by the up-down counter, and a control logic.

Abstract: The synchronized transformer-coupled power supply circuit includes a transformer 20; an input power signal coupled to a primary winding 22 of the transformer 20; voltage regulators 48-53 coupled to secondary windings 24 and 26 of the transformer 20; and a start-up circuit 10 for coupling the input power signal directly to one of the voltage regulators 48-51 until the transformer 20 reaches a desired operating level.

Abstract: A control circuit for use with a phase locked loop in a digital video receiver. The digital receiver accepts a serial digital input signal which can comprise composite or component video signals. The phase locked loop comprises a phase detector, a loop filter, and a voltage controlled oscillator (VCO) and includes a divide-by-two modulus divider coupled to the output of the VCO. The VCO has an oscillation frequency control port and the divider has a frequency select port. The control circuit includes an automatic fine tuning and frequency sweeping stage which is coupled to the output of the loop filter and the oscillation frequency control port. The tuning and frequency stage provides temperature drift correction for the VCO. In addition, the tuning and frequency stage "sweeps" the oscillation frequency of the VCO to aid in "locking" the phase locked loop to the phase or frequency of the input signal. Once locked, timing signals and digital data can be extracted from the input signal.