Abstract: A video display for a television apparatus has a wide format display ratio and is synchronized with a first video signal representative of first picture. A PIP processor is responsive to a second video signal representative of a second picture to define an auxiliary picture smaller in size than the video display. A FIFO line memory stores successive lines of video information representative of the auxiliary picture, which are combined with certain successive lines of video information representative of the first picture. A counter initialized at a time corresponding to the start of each horizontal line of the first video signal generates a variable time delay. A FIFO control circuit successively initiates a transfer of the lines of video information representative of the auxiliary picture from the line memory for combination with the video information representative of the main picture after the variable time delay.

Abstract: A television receiver system having PIP capability includes two NTSC tuners and signal processing arrangements, and an HDTV tuner and signal processing arrangement. In order to accomplish a CHANNEL SWAP function, a controller searches a table for data indicative of pairing of NTSC channels and HDTV channels, the NTSC channel associated with the main channel HDTV source is tuned by the PIP NTSC tuner, and the HDTV channel associated with the PIP NTSC source is tuned by the HDTV tuner. If the inset image has no paired HDTV channel then the second NTSC tuner is controlled to select the channel formerly tuned by the PIP NTSC tuner.

Abstract: A video display system comprising: a first source of a first video signal representative of a first picture having a first display format ratio; a first memory having write and read ports, the first video signal being written into the first memory at a slower rate than the first video signal is read from the first memory, at least one of the ports of the first memory being selectively disabled to reduce the first display format ratio; a second source of a second video signal representative of a second picture having a second display format ratio; a video display having a wide display format ratio and synchronized with the first and second video signals; a second memory having write and read ports, the second video signal being written into the second memory at a slower rate than the second video signal is read from the second memory, at least one of the ports of the second memory being selectively disabled to reduce the second display format ratio; and, a multiplexer coupled to the first and second memories,

Abstract: A picture overlay system assures proper size and placement of picture overlays in simultaneous picture displays. The system comprises a video memory and a control circuit for writing and reading information from a video signal into and out of the video memory, the information relating to video data and field type. A reading circuit supplies information from the video memory synchronously with a display for another video signal. An interpolator selectively compresses and expands the information read from the reading circuit. The field type information undergoes the compression and expansion together with the video information. A decoding circuit decodes the field type information to identify first and second types of fields and an absence of valid video data. A multiplexer combines the video signals for simultaneous display, operating responsive to the decoding circuit.

Abstract: A video display system comprises: a video display; first and second signal processors for cropping first and second video signals representative of first and second pictures; a circuit for generating a side-by-side display format of the pictures on the video display; and, a panning control circuit, responsive to panning command signals, for positioning said pictures in the side-by-side display format and for independently panning the pictures, as positioned. The panning control circuit generates independent fixed and variable delays for controlling line memories in the signal processors. Fixed delays control picture positions and variable delays control panning.

Abstract: A display apparatus comprising a field frequency converter for converting the field frequency of a parent-picture video signal; an aspect ratio converter for converting the aspect ratio of the video signal after the field frequency conversion; a child-picture processor for generating a child-picture video signal; and a switch for synthesizing the aspect-converted video signal with the video signal obtained from the child-picture processor. In one embodiment, the storage capacity of a memory required in the field frequency converter can be minimized. The apparatus further comprises a selector for selecting either the parent-picture video signal of the second aspect ratio or the parent-picture video signal of the first aspect ratio which has been converted to the second aspect ratio, wherein merely one switch is sufficient for synthesizing the video signal obtained from the child-picture processor with the selected parent-picture video signal of the second aspect ratio.

Abstract: First and second field type detectors for first and second video signals have outputs indicating whether the video signals have first or second field types. The first video signal is synchronized with the second video signal for a combined display by a synchronous field memory and an asynchronous multiple line memory. The field type of the second video signal is changed when necessary to match the field type of the first video signal to maintain interlace integrity in the combined display. A field type changing circuit, which controls the synchronizing, has a first mode of operation which delays writing a current field of the first field type by one horizontal line period, a second mode of operation which advances writing a current field of the second field type by one horizontal line period and a third mode of operation which maintains a current field type.

Abstract: In a method for picture-in-picture insertion, successive frames of a small picture to be inserted into a main picture having successive frames are alternatingly written frame-wise into a memory region of a memory device. A decision signal is generated at a beginning of a display of the main picture, for deciding from which of the two memory regions a stored frame of the small picture is to be read out. Frames of the small picture are read out from whichever memory region enables joint-line-free insertion of the small picture into the main picture.

Abstract: An index scan apparatus and the method thereof applied to a video tape recorder. Video signals corresponding to one screen among reproduced video signals are stored whenever an index signal is detected during the reproducing mode, and video signals received during the setting of an index scan mode are displayed into a main screen and video signals stored on the memory corresponding to the detected index identification data are displayed by a plurality of subscreens. Thus, the user is easily able to find the desired program from among the programs recorded on a magnetic tape.

Abstract: A method and an apparatus for converting a video signal having a predetermined aspect ratio into a signal adapted for a television receiver having a wider aspect ratio. An analog to digital converter converts the received video signal into a digital signal. A main picture processor converts the video signal of the first aspect ratio into a main screen of the television receiver. A picture-out-picture processor converts the video signal having the first aspect ratio into at least one picture-out-picture screen of the television receiver. A multiplexed picture formation portion multiplexes the video signals for the main and picture-out-picture screens into a video signal having the second aspect ratio appropriate for the television receiver. A control signal generator controls the picture-out-picture processor and the multiplexed picture formation portion.

Abstract: A line memory and control system comprises a line memory, for example a first in first out (FIFO) device. A comparator compares a first value, specifying a location in the horizontal line period where reading or writing of the line memory is to begin, with a second value, fixing pixel location within each line period. A register stores the number of data samples stored in the line memory. A counter counts the number of data samples which have actually been written into the line memory or read from the line memory. The counter has an output of the comparator as a first input and the number of data samples previously stored in the line memory as a second input. In the case of both compression and expansion, a line memory control system assures that the number of samples written into each FIFO line memory be the same as the number of samples read out of each FIFO line memory.