Abstract: CRT control apparatus for use in high-resolution graphic display equipment of the type including a frame buffer having storage banks for storing digital signals representing the color intensities of red, green and blue colors of pixels on the CRT screen. The control apparatus is formed in a single MOS integrated-circuit (IC) chip which incorporates three multiplexers for the three 8-bit sets of color digital signals from the frame buffer. The 8-bit outputs of the multiplexers are directed to digital-signal-transformation devices which, in response to each 8-bit signal, produce a corresponding 10-bit signal incorporating the color-intensity information of the original 8-bit signal, and also incorporating a gamma correction factor for the particular intensity represented by the original 8-bit signal. The 10-bit signals are directed to 10-bit DACs, one for each color, to produce corresponding analog control signals for the corresponding electron guns of the CRT.

Abstract: A composite signal which comprises a video signal situated in the base band and a frequency-modulated audio signal situated outside the base band is coded by an N-bit pulse code modulator or an N-bit noise-shaped pulse code modulator with inadequate quality for, for example, N<5 (in particular for N=1) because, after modulation, demodulation and decoding, the video signal is found to affect the audio signal if, as is usual, the amplitude of the video signal is, for example, ten times greater than the amplitude of the frequency-modulated audio signal. If the amplitude of the video signal is not more than five times greater (in the ideal case one and a half times greater) than the amplitude of the frequency-modulated audio signal, the effect mentioned is apparently considerably reduced.

Abstract: A video signal AGC circuit including an analog gain control amplifier for adjusting the level of an input analog video signal; an A-D converter for converting the output of the analog gain control amplifier to a digital video signal; a sync level detector for detecting the sync level of the digital video signal outputted from the A-D converter; a digital gain control amplifier for adjusting the level of the digital video signal outputted from the A-D converter; a first control signal generator for generating a first control signal to adjust the gain of the analog gain control amplifier on the basis of the output of the sync level detector; and a second control signal generator for generating a second control signal to adjust the gain of the digital gain control amplifier on the basis of the output of the sync level detector.

Abstract: In a computer system having a frame buffer, apparatus for providing an overlay for the frame buffer, and a digital-to-analog converter for furnishing analog signals from the frame buffer to a pedestal setup display monitor, the digital-to-analog converter including apparatus for furnishing a blank level substantially below the lowest level of the analog signal desired to be visible on the monitor during retrace periods when used with a pedestal setup display monitor, the improvement including apparatus for allowing the system to utilize zero setup display monitors including apparatus for disabling the apparatus for furnishing a blank level when the computer system is used with a zero setup display monitor, and apparatus for causing the apparatus for providing an overlay for the frame buffer to furnish signals indicating a black level during retrace periods when the computer system is used with a zero setup display monitor.

Abstract: A time base corrector includes a main memory, a sub memory, and a passing detection circuit for generating a passing detection signal on the basis of the frequency difference between a write reference signal and a read reference signal. A memory control circuit controls the main and sub memories so that a field image immediately prior to a field in which passing will occur is written into both the main and sub memories. The written field image is read out from the sub memory when the field in which passing will occur is processed. Alternatively, the memory control circuit performs switching between a normal mode and a slip mode on the basis of the passing detection signal. In the normal mode, only the main memory is used. In the slip mode, both the main memory and the sub memory are integrally used for writing and reading of the video image.

Abstract: A binary to unary decoder for a video digital to analog converter is cascadeable in both a horizontal and a vertical direction. Video data is transmitted from a video data source and received by a plurality of unary decoders which convert the video data to a corresponding number of unary digits having comparable value. The unary decoders are arranged in a number of cascaded levels. A plurality of cascaded unary block drivers receive the unary digits and transit unary output digits to a video data bus. The plurality of unary block drivers are arranged in a number of tiers having a predetermined number of individual unary block drivers. The predetermined number of cascaded unary block drivers are enabled based upon the numerical value of the video data.