Abstract: An apparatus and method for adaptively varying a black stretch control range and a gain according to a mean level of a video signal to control black stretch of the video signal. According to the apparatus and method, the slope and range of black stretch are varied depending on the mean of the input video signal, so black stretch compensation can be adaptively performed depending on the brightness of a screen. Particularly, black stretch compensation can be effectively performed on a dark screen.

Abstract: An apparatus, system and method for clamping a video signal input to a coupling capacitor (215) for providing a clamping voltage. A charging current is applied to the capacitor (215) via an amplifier (225) having a first input (227) coupled with the capacitor output and a second input (226) coupled to a reference potential, the amplifier (225) is responsive to the capacitor output signal and the reference potential for providing the charging current to the capacitor (215). The current has a linearly varying magnitude which is proportional to a difference between the capacitor output and the reference potential.

Abstract: The object of the invention is offering an external output video signal processor, which does not need coupling capacitor or clamping circuit. A system controller outputs a video signal by which the sync. tip level and the pedestal level were fixed to a predetermined value. It was considered as an external output video signal processor which carries out direct input of the video signal output to the video signal processing circuit from the system controller, and is characterized by providing a level shift circuit which adjusts the level and is sent to said latter part processing circuit.

Abstract: A method and apparatus for adjusting the amplitude and DC bias of a video signal is presented, which may be performed in preparation for analog-to-digital conversion. This is accomplished by first converting a received voltage mode video signal to a current mode video signal. Similarly, a voltage mode bias control signal is converted to a current mode bias control signal. The amplitude of the current mode video signal is then adjusted to produce an amplitude adjusted video signal. Similarly, the amplitude of the current mode bias signal is adjusted to produce an amplitude adjusted bias control signal. The current mode amplitude adjusted signals are then combined to produce a biased adjusted current mode video signal. The biased adjusted current mode video signal is then converted back to a voltage mode signal, which may be provided to an analog-to-digital converter for conversion.

Abstract: A method and apparatus within a television receiver for electronically aligning signals within the receiver by controlling support circuitry for an IF module. A video amplifier is coupled to an output of the IF module. A control voltage source (DAC 114) controls a DC level control circuit within the video amplifier (244) such that the video signal is amplified and DC level shifted to align the video signal with down stream circuitry.

Abstract: An AGC circuit (70) amplifies a video signal according to again value output from again setting circuit (56). A clamp circuit (72) performs clamping of the direct current level of an output signal from the AGC circuit (70) at a clamp ability level according to a time constant set by a clamp time constant setting circuit (58). The clamp time constant setting circuit (58) receives input of the gain value generated by the gain setting circuit (56). A comparator circuit (120) compares the received gain value to a reference value, and, when the gain value exceeds the reference value, outputs a relatively large time constant. The clamp ability level of the clamp circuit (72) is controlled according to this time constant. In this manner, when the gain value is large, gradual clamping can be executed so as to minimize the influence of noise components superimposed on the direct current level, thereby suppressing transverse noise.

Abstract: The invention teaches a method, means and apparatus for clamping a back porch interval of a video signal including clamping a sync-tip level of said video signal to a variable reference voltage (33), comparing a back-porch voltage level of the sync-tip clamped video signal to a predetermined reference voltage (22), generating an error signal (24) representative of the difference between the back-porch voltage level and the predetermined reference voltage (22), and adjusting the variable reference voltage (33) in response to the error signal (24) such that the error signal (24) is minimized.

Abstract: A clamping circuit disclosed herein has two modes of operation which include both a bottom level and mid-level clamping mode for clamping automatically onto the sync tip of a video signal and customizably clamping onto the front porch, back porch/pedestal or anywhere within the signal. The clamping circuit (400) includes a clamping capacitor (404) that couples to an automatic clamping circuit portion (405) to automatically clamp the synchronization pulse of the video input signal to a first predetermined reference voltage (Vref1) of a first clamping pulse signal during an automatic clamping mode of operation. The automatic clamping portion (405) connects to the customizable clamping circuit portion (411) to clamp any portion of the video input signal to a second predetermined reference voltage (Vref2) of a second clamping pulse signal during a customizable clamping mode of operation. A buffer (416) connects between the customizable clamping circuit portion and the output node of the clamping circuit.

Abstract: A dc level control method for holding a dc level of a clamp portion in an electric signal to be a prescribed value is disclosed, wherein the method comprises the steps of: comparing a dc level of a sampling interval in said electric signal with a predetermined reference value to obtain a difference between said dc level and said reference value using an A/D converting section for dc level comparison which has a lower bit resolution than an A/D converting section for digital signal processing of said electric signal; and feeding back a clamp signal to said electric signal so that said obtained difference between said dc level and said reference value substantially becomes zero. This method is suitable for applying to a signal processing system for a solid state imaging apparatus.

Abstract: A circuit for clamping a TV signal includes an input capacitor coupled to the TV signal, an analog-to-digital converter that outputs a digital signal corresponding to TV signal, a comparator that compares the digital signal to a black level signal, and a high impedance driver that charges the input capacitor in response to an output of the comparator.

Abstract: A variable voltage range of a reference potential is changed during the same horizontal synchronizing period. It is possible to correctly discriminate data superposed on a video signal even if an analog potential of the video signal considerably varies during the same horizontal synchronizing period.

Abstract: A calibration device for a video circuit input stage comprises an analog-to-digital converter and an input capacitor constantly discharged by a power source and recharged by a charging circuit by means of a first and a second charging current. The charging circuit is controlled by a central processing unit receiving an estimate of the variation between the converter's output code and a clamp value.

Abstract: Disclosed is a period measuring device comprising a clamping circuit to which a synchronizing signal in an input image signal is inputted, a comparator for removing noise in the synchronizing signal outputted from the clamping circuit, period measuring circuit for measuring the period of the synchronizing signal on the basis of the synchronizing signal obtained by the comparator, judging circuit for judging whether or not the period of the synchronizing signal which has been measured by the period measuring circuit is stable, and a control circuit for controlling, when the judging circuit judges that the period of the synchronizing signal is not stable, a threshold voltage of the comparator such that the period of the synchronizing signal is stabilized.

Abstract: A low pass filter smooths a voltage corresponding to a least significant bit of a digital image signal outputted from an A/D convertor, and outputs the smoothed voltage to a sample-and-hold circuit. In the sample-and-hold circuit, a sample-hold-pulse is added during an optical black period, so that a voltage of the least significant bit of only a black level is extracted and outputted to a clamp level adjusting circuit. In the clamp level adjusting circuit, when the voltage inputted from the sample-and-hold circuit is higher 0 volts, a voltage, corresponding to a standard voltage from which the inputted voltage is subtracted by a differential amplifier, is outputted to a clamp circuit, and when the inputted voltage is 0 volts, the clamp voltage is pulled up by a pull-up resistance.

Abstract: An apparatus and method for adaptively varying a black stretch control range and a gain according to a mean level of a video signal to control black stretch of the video signal. According to the apparatus and method, the slope and range of black stretch are varied depending on the mean of the input video signal, so black stretch compensation can be adaptively performed depending on the brightness of a screen. Particularly, black stretch compensation can be effectively performed on a dark screen.

Abstract: A method for estimating a level of a predetermined portion of a video signal comprising the steps of determining a location of the predetermined portion of the video signal, sampling the video signal during the predetermined portion and estimating the level as an average of the samples of the video signal during the predetermined portion.

Abstract: A method and/or apparatus is capable of performing high accuracy digital level restoration with a high degree of noise immunity provided by a passive clamping stage.

Abstract: An object of the present invention is to provide a signal processor which improves the offset accuracy of a video signal without increasing the number of bits of a circuit.

Abstract: In order to reduce a circuit scale such as a brightness adjustment circuit or the number of pins in an IC chip, in the brightness adjustment circuit, a brightness adjusted video signal (internal video signal) output from an analog signal synthesis circuit or a D/A converter is input to one input terminal of a switch and a sample/hold circuit. The sample/hold circuit holds a voltage of a level in accordance with the pedestal level of the internal video signal at a timing in accordance with a sampling pulse in synchronization with the internal video signal. A clamp circuit clamps the pedestal level of an external video signal in accordance with a clamp pulse, using the voltage held by the sample/hold circuit as the reference voltage, and input it to the other input terminal. The output terminal of the switch is connected to an amplifier.

Abstract: A digitized luminance signal, representing the luminance component of a picture signal, is adjusted according to data stored in a memory. The data are output according to the value of the digitized luminance signal and multiplied by a weighting signal generated according to the amount of black area represented by the digitized luminance signal. The digitized luminance signal is then multiplied by a value obtained from the weighted product data. Use of the weighting signal enables the luminance scale to be stretched and compressed according to various different control characteristics without the need to store separate data for each characteristic in the memory.

Abstract: A programmable gain amplifier having three separately programmable amplifiers. A programmable transconductance amplifier is followed by a programmable transimpedance amplifier, then a programmable switched capacitor amplifier. In one embodiment, this programmable gain amplifier is implemented in an analog front-end (AFE) circuit. One AFE embodiment provides a coarse pre-gain offset a black reference level sampler, and a fine post-gain offset in the programmable switched capacitor amplifier. In one embodiment, an ADC reference is sampled, and is subtracted directly from the video signal in the switched capacitor amplifier so that the zero level of the video signal is made to correspond to the zero level of the ADC.

Abstract: A method and device are provided for correcting an amplitude of a synchronizing signal. A pedestal voltage, Vped, (i.e., a reference level) may be detected which repetitively occurs at the same period as a synchronizing signal of an input composite video signal. A reference voltage, Vsync, may be generated corresponding to an amplitude of the synchronizing signal which meets a standard for the input composite video signal. A DC voltage, Vh, may be generated having a voltage level corresponding to a tip or peak level of the synchronizing signal which meets the standard for the input composite video signal based on the pedestal voltage, Vped, and the reference voltage, Vsync. The DC voltage Vh and the composite video signal may be switchably output in synchronism with the synchronizing signal extracted from the composite video signal.

Abstract: An AKB interface apparatus in a display system (10), includes a video signal processing IC (12) having outputs coupled via respective kinescope driver ICs (18,20,22) to respective kinescope cathodes (K1,K2,K3) for display of a color image, the signal processing IC having an input 27 for receiving an AKB input signal, the driver ICs having respective outputs (28,30,32) providing respective cathode current indicating signals (RP,GP,BP) An interface circuit (100) couples the cathode current indicating signals to the AKB input of the signal processing IC. The interface circuit comprises a load circuit (110) for generating a load voltage (Vo) in response to at least one of the cathode current indicating signals. A leakage correction circuit (130), responsive to said load voltage (Vo), feeds back a leakage correction current (Io) to the load circuit.

Abstract: A clamping circuit with a low-pass filter inserted in a feedback loop from an output terminal of a comparator to variable current sources for obtaining a feedback signal having only a DC component or having only a substantial portion of a DC component obtained by removing an AC component due to a burst signal from the output signal of the comparator.

Abstract: The present invention provides a clamp circuit for clamping a video signal which includes a sync tip clamp circuit, a pedestal clamp circuit, and a direct current electrical potential correcting circuit. The sync tip clamp circuit clamps a sync tip of the horizontal synchronization signal of the composite video signal at a first reference electrical potential when a clamp pulse is not received in a pulse input terminal, and outputs the composite video signal to an output terminal. The pedestal clamp circuit clamps the pedestal DC electrical potential of the composite video signal received to the video signal input terminal to the second reference electric potential when the clamp pulse is received at the pulse input terminal, and outputs the composite video signal to the output terminal.

Abstract: A kinescope video driver includes a series connection of a main cascode transistor coupled to a cathode of a cathode ray tube and a video signal amplifying transistor. A second cascode transistor is coupled between the main cascode transistor and the video signal amplifying transistor. The second transistor is coupled to the video signal amplifying transistor through a short wire conductor and to the main cascode transistor through a long wire conductor.

Abstract: A clamp and gamma correction circuit which processes an image signal through a clamp circuit and then a gamma correction circuit in that order to perform a proper gamma correction with a clamp voltage adjusted to its appropriate value. An image signal varying between a black level and a white level is applied to the clamp circuit. The clamp circuit outputs an image signal, the black level of which is clamped to the clamp voltage, while the amplitude between the black level and the white level is maintained at constant level. The gamma correction circuit amplifies the image signal output by the clamp circuit at different amplification factors based on a reference voltage. A voltage setting circuit varies the clamp voltage and the reference voltage but with the voltage difference therebetween kept constant, and applies the clamp voltage and the reference voltage to the clamp circuit and the gamma correction circuit, respectively.

Abstract: A video signal clamping circuit for maintaining a constant clamping output level is disclosed including a clamper for generating a clamping output level in response to a reference voltage by use of an external condenser receiving a video signal and a plurality of transistors, a level variation detector for sensing a variation the clamping output level of the clamper and generating a level variation signal corresponding to the variation in the clamping output level, and a reference voltage compensator connected to the level variation detector, for receiving the level variation signal and compensating for the reference voltage of the clamper.

Abstract: A clamp pulse generating circuit comprising a synchronizing decision circuit for deciding whether an external synchronizing pulse is being input or not; an exclusive-OR circuit, a change-over switch and a pulse width detecting circuit for deciding whether a video signal containing a synchronizing pulse is being input or not; and a pulse generating circuit for generating a clamp pulse at the front or rear edge of the external synchronizing pulse output from a synchronizing separator circuit, and outputting the clamp pulse at the front edge selected by a selection switch when the external synchronizing pulse is being input and forcing to select and output the clamp pulse at the rear edge of the synchronizing pulse irrespective of the presence of the external synchronizing pulse when the video signal containing the synchronizing pulse is being input.

Abstract: An analog circuit controller having fewer signal paths and elements is disclosed herein. A microcomputer has a first D/A converter for generating control voltages variable into a plurality of levels in a time-divided manner and a second D/A converter for generating switching signals of various levels each indicative of the type of a control voltage. The analog circuit controller receives the outputs of the first and second D/A converters and responds to the output of the second D/A converter to select the necessary circuit to be controlled to which the control voltage is to be applied. As a result, a plurality of circuits to be controlled can be controlled through only two signal lines.

Abstract: A circuit and method for optimizing the display of a video signal on a display. Control of the display's brightness and contrast is based on aspects of a video signal, such as the average amplitude of the signal and the standard deviation. These aspects of the video signal are determined and the video signal manipulated based on the determined characteristics such that the resultant video signal is optimized to the dynamic range of the display.

Abstract: A video signal clamping circuit for adapting the DC level of a composite video signal to the processing range of a digital video signal processing device, includes an isolating capacitor in the analog video signal path and a controlled current source which is connected to a floating isolating-capacitor terminal and charges or discharges the isolating capacitor solely by means of a positive or negative clamping current, with the value and sign of the clamping pulses being digitally controlled by a comparator circuit which compares predetermined reference values of the composite video signal with mode-dependent comparison values.

Abstract: A signal voltage level dual clamping circuit is disclosed for use in a receiving circuit for extraction of timing information from a signal. A first, start-up voltage level clamp is provided, the operation of which is independent of the signal timing information. A second, gated voltage level clamp is provided, the operation of which is dependent on the signal timing information. A switching circuit operates to switch the first clamp out of operation and switch the second clamp into operation once sufficient timing information has been extracted from the signal to permit operation of the second clamp.

Abstract: The direct current voltage level and amplification of a multiple channel output imaging element are adjusted by comparing the output values of each channel. A calculating device, such as, for example, a CPU uses the data of one channel (i.e., a standard channel), which was sampled by a sampling circuit, as a standard, and then takes the difference between this data and the data of the other channels to calculate the offset and amplification differences. The results are sent to a D/A unit, which sends regulating voltages to offset regulating circuits and to amplifying circuits. In this manner, the offsets and amplifications of each channel are adjusted so as to become equal.

Abstract: This invention relates to a device for correcting DC of a HDTV, which can correct DC(Direct Current) that is liable to cause in mixers, base band amplifiers and ADC(Analog/Digital Converter) for a HDTV receiver. The device includes a non-interference DC detector for detecting DC from digital signals of an I channel and a Q channel applied under non-interference conditions in which an IF signal input has been cut off. An interference DC detector for detecting DC from the digital signals of an I channel and a Q channel applied at every field according to data field synchronization signal applied from outside. A selection part for selecting either one of the DC values received from the non-interference DC detector and the interference DC dectector. And, a D/A conversion part for D/A conversion of the DC value received from the selection part. Whereby, the DC value varying with time can be corrected by using field synchronization data and without turning the switch of IF terminal off.

Abstract: A video processor, having an input and an output, for compensating for accumulated phase and amplitude errors encountered during transmission of a video signal over a communications channel. The video processor includes a high-pass filter and amplifier, coupled to the input; a post-correction-phase-and-gain restorer; a wide-band-video-delay line coupled to the input; a pre-correction-comb-equalizer restorer; and a combining network, coupled to the output. The high-pass filter has a bandwidth characteristic which is approximately inverse to a low-pass characteristic encountered by the video signal during its transmission over the communications channel. The high-pass filter takes the video signal and outputs a filtered-video signal. The amplifier associated with the high-pass filter inverts the filtered-video signal. The post-correction-phase-and-gain restorer adjusts the inverted-filtered-video signal to generate a restored-video signal.

Abstract: A television (TV) signal alignment method and device are disclosed which provide a clear TV picture. The alignment method provides reduced noise. Despite transmission noise, the alignment method reduces noise at frequencies lower than 15 kHz which is generated by the alignment device, to below the visual perception threshold. This improves signal-to-noise ratio. The alignment method and device reduce this noise while rejecting 50 Hz and 25 Hz frequencies of greater than 30 dB. At each line of an image, the alignment method and device use a feedback loop to successively align a plateau at a first start of the current line of a television signal, which has transmission noise superimposed thereon, on the plateau of the preceding line. This is performed to restore the DC component of the television signal.

Abstract: A display unit in which a black level is set to a predetermined level in a first display screen having a first aspect ratio and a black level is set to a predetermined level in a second display screen having a second aspect ratio is provided. A darkest signal of a video signal is detected from an image area corresponding to the second display screen. The darkest signal is lowered to a predetermined level in an image area corresponding to the first display screen. In accordance with the principles of the present invention, the situation where a video signal of the second display screen that is to be lowered will not be lowered can be prevented.

Abstract: The present invention is directed to a system and method for compensating for offset and gain drift in a fast scan direction during an image forming process. To achieve compensation, the present invention samples a plurality of permanently darkened pixels upon powering up image sensors and circuitry therefor and during a sub-scanning process of an image and feeds this information into an offset value generating circuit. The offset generating circuit continually adjusts a pixel offset voltage according to a difference between sequential samples of the permanently darkened pixel, thereby compensating for fast scan offset drift. The present invention also samples a plurality of active pixels during a scanning of a calibration strip. From this scan, a gain corrective value is calculated. The present invention then samples active pixels during a scanning of a platen background.

Abstract: Compensation for offset errors caused by data truncation is accomplished by adding a compensation value to processed data in systems where the truncation stages are arranged in determinable configurations. More than one compensation value may be selected and applied. The selection of the appropriate value is determined by the number and type of truncation stages used in a given system configuration. The compensation value may be predetermined or measured.

Abstract: An adaptive clamping circuit for a video signal processing device includes a control signal generator for generating a control signal capable of controlling a speed of clamping operation in an input signal provided to the video signal processing device, a variable response signal generator for generating a variable response gain signal which enables the input signal to be adaptively clamped by selecting a time constant which is derived from a most significant bit (MSB) and which is adaptively changed in response to the control signal from the control signal generator, and a clamping circuit producing a direct current signal from output of the variable response signal generator and for applying the direct current signal to the input signal.

Abstract: An automatic dark level zeroing circuit removes a dark level DC bias from an analog video signal generated by a charge-coupled device (CCD) camera, The automatic dark level zeroing circuit is DC-coupled to the CCD camera such that there is no loss of low frequency information in the analog video signal, The automatic dark level zeroing circuit forms an adaptive feedback loop that removes the dark level DC bias from the analog video signal by using a sampled value of the analog video signal that represents an internally masked pixel to produce a zero correction signal that is then combined with the analog video signal to remove the dark level DC bias without removing any useful video information or otherwise altering the information content of the analog video signal,

Abstract: An image signal processing apparatus wherein image signals of plural kinds transmitted in different TV systems can selectively be reproduced, to provide an image signal processing apparatus wherein image signals of plural kinds transmitted in different systems can selectively be reproduced with simple construction, high cost-effectiveness, and high practicability. The apparatus has a sync signal generating unit for performing arithmetic operation processing for extracting a sync signal component from an input image signal, by changing a processing program in accordance with a transmission system of the input image signal, and a decoding unit for decoding the input image signal on the basis of a sync signal generated by the sync signal generating unit.

Abstract: A driver for a cathode ray tube includes a black level compensation circuit which generates an offset voltage which tracks the current flowing to the output of the driver and therefore the average picture level (APL). The offset voltage is added as a component of the output voltage so as to increasingly shift the output voltage toward black as the APL increases. This compensates for CRT gamma non-linearities and for light scattering effects which might otherwise cause the loss of perceived detail and sharpness in dark areas of a high APL image. In the disclosed embodiment, the driver comprises a cascode amplifier and the offset voltage generating element includes a capacitively bypassed resistor connected in a reference voltage network connected to the emitter circuit of the lower (common emitter configured) transistor of the cascode amplilfier.

Abstract: A clamping circuit clamps an input signal applied at an input pin of an integrated circuit package by charging and discharging a series capacitor into the input pin with first and second controlled current sources. The voltage developed at the input pin is compared against a reference signal in either the analog or digital domain to generate control signals to control the first and second current sources. The controlled current sources maintain the proper voltage across the series capacitor to clamp the voltage at the input pin. In the digital embodiment, an analog-to-digital converter and digital filter provide a filtered digital signal to compare against a digital reference to generate the control signals.

Abstract: A circuit arrangement for processing an input video signal (V) is described, which video signal has a fixed black level (SP), a given white peak value (WW) as well as a black peak value (SW) dependent on the picture contents (during tb), in which a correct display of the blackest and brightest parts of the picture contents of the video signal (V) is rendered possible without many components and without interference.

Abstract: A video signal AGC circuit including an analog gain control amplifier for adjusting the level of an input analog video signal; an A-D converter for converting the output of the analog gain control amplifier to a digital video signal; a sync level detector for detecting the sync level of the digital video signal outputted from the A-D converter; a digital gain control amplifier for adjusting the level of the digital video signal outputted from the A-D converter; a first control signal generator for generating a first control signal to adjust the gain of the analog gain control amplifier on the basis of the output of the sync level detector; and a second control signal generator for generating a second control signal to adjust the gain of the digital gain control amplifier on the basis of the output of the sync level detector.

Abstract: An automatic knee control circuit including a knee circuit for setting a knee point and a knee slope, a detecting circuit for detecting an output signal of the knee circuit and a comparing circuit for comparing an output of the detecting circuit with a reference voltage, wherein the knee circuit is controlled on the basis of an output of the comparing circuit. This automatic knee control circuit is characterized by a distributing circuit for distributing the output of the comparing circuit by an arbitrary distributing ratio, wherein the setting of the knee point is controlled by a first distributed output and the setting of the knee slope is controlled by a second distributed output, thereby making it possible to set a wide variety of signal processing states with ease. Therefore, pictures corresponding to cameraman's intention can be produced.

Abstract: A video signal clamping circuit capable of maintaining a DC level of a digital video signal at a fixed level, in which a pedestal level in a vertical blanking period of the digital video signal after an A/D conversion is sampled, and an average value of a plurality of sampling data in a plurality of fields is calculated by an average value calculator. The average value is compared with a predetermined clamp level reference value by a comparison output circuit, and depending on the comparison result, a signal either added or subtracted by a certain width to or from an output signal of a predetermined period before is output for automatically controlling a clamp voltage.

Abstract: In a computer system having a frame buffer, apparatus for providing an overlay for the frame buffer, and a digital-to-analog converter for furnishing analog signals from the frame buffer to a pedestal setup display monitor, the digital-to-analog converter including apparatus for furnishing a blank level substantially below the lowest level of the analog signal desired to be visible on the monitor during retrace periods when used with a pedestal setup display monitor, the improvement including apparatus for allowing the system to utilize zero setup display monitors including apparatus for disabling the apparatus for furnishing a blank level when the computer system is used with a zero setup display monitor, and apparatus for causing the apparatus for providing an overlay for the frame buffer to furnish signals indicating a black level during retrace periods when the computer system is used with a zero setup display monitor.