Having Tunnel Junction Effect Patents (Class 360/324.2)
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Patent number: 10720569Abstract: A magnetic tunnel junction comprises a conductive first magnetic electrode comprising magnetic recording material, a conductive second magnetic electrode spaced from the first electrode and comprising magnetic reference material, and a non-magnetic tunnel insulator material between the first and second electrodes. The magnetic reference material of the second electrode comprises a synthetic antiferromagnetic construction comprising two spaced magnetic regions one of which is closer to the tunnel insulator material than is the other. The one magnetic region comprises a polarizer region comprising CoxFeyBz where “x” is from 0 to 90, “y” is from 10 to 90, and “z” is from 10 to 50. The CoxFeyBz is directly against the tunnel insulator. A non-magnetic region comprising an Os-containing material is between the two spaced magnetic regions. The other magnetic region comprises a magnetic Co-containing material. Other embodiments are disclosed.Type: GrantFiled: June 7, 2019Date of Patent: July 21, 2020Assignee: Micron Technology, Inc.Inventors: Wei Chen, Witold Kula, Manzar Siddik, Suresh Ramarajan, Johnathan D. Harms
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Patent number: 10714125Abstract: A magnetic recording head having air bearing surface (ABS) includes a main pole, a side shield laterally spaced from the main pole by a first side gap and a second side gap, an electrically conductive non-magnetic gap material layer disposed between the main pole and the side shield in the first side gap, and a dielectric non-magnetic gap material matrix and a conformal dielectric spacer layer disposed between the main pole and the side shield in the second side gap.Type: GrantFiled: May 14, 2018Date of Patent: July 14, 2020Assignee: SANDISK TECHNOLOGIES LLCInventors: Jinqiu Zhang, Ming Sun, Feng Liu, Xiaojun Zhang
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Patent number: 10714681Abstract: Embodiments of the invention are directed to a method of forming a memory element pillar. The method includes forming memory element stack layers, forming a conductive cap layer over the memory element stack layers, forming a conductive seal layer over the cap layer, and forming a conductive etch stop layer over the conductive seal layer, wherein the conductive etch stop layer comprises a substantially planar surface. A hardmask is formed over the substantially planar surface of the conductive etch stop layer, wherein the hardmask defines dimensions of the memory element pillar.Type: GrantFiled: October 19, 2018Date of Patent: July 14, 2020Assignee: International Business Machines CorporationInventors: Michael Rizzolo, Theodorus E. Standaert, Cornelius Brown Peethala
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Patent number: 10714126Abstract: A magnetic recording head includes a slider having an air bearing surface, a main magnetic pole including a fore-end portion that extends towards the air bearing surface and configured to generate recording magnetic fields in a first direction, a write shield magnetic pole located across from the fore-end portion to form a write gap that extends therebetween in a second direction and forming a magnetic core in conjunction with the main magnetic pole, a coil configured to excite a magnetic flux in the magnetic core, first and second spin-torque oscillators in the write gap and arranged along a third direction with a spacing therebetween, and a current circuit connected to the first and second spin-torque oscillators via the main magnetic pole and the write shield magnetic pole and configured to supply current to oscillate the first or second spin-torque oscillators.Type: GrantFiled: February 25, 2019Date of Patent: July 14, 2020Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventor: Takuya Matsumoto
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Patent number: 10706996Abstract: A magnetic material includes a structure in which a first magnetic layer 1 and a second magnetic layer 2 are stacked such that each layer is formed at least partially in a stacking direction by substantially one atomic layer. The first magnetic layer contains Co as a principal component. The second magnetic layer includes at least Ni. The magnetic material has magnetic anisotropy in the stacking direction. Preferably, an atomic arrangement within a film surface of the first magnetic layer and the second magnetic layer has six-fold symmetry.Type: GrantFiled: November 11, 2013Date of Patent: July 7, 2020Assignee: TOHOKU UNIVERSITYInventors: Shunsuke Fukami, Hideo Sato, Michihiko Yamanouchi, Shoji Ikeda, Hideo Ohno
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Patent number: 10707268Abstract: A magnetoresistive element according to an embodiment includes: a first layer; a first magnetic layer; a second magnetic layer disposed between the first layer and the first magnetic layer; a nonmagnetic layer disposed between the first magnetic layer and the second magnetic layer; and an insulating layer disposed at least on side surfaces of the nonmagnetic layer, the first layer including: at least one element selected from a first group consisting of Hf, Zr, Al, Cr, and Mg; and at least one element selected from a second group consisting of Ta, W, Mo, Nb, Si, Ge, Be, Li, Sn, Sb, and P, and the insulating layer including at least one element selected from the first group.Type: GrantFiled: August 14, 2018Date of Patent: July 7, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Masaki Endo, Tadaomi Daibou, Shumpei Omine, Akiyuki Murayama, Junichi Ito
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Patent number: 10700267Abstract: A magnetoresistive element has a magnetization free layer whose magnetization direction changes in an external magnetic field; a magnetization pinned layer whose magnetization direction is pinned in the external magnetic field; and a barrier layer that is positioned between the magnetization free layer and the magnetization pinned layer and that exhibits a magnetoresistive effect. The barrier layer is an oxide of an alloy that includes Mg and Al, and the barrier layer includes a crystalline region and a non-crystalline region.Type: GrantFiled: October 18, 2018Date of Patent: June 30, 2020Assignee: TDK CorporationInventors: Kohei Honma, Satoshi Miura
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Patent number: 10700264Abstract: A method includes forming in sequence a bottom magnetic layer, a tunnel barrier layer, a top magnetic layer, and a top electrode layer over a bottom electrode layer; performing a first etching process to recess the top electrode layer, in which the first etching process stops before the top magnetic layer is etched; performing a second etching process to pattern the top electrode layer as a top electrode and the top magnetic layer as a patterned top magnetic layer, in which the second etching process stops before the bottom magnetic layer is etched; forming a first spacer around the top electrode and the patterned top magnetic layer; and after forming the first spacer, performing a third etching process to pattern the tunnel barrier layer as a patterned tunnel barrier layer and the bottom magnetic layer as a patterned bottom magnetic layer.Type: GrantFiled: July 15, 2019Date of Patent: June 30, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wei-Hao Liao, Chih-Wei Lu, Hsi-Wen Tien, Pin-Ren Dai, Chung-Ju Lee
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Patent number: 10665778Abstract: Methods and apparatuses for producing magneto resistive apparatuses are provided. Here, structures are formed for defining regions of the same magnetization, magnets are magnetized, and structures are formed within the magnets of the regions, for example, in order to define magneto resistive elements.Type: GrantFiled: May 12, 2017Date of Patent: May 26, 2020Assignee: Infineon Technologies AGInventor: Wolfgang Raberg
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Patent number: 10644226Abstract: A magnetic junction, a memory using the magnetic junction and method for providing the magnetic junction are described. The magnetic junction includes first and second reference layers, a main barrier layer, a free layer, an engineered secondary barrier layer and a second reference layer. The free layer is switchable between stable magnetic states when a write current is passed through the magnetic junction. The main barrier layer is between the first reference layer and the free layer. The secondary barrier layer is between the free layer and the second reference layer. The engineered secondary barrier layer has a resistance and a plurality of regions having a reduced resistance less than the resistance. The free and reference layers each has a perpendicular magnetic anisotropy energy and an out-of-plane demagnetization energy less than the perpendicular magnetic anisotropy energy.Type: GrantFiled: June 26, 2019Date of Patent: May 5, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Zheng Duan, Dmytro Apalkov, Vladimir Nikitin
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Patent number: 10622550Abstract: A magnetoresistance effect element includes a bias layer comprised of an antiferromagnetic material and having a shape in which a first length in a first direction greater than a second length in a second direction perpendicular to the first direction, a recording layer comprised of a ferromagnetic material and being disposed on the bias layer, a direction of magnetization of the recording layer being reversible, a barrier layer comprised of an insulation material and being disposed on the recording layer, and a reference layer comprised of a ferromagnetic material and being disposed on the barrier layer, a direction of magnetization of the reference layer being substantially fixed.Type: GrantFiled: September 28, 2017Date of Patent: April 14, 2020Assignee: TOHOKU UNIVERSITYInventors: Shunsuke Fukami, Hideo Ohno, Tetsuo Endoh
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Patent number: 10586561Abstract: An apparatus according to one embodiment includes a sensor having an active region, a magnetic shield adjacent the active region, a spacer between the active region and the magnetic shield, a second magnetic shield on an opposite side of the active region as the magnetic shield, and a second spacer between the active region and the second magnetic shield. Both spacers include an electrically conductive ceramic layer. The electrically conductive ceramic layer of the spacer has a different composition than the electrically conductive ceramic layer of the second spacer.Type: GrantFiled: April 26, 2018Date of Patent: March 10, 2020Assignee: International Business Machines CorporationInventors: Robert G. Biskeborn, Calvin S. Lo, Philip M. Rice, Teya Topuria
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Patent number: 10586562Abstract: A hybrid dual reader. The hybrid dual reader includes first and second read sensors with conflicting design characteristics. The first read sensor includes at least one signal-to-noise ratio favoring design characteristic. The second read sensor includes at least one pulse width favoring design characteristic. The at least one signal-to-noise ratio favoring design characteristic is in conflict with the at least one pulse width favoring design characteristic.Type: GrantFiled: November 1, 2017Date of Patent: March 10, 2020Assignee: SEAGATE TECHNOLOGY LLCInventors: Victor Sapozhnikov, Pavol Krivosik, Mohammed Shariat Ullah Patwari, Scott Wilson Stokes
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Patent number: 10534047Abstract: Tunnel magneto-resistive (TMR) sensors employing TMR devices with different magnetic field sensitivities for increased detection sensitivity are disclosed. For example, a TMR sensor may be used as a biosensor to detect the presence of biological materials. In aspects disclosed herein, free layers of at least two TMR devices in a TMR sensor are fabricated to exhibit different magnetic properties from each other (e.g., MR ratio, magnetic anisotropy, coercivity) so that each TMR device will exhibit a different change in resistance to a given magnetic stray field for increased magnetic field detection sensitivity. For example, the TMR devices may be fabricated to exhibit different magnetic properties such that one TMR device exhibits a greater change in resistance in the presence of a smaller magnetic stray field, and another TMR device exhibits a greater change in resistance in the presence of a larger magnetic stray field.Type: GrantFiled: March 30, 2017Date of Patent: January 14, 2020Assignee: QUALCOMM IncorporatedInventors: Wei-Chuan Chen, Wah Nam Hsu, Xia Li, Seung Hyuk Kang, Nicholas Ka Ming Stevens-Yu
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Patent number: 10497860Abstract: Some embodiments of the present disclosure relate to a method that achieves a substantially uniform pattern of magnetic random access memory (MRAM) cells with a minimum dimension below the lower resolution limit of some optical lithography techniques. A copolymer solution comprising first and second polymer species is spin-coated over a heterostructure which resides over a surface of a substrate. The heterostructure comprises first and second ferromagnetic layers which are separated by an insulating layer. The copolymer solution is subjected to self-assembly into a phase-separated material comprising a pattern of micro-domains of the second polymer species within a polymer matrix comprising the first polymer species. The first polymer species is then removed, leaving a pattern of micro-domains of the second polymer species. A pattern of magnetic memory cells within the heterostructure is formed by etching through the heterostructure while utilizing the pattern of micro-domains as a hardmask.Type: GrantFiled: January 8, 2016Date of Patent: December 3, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Ming Chen, Chern-Yow Hsu, Szu-Yu Wang, Chung-Yi Yu, Chia-Shiung Tsai, Xiaomeng Chen
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Patent number: 10490737Abstract: The present invention is directed to a magnetic memory element including a magnetic free layer structure that includes two magnetic free layers separated by a magnesium perpendicular enhancement layer; an insulating tunnel junction layer formed adjacent to the magnetic free layer structure; a first magnetic reference layer formed adjacent to the insulating tunnel junction layer; a second magnetic reference layer separated from the first magnetic reference layer by a non-magnetic perpendicular enhancement layer; an anti-ferromagnetic coupling layer formed adjacent to the second magnetic reference layer; and a magnetic fixed layer structure formed adjacent to the anti-ferromagnetic coupling layer. The two magnetic free layers have a same variable magnetization direction substantially perpendicular to layer planes thereof. The first and second magnetic reference layers have a first invariable magnetization direction substantially perpendicular to layer planes thereof.Type: GrantFiled: February 27, 2019Date of Patent: November 26, 2019Assignee: Avalanche Technology, Inc.Inventors: Zihui Wang, Yiming Huai
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Patent number: 10454021Abstract: The present disclosure provides a semiconductor structure, including an Nth metal layer, a bottom electrode over the Nth metal layer, a magnetic tunneling junction (MTJ) over the bottom electrode, a top electrode over the MTJ, and an (N+M)th metal layer over the Nth metal layer. N and M are positive integers. The (N+M)th metal layer surrounds a portion of a sidewall of the top electrode. A manufacturing method of forming the semiconductor structure is also provided.Type: GrantFiled: May 10, 2016Date of Patent: October 22, 2019Assignee: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: Fu-Ting Sung, Chung-Chiang Min, Yuan-Tai Tseng, Chern-Yow Hsu, Shih-Chang Liu
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Patent number: 10347823Abstract: A magnetoresistive element includes a channel layer, a first ferromagnetic layer, a second ferromagnetic layer, and a reference electrode. The first ferromagnetic layer, the second ferromagnetic layer, and the reference electrode are apart from each other and are electrically connected to each other through the channel layer. The average resistivity of a sixth region composed of a first region, a second region, and a fourth region is higher than the average resistivity of a seventh region composed of the second region, a third region, and a fifth region.Type: GrantFiled: March 16, 2017Date of Patent: July 9, 2019Assignee: TDK CORPORATIONInventor: Hayato Koike
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Patent number: 10326074Abstract: Embodiments are directed to STT MRAM devices. One embodiment of an STT MRAM device includes a reference layer, a tunnel barrier layer, a free layer and one or more conductive vias. The reference layer is configured to have a fixed magnetic moment. In addition, the tunnel barrier layer is configured to enable electrons to tunnel between the reference layer and the free layer through the tunnel barrier layer. The free layer is disposed beneath the tunnel barrier layer and is configured to have an adaptable magnetic moment for the storage of data. The conductive via is disposed beneath the free layer and is connected to an electrode. Further, the conductive via has a width that is smaller than a width of the free layer such that a width of an active STT area for the storage of data in the free layer is defined by the width of the conductive via.Type: GrantFiled: August 8, 2017Date of Patent: June 18, 2019Assignee: International Business Machines CorporationInventors: Michael C. Gaidis, Janusz J. Nowak, Daniel C. Worledge
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Patent number: 10320404Abstract: Described is an oscillating apparatus which comprises: an interconnect with spin-coupling material (e.g., Spin Hall Effect (SHE) material); and a magnetic stack having two magnetic layers such that one of the magnetic layers is coupled to the interconnect, wherein each of the two magnetic layers have respective magnetization directions to cause the magnetic stack to oscillate.Type: GrantFiled: June 18, 2014Date of Patent: June 11, 2019Assignee: Intel CorporationInventors: Sasikanth Sasi Manipatruni, George I. Bourianoff, Dmitri E. Nikonov, Ian A. Young
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Patent number: 10297278Abstract: Structures and methods for fabrication servo and data heads of tape modules are provided. The servo head may have two shield layers spaced apart by a plurality of gap layers and a sensor. Similarly, the data head may have two shield layers spaced apart by a plurality of gap layers and a sensor. The distance between the shield layers of the servo head may be greater than the distance between the shield layers of the data head. The material of the gap layers may include tantalum or an alloy of nickel and chromium. The material for the gap layers permits deposition of gap layers with sufficiently small surface roughness to prevent distortion of the tape module and increase the stability of the tape module operation.Type: GrantFiled: July 31, 2014Date of Patent: May 21, 2019Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Satoru Araki, Diane L. Brown, Hiroaki Chihaya, Dustin W. Erickson, David J. Seagle
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Patent number: 10283701Abstract: A magnetic junction and method for providing the magnetic junction are described. The method includes providing a pinned layer, a nonmagnetic spacer layer and a free layer switchable between stable magnetic states. The nonmagnetic spacer layer is between the pinned and free layers. Providing the pinned layer and/or providing the free layer includes cooling a portion of the magnetic junction, depositing a wetting layer while the portion of the magnetic junction is cooled, oxidizing/nitriding the wetting layer and depositing a boron-free magnetic layer on the oxide/nitride wetting layer. The portion of the magnetic junction is cooled to within a temperature range including temperature(s) not greater than 250 K. The wetting layer has a thickness of at least 0.25 and not more than three monolayers. The wetting layer includes at least one magnetic material. The boron-free magnetic layer has a perpendicular magnetic anisotropy energy greater than an out-of-plane demagnetization energy.Type: GrantFiled: February 6, 2018Date of Patent: May 7, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Ikhtiar, Xueti Tang, Mohamad Towfik Krounbi
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Patent number: 10263182Abstract: A magnetoresistance effect element is capable of realizing a high magnetoresistance (MR) ratio. The magnetoresistance effect element includes a laminate in which: an underlayer; a first ferromagnetic metal layer; a tunnel barrier layer; and a second ferromagnetic metal layer are laminated in that order. The underlayer is made of a nitride, the tunnel barrier layer is made of any one selected from a group consisting of MgAl2O4, ZnAl2O4, MgO, and ?-Al2O3, and a degree of lattice mismatching between a lattice constant of the tunnel barrier layer and a lattice constant of a crystal structure to be taken by the underlayer is 5% or less.Type: GrantFiled: September 22, 2017Date of Patent: April 16, 2019Assignee: TDK CORPORATIONInventor: Tomoyuki Sasaki
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Patent number: 10217934Abstract: The present invention is directed to a method for manufacturing a memory cell that includes a magnetic memory element electrically connected to a two-terminal selector.Type: GrantFiled: August 24, 2018Date of Patent: February 26, 2019Assignee: Avalanche Technology, Inc.Inventors: Hongxin Yang, Dong Ha Jung, Jing Zhang, Bing K. Yen
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Patent number: 10186656Abstract: A magnetic memory according to an embodiment includes: a first magnetic layer; a second magnetic layer; a first nonmagnetic layer disposed between the first magnetic layer and the second magnetic layer; a third magnetic layer disposed between the first magnetic layer and the first nonmagnetic layer; and a first layer disposed between the first magnetic layer and the third magnetic layer, wherein the first layer contains at least one element selected from the group consisting of Co, Fe, Ni, and Mn, and at least one element selected from the group consisting of Ta, Mo, Zr, Nb, Hf, V, Ti, Sc, and La.Type: GrantFiled: September 13, 2017Date of Patent: January 22, 2019Assignee: Toshiba Memory CorporationInventors: Shumpei Omine, Takeshi Iwasaki, Masaki Endo, Akiyuki Murayama, Tadaomi Daibou, Tadashi Kai, Junichi Ito
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Patent number: 10170687Abstract: The disclosed technology relates generally to magnetic devices, and more particularly to spin torque majority gate devices such as spin torque magnetic devices (STMG), and to methods of fabricating the same. In one aspect, a majority gate device includes a plurality of input zones and an output zone. A magnetic tunneling junction (MTJ) is formed in each of the input zones and the output zone, where the MTJ includes a non-magnetic layer interposed between a free layer stack and a hard layer. The free layer stack in turn includes a bulk perpendicular magnetic anisotropy (PMA) layer on a seed layer, a magnetic layer formed on and in contact with the bulk PMA layer, and a non-magnetic layer formed on the magnetic layer. Each of the bulk PMA layer and the seed layer is configured as a common layer for each of the input zones and the output zone.Type: GrantFiled: December 21, 2016Date of Patent: January 1, 2019Assignee: IMEC vzwInventors: Johan Swerts, Mauricio Manfrini, Christoph Adelmann
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Patent number: 10164177Abstract: A magnetic junction usable in a magnetic device and a method for providing the magnetic junction are described. A first portion of a magnetoresistive stack corresponding to the magnetic junction is provided. Providing this portion of the magnetoresistive stack includes providing at least one layer for a free layer of the magnetic junction. A second portion of the magnetoresistive stack is provided after the step of providing the first portion of the magnetoresistive stack. The magnetoresistive stack is patterned to provide the magnetic junction after the step of providing the second portion of the magnetoresistive stack. An ambient temperature for the magnetoresistive stack and the magnetic junction does not exceed a crystallization temperature of the free layer after the step of providing the free layer through the step of patterning the magnetoresistive stack.Type: GrantFiled: February 28, 2017Date of Patent: December 25, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Sebastian Schafer, Dmytro Apalkov, Vladimir Nikitin, Don Koun Lee
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Patent number: 10141037Abstract: According to one embodiment, a magnetic memory device includes a conductive layer, a first magnetic layer, a second magnetic layer, a first nonmagnetic layer, and a controller. The conductive layer includes a first portion, a second portion, and a third portion. The first magnetic layer is separated from the third portion. The first nonmagnetic layer is provided between the first magnetic layer and the second magnetic layer that is electrically connected with the third portion. The first nonmagnetic layer is curved. The controller is electrically connected to the first portion and the second portion. The controller implements a first operation and a second operation. The controller in the first operation supplies a first current to the conductive layer from the first portion toward the second portion. The controller in the second operation supplies a second current to the conductive layer from the second portion toward the first portion.Type: GrantFiled: September 14, 2017Date of Patent: November 27, 2018Assignee: Kabushiki Kaisha ToshibaInventors: Yuichi Ohsawa, Hiroaki Yoda, Altansargai Buyandalai, Satoshi Shirotori, Mariko Shimizu, Hideyuki Sugiyama, Yushi Kato
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Patent number: 10119988Abstract: An MLU-based accelerometer including: at least one MLU including a tunnel barrier layer between a first magnetic layer having a fixed first magnetization direction and a second magnetic layer having a second magnetization direction that can be varied. A proof-mass includes a ferromagnetic material having a proof-mass magnetization inducing a proof-mass field, the proof-mass being elastically suspended such as to be deflected in at least one direction when subjected to an acceleration vector. The proof-mass is magnetically coupled to the MLU cell via the proof-mass field. A read module is configured for determining a magnetoresistance of each MLU cell such as to determine an acceleration vector from the deflection of the proof-mass relative to any one of the at least one MLU cell.Type: GrantFiled: June 30, 2015Date of Patent: November 6, 2018Assignee: CROCUS TECHNOLOGY SAInventor: Ali Alaoui
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Patent number: 10101414Abstract: Thin film resistive sensors typically include a number of resistive components. These components should be well matched in order for the sensor to provide accurate readings. When a sensor is incorporated within an integrated circuit, the resistive components may be formed over, or under, metallic traces that form part of other components. As a result, the thin film resistive components are subjected to different levels of stress. This disclosure provides a structure that is arranged to mitigate the effects of stress.Type: GrantFiled: January 18, 2016Date of Patent: October 16, 2018Assignee: Analog Devices GlobalInventors: Jan Kubik, Seamus P. Whiston, Padraig Michael Doran
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Patent number: 10102870Abstract: A magnetic read head including a first read element magnetically coupled to a bottom shield; a second read element magnetically coupled to a top shield; a magnetic shielding structure that magnetically shields the first read element from the second read element; and a first electrical contact electrically coupled to the bottom shield, a second electrical contact electrically coupled to the top shield and a third electrical contact electrically coupled to the magnetic shielding structure.Type: GrantFiled: December 19, 2016Date of Patent: October 16, 2018Assignee: Seagate Technology LLCInventor: Steven A. Mastain
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Patent number: 10079338Abstract: The present invention is directed to a magnetic memory element including a magnetic free layer structure having a variable magnetization direction perpendicular to a layer plane thereof; an oxide layer formed adjacent to the magnetic free layer structure; an insulating tunnel junction layer formed adjacent to the magnetic free layer structure opposite the oxide layer; a first magnetic reference layer formed adjacent to the insulating tunnel junction layer opposite the magnetic free layer structure; a second magnetic reference layer separated from the first magnetic reference layer by a perpendicular enhancement layer; an antiferromagnetic coupling layer formed adjacent to the second magnetic reference layer; and a magnetic fixed layer structure formed adjacent to the antiferromagnetic coupling layer. The first and second magnetic reference layers have a first invariable magnetization direction substantially perpendicular to layer planes thereof.Type: GrantFiled: October 26, 2017Date of Patent: September 18, 2018Assignee: Avalanche Technology, Inc.Inventors: Yiming Huai, Huadong Gan, Bing K. Yen
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Patent number: 10069062Abstract: A magnetoresistive element includes a laminated structure including a plurality of fixed layers, an intermediate layer formed of a non-magnetic material, and a recording layer, the plurality of fixed layers being laminated via a non-magnetic layer, the plurality of fixed layers having at least a first fixed layer and a second fixed layer, the following formula being satisfied: S1>S2 (wherein S1 is an area of a portion of the first fixed layer adjacent to the intermediate layer, which faces the intermediate layer, and S2 is an area of the fixed layer having the smallest area out of the fixed layers other than the first fixed layer).Type: GrantFiled: November 18, 2016Date of Patent: September 4, 2018Assignee: Sony CorporationInventors: Hiroyuki Uchida, Masanori Hosomi, Hiroyuki Ohmori, Kazuhiro Bessho, Yutaka Higo, Kazutaka Yamane
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Patent number: 10054649Abstract: A magnetic sensor assembly includes first and second shields each comprised of a magnetic material. The first and second shields define a physical shield-to-shield spacing. A sensor stack is disposed between the first and second shields and includes a seed layer adjacent the first shield, a cap layer adjacent the second shield, and a magnetic sensor between the seed layer and the cap layer. At least a portion of the seed layer and/or the cap layer comprises a magnetic material to provide an effective shield-to-shield spacing of the magnetic sensor assembly that is less than the physical shield-to-shield spacing.Type: GrantFiled: August 16, 2016Date of Patent: August 21, 2018Assignee: Seagate Technology LLCInventors: Eric W. Singleton, Qing He, Jae-Young Yi, Matt Johnson, Zheng Gao, Dimitar V. Dimitrov, Song S. Xue
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Patent number: 10038137Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a magnetoresistive random access memory (MRAM) device in an insulating layer. The MRAM device includes a first electrode, a magnetic tunnel junction (MTJ) over the first electrode, a second electrode over the MTJ, and an insulating spacer surrounding sidewalls of the first electrode, the MTJ, and the second electrode. Top surfaces of the insulating spacer and the second electrode are exposed from the insulating layer. The semiconductor device structure also includes a conductive pad over the insulating layer and electrically connected to the second electrode. The MTJ is entirely covered by the conductive pad.Type: GrantFiled: September 30, 2016Date of Patent: July 31, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Harry-Hak-Lay Chuang, Sheng-Haung Huang, Hung-Cho Wang, Kuei-Hung Shen, Shy-Jay Lin
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Patent number: 10002973Abstract: The present disclosure concerns a method of fabricating a magnetic tunnel junction suitable for a magnetic random access memory (MRAM) cell and comprising a first ferromagnetic layer, a tunnel barrier layer, and a second ferromagnetic layer, comprising: forming the first ferromagnetic layer; forming the tunnel barrier layer; and forming the second ferromagnetic layer; wherein said forming the tunnel barrier layer comprises depositing a layer of metallic Mg; and oxidizing the deposited layer of metallic Mg such as to transform the metallic Mg into MgO; the step of forming the tunnel barrier layer being performed at least twice such that the tunnel barrier layer comprises at least two layers of MgO.Type: GrantFiled: September 5, 2012Date of Patent: June 19, 2018Assignee: CROCUS TECHNOLOGY SAInventors: Ioan Lucian Prejbeanu, Celine Portemont, Clarisse Ducruet
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Patent number: 9997563Abstract: An embodiment integrates memory, such as spin-torque transfer magnetoresistive random access memory (STT-MRAM) within a logic chip. The STT-MRAM includes a magnetic tunnel junction (MTJ) that has an upper MTJ layer, a lower MTJ layer, and a tunnel barrier directly contacting the upper MTJ layer and the lower MTJ layer; wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer. Another embodiment includes a memory area, comprising a MTJ, and a logic area located on a substrate; wherein a horizontal plane intersects the MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the MTJ, and a second ILD material included in the logic area, the first and second ILD materials being unequal to one another. Other embodiments are described herein.Type: GrantFiled: May 16, 2017Date of Patent: June 12, 2018Assignee: Intel CorporationInventors: Kevin J. Lee, Tahir Ghani, Joseph M. Steigerwald, John H. Epple, Yih Wang
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Patent number: 9990944Abstract: An apparatus, according to one embodiment, includes: a tape head having: a write module, a read module, and a plurality of tunnel valve read transducers arranged in an array extending along the read module. Each of the tunnel valve read transducers includes: a sensor structure, an upper and lower magnetic shield, an upper conducting spacer layer between the sensor structure and the upper magnetic shield, a lower conducting spacer layer between the sensor structure and the lower magnetic shield, and electrically insulating layers opposite the sensor structure. The sensor structure includes a cap layer, a free layer, a tunnel barrier layer, a reference layer and antiferromagnetic layer. A height of the free layer measured in a direction perpendicular to a media bearing surface of the read module is less than a width of the free layer measured in a cross-track direction perpendicular to an intended direction of media travel.Type: GrantFiled: February 28, 2017Date of Patent: June 5, 2018Assignee: International Business Machines CorporationInventors: Robert G. Biskeborn, Robert E. Fontana, Jr., Calvin S. Lo
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Patent number: 9963780Abstract: A method for forming metal on a dielectric includes forming a seed layer on a surface including a reactant element. A first metal layer is formed on the seed layer wherein the first metal layer wets the seed layer. A second metal layer is formed on the first metal layer wherein the second metal layer wets the first metal layer. Diffuse the reactant element of the seed layer into the first metal layer by annealing to convert the first metal layer to a dielectric layer.Type: GrantFiled: December 3, 2015Date of Patent: May 8, 2018Assignee: International Business Machines CorporationInventors: Guohan Hu, Daniel C. Worledge
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Patent number: 9947866Abstract: A method of manufacturing a nonvolatile memory device includes sequentially forming, on a first wiring layer extending in a first direction, a first layer containing a first metal and a second layer containing a second metal into which the first metal can diffuse. The method further includes oxidizing the first layer and the second layer, removing oxygen from the oxidized first layer by annealing, forming a conductive third layer on the oxidized second layer after removing oxygen from the oxidized first layer, and forming a second wiring layer on the third layer. The second wiring layer extends in a second direction crossing the first wiring layer.Type: GrantFiled: August 31, 2016Date of Patent: April 17, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventor: Kensuke Takahashi
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Patent number: 9940955Abstract: A read head is provided with a scissors sensor. The read head may include a bottom magnetic shield, and a first non-magnetic seed layer, a magnetic seed layer, a second non-magnetic seed layer, an antiferromagnetic layer, a coupling layer, a first free magnetic layer, a spacer layer, and a second free magnetic layer positioned above the bottom magnetic shield, in this order. A pair of magnetic side shield layers may be positioned on respective sides of the second free magnetic layer.Type: GrantFiled: December 1, 2015Date of Patent: April 10, 2018Assignee: Western Digital Technologies, Inc.Inventors: Kouichi Nishioka, Zheng Gao, Ching Tsang, Quang Le, Sangmun Oh
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Patent number: 9923138Abstract: A memory device includes a magnetic tunnel junction comprising a first free layer, a pinned layer, and a tunnel barrier layer disposed between the first free layer and the pinned layer, wherein the first free layer comprises a first free magnetic pattern adjacent to the tunnel barrier layer, and a second free magnetic pattern spaced apart from the tunnel barrier layer with the first free magnetic pattern interposed therebetween, wherein the second free magnetic pattern contacts the first free magnetic pattern, wherein the first and second free magnetic patterns include boron (B), wherein a boron content of the first free magnetic pattern is higher than a boron content of the second free magnetic pattern, and wherein the boron content of the first free magnetic pattern is in a range of about 25 at % to about 50 at %.Type: GrantFiled: December 12, 2016Date of Patent: March 20, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Sang Hwan Park, Kwangseok Kim, Keewon Kim, Jae Hoon Kim, Joonmyoung Lee
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Patent number: 9915707Abstract: Embodiments relate to xMR sensors having very high shape anisotropy. Embodiments also relate to novel structuring processes of xMR stacks to achieve very high shape anisotropies without chemically affecting the performance relevant magnetic field sensitive layer system while also providing comparatively uniform structure widths over a wafer, down to about 100 nm in embodiments. Embodiments can also provide xMR stacks having side walls of the performance relevant free layer system that are smooth and/or of a defined lateral geometry which is important for achieving a homogeneous magnetic behavior over the wafer.Type: GrantFiled: February 15, 2017Date of Patent: March 13, 2018Assignee: Infineon Technologies AGInventors: Juergen Zimmer, Klemens Pruegl, Olaf Kuehn, Andreas Strasser, Ralf-Rainer Schledz, Norbert Thyssen
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Patent number: 9880232Abstract: A magnetic sensor comprising a first shield and a second shield and a sensor stack between the first and the second shield, the sensor stack having a plurality of layers wherein at least one layer is annealed using in-situ rapid thermal annealing. In one implementation of the magnetic sensor a seed layer is annealed using in-situ rapid thermal annealing. Alternatively, one of a barrier layer, an antiferromagnetic (AFM) layer, and a cap layer is annealed using in-situ rapid thermal annealing.Type: GrantFiled: March 14, 2012Date of Patent: January 30, 2018Assignee: SEAGATE TECHNOLOGY LLCInventors: Qing He, Wonjoon Jung, Mark William Covington, Mark Thomas Kief, Yonghua Chen
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Patent number: 9865320Abstract: This technology provides an electronic device. An electronic device in accordance with an implementation of this document may include a semiconductor memory, and the semiconductor memory may include free layer having a variable magnetization direction; a tunnel barrier layer formed over the free layer; a pinned layer formed over the tunnel barrier layer and having a pinned magnetization direction; an exchange coupling layer formed over the pinned layer; and a magnetic correction layer formed over the exchange coupling layer, wherein the magnetic correction layer comprises a first magnetic layer, a spacer layer and a second magnetic layer that are sequentially stacked, and the first magnetic layer has a saturation magnetization smaller than a saturation magnetization of the second magnetic layer.Type: GrantFiled: May 20, 2016Date of Patent: January 9, 2018Assignee: SK hynix Inc.Inventors: Jung-Hwan Moon, Jeong-Myeong Kim, June-Seo Kim, Sung-Joon Yoon
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Patent number: 9842637Abstract: A magnetic memory device and a method of fabricating the same are provided. The method includes forming a first magnetic layer on a substrate, forming a tunnel barrier layer on the first magnetic layer, and forming a second magnetic layer on the tunnel barrier layer. The forming of the tunnel barrier layer includes forming a first metal oxide layer on the first magnetic layer, forming a first metal layer on the first metal oxide layer, forming a second metal oxide layer on the first metal layer, and performing a first thermal treatment process to oxidize at least a portion of the first metal layer.Type: GrantFiled: October 31, 2016Date of Patent: December 12, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ki Woong Kim, Juhyun Kim, Yong Sung Park, Sechung Oh, Joonmyoung Lee, Woo Chang Lim
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Patent number: 9793470Abstract: A method of manufacturing a magnetoresistive stack/structure comprising etching through a second magnetic region to (i) provide sidewalls of the second magnetic region and (ii) expose a surface of a dielectric layer; depositing a first encapsulation layer on the sidewalls of the second magnetic region and over the dielectric layer; etching (i) the first encapsulation layer which is disposed over the exposed surface of the dielectric layer and (ii) re-deposited material disposed on the dielectric layer, wherein, thereafter a portion of the first encapsulation layer remains on the sidewalls of the second magnetic region. The method further includes depositing a second encapsulation layer: (i) on the first encapsulation layer disposed on the sidewalls of the second magnetic region and (ii) over the exposed surface of the dielectric layer; and etching the remaining layers of the stack/structure (via one or more etch processes).Type: GrantFiled: February 2, 2016Date of Patent: October 17, 2017Assignee: Everspin Technologies, Inc.Inventors: Sarin A. Deshpande, Kerry Joseph Nagel, Chaitanya Mudivarthi, Sanjeev Aggarwal
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Patent number: 9768269Abstract: An interlayer is used to reduce Fermi-level pinning phenomena in a semiconductive device with a semiconductive substrate. The interlayer may be a rare-earth oxide. The interlayer may be an ionic semiconductor. A metallic barrier film may be disposed between the interlayer and a metallic coupling. The interlayer may be a thermal-process combination of the metallic barrier film and the semiconductive substrate. A process of forming the interlayer may include grading the interlayer. A computing system includes the interlayer.Type: GrantFiled: September 18, 2014Date of Patent: September 19, 2017Assignee: Intel CorporationInventors: Gilbert Dewey, Niloy Mukherjee, Matthew Metz, Jack T. Kavalieros, Nancy M. Zelick, Robert S. Chau
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Patent number: 9754996Abstract: The present disclosure relates to the fabrication of spin transfer torque memory elements for non-volatile microelectronic memory devices. The spin transfer torque memory element may include a magnetic tunneling junction connected with specifically sized and/or shaped fixed magnetic layer that can be positioned in a specific location adjacent a free magnetic layer. The shaped fixed magnetic layer may concentrate current in the free magnetic layer, which may result in a reduction in the critical current needed to switch a bit cell in the spin transfer torque memory element.Type: GrantFiled: June 23, 2014Date of Patent: September 5, 2017Assignee: Intel CorporationInventors: Brian S. Doyle, David L. Kencke, Charles C. Kuo, Dmitri E. Nikonov, Robert S. Chau
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Patent number: 9728210Abstract: A magnetic field-assisted magnetic recording (MAMR) head is provided, which includes a recording main pole and a texture control layer (TCL), a seed control layer, and a spin torque oscillator (STO) positioned over the main pole, in this order, in a stacking direction from a leading side to a trailing side of the recording head. The STO has a crystallographic preferred growth orientation and includes a spin polarized layer (SPL). The TCL may include a Cu layer.Type: GrantFiled: November 25, 2015Date of Patent: August 8, 2017Assignee: Western Digital Technologies, Inc.Inventors: Susumu Okamura, Yo Sato, Keiichi Nagasaka, Masashige Sato