Having Tunnel Junction Effect Patents (Class 360/324.2)
  • Patent number: 10665778
    Abstract: Methods and apparatuses for producing magneto resistive apparatuses are provided. Here, structures are formed for defining regions of the same magnetization, magnets are magnetized, and structures are formed within the magnets of the regions, for example, in order to define magneto resistive elements.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: May 26, 2020
    Assignee: Infineon Technologies AG
    Inventor: Wolfgang Raberg
  • Patent number: 10644226
    Abstract: A magnetic junction, a memory using the magnetic junction and method for providing the magnetic junction are described. The magnetic junction includes first and second reference layers, a main barrier layer, a free layer, an engineered secondary barrier layer and a second reference layer. The free layer is switchable between stable magnetic states when a write current is passed through the magnetic junction. The main barrier layer is between the first reference layer and the free layer. The secondary barrier layer is between the free layer and the second reference layer. The engineered secondary barrier layer has a resistance and a plurality of regions having a reduced resistance less than the resistance. The free and reference layers each has a perpendicular magnetic anisotropy energy and an out-of-plane demagnetization energy less than the perpendicular magnetic anisotropy energy.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: May 5, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Zheng Duan, Dmytro Apalkov, Vladimir Nikitin
  • Patent number: 10622550
    Abstract: A magnetoresistance effect element includes a bias layer comprised of an antiferromagnetic material and having a shape in which a first length in a first direction greater than a second length in a second direction perpendicular to the first direction, a recording layer comprised of a ferromagnetic material and being disposed on the bias layer, a direction of magnetization of the recording layer being reversible, a barrier layer comprised of an insulation material and being disposed on the recording layer, and a reference layer comprised of a ferromagnetic material and being disposed on the barrier layer, a direction of magnetization of the reference layer being substantially fixed.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: April 14, 2020
    Assignee: TOHOKU UNIVERSITY
    Inventors: Shunsuke Fukami, Hideo Ohno, Tetsuo Endoh
  • Patent number: 10586561
    Abstract: An apparatus according to one embodiment includes a sensor having an active region, a magnetic shield adjacent the active region, a spacer between the active region and the magnetic shield, a second magnetic shield on an opposite side of the active region as the magnetic shield, and a second spacer between the active region and the second magnetic shield. Both spacers include an electrically conductive ceramic layer. The electrically conductive ceramic layer of the spacer has a different composition than the electrically conductive ceramic layer of the second spacer.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: March 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Robert G. Biskeborn, Calvin S. Lo, Philip M. Rice, Teya Topuria
  • Patent number: 10586562
    Abstract: A hybrid dual reader. The hybrid dual reader includes first and second read sensors with conflicting design characteristics. The first read sensor includes at least one signal-to-noise ratio favoring design characteristic. The second read sensor includes at least one pulse width favoring design characteristic. The at least one signal-to-noise ratio favoring design characteristic is in conflict with the at least one pulse width favoring design characteristic.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: March 10, 2020
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Victor Sapozhnikov, Pavol Krivosik, Mohammed Shariat Ullah Patwari, Scott Wilson Stokes
  • Patent number: 10534047
    Abstract: Tunnel magneto-resistive (TMR) sensors employing TMR devices with different magnetic field sensitivities for increased detection sensitivity are disclosed. For example, a TMR sensor may be used as a biosensor to detect the presence of biological materials. In aspects disclosed herein, free layers of at least two TMR devices in a TMR sensor are fabricated to exhibit different magnetic properties from each other (e.g., MR ratio, magnetic anisotropy, coercivity) so that each TMR device will exhibit a different change in resistance to a given magnetic stray field for increased magnetic field detection sensitivity. For example, the TMR devices may be fabricated to exhibit different magnetic properties such that one TMR device exhibits a greater change in resistance in the presence of a smaller magnetic stray field, and another TMR device exhibits a greater change in resistance in the presence of a larger magnetic stray field.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: January 14, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Wei-Chuan Chen, Wah Nam Hsu, Xia Li, Seung Hyuk Kang, Nicholas Ka Ming Stevens-Yu
  • Patent number: 10497860
    Abstract: Some embodiments of the present disclosure relate to a method that achieves a substantially uniform pattern of magnetic random access memory (MRAM) cells with a minimum dimension below the lower resolution limit of some optical lithography techniques. A copolymer solution comprising first and second polymer species is spin-coated over a heterostructure which resides over a surface of a substrate. The heterostructure comprises first and second ferromagnetic layers which are separated by an insulating layer. The copolymer solution is subjected to self-assembly into a phase-separated material comprising a pattern of micro-domains of the second polymer species within a polymer matrix comprising the first polymer species. The first polymer species is then removed, leaving a pattern of micro-domains of the second polymer species. A pattern of magnetic memory cells within the heterostructure is formed by etching through the heterostructure while utilizing the pattern of micro-domains as a hardmask.
    Type: Grant
    Filed: January 8, 2016
    Date of Patent: December 3, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Ming Chen, Chern-Yow Hsu, Szu-Yu Wang, Chung-Yi Yu, Chia-Shiung Tsai, Xiaomeng Chen
  • Patent number: 10490737
    Abstract: The present invention is directed to a magnetic memory element including a magnetic free layer structure that includes two magnetic free layers separated by a magnesium perpendicular enhancement layer; an insulating tunnel junction layer formed adjacent to the magnetic free layer structure; a first magnetic reference layer formed adjacent to the insulating tunnel junction layer; a second magnetic reference layer separated from the first magnetic reference layer by a non-magnetic perpendicular enhancement layer; an anti-ferromagnetic coupling layer formed adjacent to the second magnetic reference layer; and a magnetic fixed layer structure formed adjacent to the anti-ferromagnetic coupling layer. The two magnetic free layers have a same variable magnetization direction substantially perpendicular to layer planes thereof. The first and second magnetic reference layers have a first invariable magnetization direction substantially perpendicular to layer planes thereof.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: November 26, 2019
    Assignee: Avalanche Technology, Inc.
    Inventors: Zihui Wang, Yiming Huai
  • Patent number: 10454021
    Abstract: The present disclosure provides a semiconductor structure, including an Nth metal layer, a bottom electrode over the Nth metal layer, a magnetic tunneling junction (MTJ) over the bottom electrode, a top electrode over the MTJ, and an (N+M)th metal layer over the Nth metal layer. N and M are positive integers. The (N+M)th metal layer surrounds a portion of a sidewall of the top electrode. A manufacturing method of forming the semiconductor structure is also provided.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: October 22, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Fu-Ting Sung, Chung-Chiang Min, Yuan-Tai Tseng, Chern-Yow Hsu, Shih-Chang Liu
  • Patent number: 10347823
    Abstract: A magnetoresistive element includes a channel layer, a first ferromagnetic layer, a second ferromagnetic layer, and a reference electrode. The first ferromagnetic layer, the second ferromagnetic layer, and the reference electrode are apart from each other and are electrically connected to each other through the channel layer. The average resistivity of a sixth region composed of a first region, a second region, and a fourth region is higher than the average resistivity of a seventh region composed of the second region, a third region, and a fifth region.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: July 9, 2019
    Assignee: TDK CORPORATION
    Inventor: Hayato Koike
  • Patent number: 10326074
    Abstract: Embodiments are directed to STT MRAM devices. One embodiment of an STT MRAM device includes a reference layer, a tunnel barrier layer, a free layer and one or more conductive vias. The reference layer is configured to have a fixed magnetic moment. In addition, the tunnel barrier layer is configured to enable electrons to tunnel between the reference layer and the free layer through the tunnel barrier layer. The free layer is disposed beneath the tunnel barrier layer and is configured to have an adaptable magnetic moment for the storage of data. The conductive via is disposed beneath the free layer and is connected to an electrode. Further, the conductive via has a width that is smaller than a width of the free layer such that a width of an active STT area for the storage of data in the free layer is defined by the width of the conductive via.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: June 18, 2019
    Assignee: International Business Machines Corporation
    Inventors: Michael C. Gaidis, Janusz J. Nowak, Daniel C. Worledge
  • Patent number: 10320404
    Abstract: Described is an oscillating apparatus which comprises: an interconnect with spin-coupling material (e.g., Spin Hall Effect (SHE) material); and a magnetic stack having two magnetic layers such that one of the magnetic layers is coupled to the interconnect, wherein each of the two magnetic layers have respective magnetization directions to cause the magnetic stack to oscillate.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: June 11, 2019
    Assignee: Intel Corporation
    Inventors: Sasikanth Sasi Manipatruni, George I. Bourianoff, Dmitri E. Nikonov, Ian A. Young
  • Patent number: 10297278
    Abstract: Structures and methods for fabrication servo and data heads of tape modules are provided. The servo head may have two shield layers spaced apart by a plurality of gap layers and a sensor. Similarly, the data head may have two shield layers spaced apart by a plurality of gap layers and a sensor. The distance between the shield layers of the servo head may be greater than the distance between the shield layers of the data head. The material of the gap layers may include tantalum or an alloy of nickel and chromium. The material for the gap layers permits deposition of gap layers with sufficiently small surface roughness to prevent distortion of the tape module and increase the stability of the tape module operation.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: May 21, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Satoru Araki, Diane L. Brown, Hiroaki Chihaya, Dustin W. Erickson, David J. Seagle
  • Patent number: 10283701
    Abstract: A magnetic junction and method for providing the magnetic junction are described. The method includes providing a pinned layer, a nonmagnetic spacer layer and a free layer switchable between stable magnetic states. The nonmagnetic spacer layer is between the pinned and free layers. Providing the pinned layer and/or providing the free layer includes cooling a portion of the magnetic junction, depositing a wetting layer while the portion of the magnetic junction is cooled, oxidizing/nitriding the wetting layer and depositing a boron-free magnetic layer on the oxide/nitride wetting layer. The portion of the magnetic junction is cooled to within a temperature range including temperature(s) not greater than 250 K. The wetting layer has a thickness of at least 0.25 and not more than three monolayers. The wetting layer includes at least one magnetic material. The boron-free magnetic layer has a perpendicular magnetic anisotropy energy greater than an out-of-plane demagnetization energy.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: May 7, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ikhtiar, Xueti Tang, Mohamad Towfik Krounbi
  • Patent number: 10263182
    Abstract: A magnetoresistance effect element is capable of realizing a high magnetoresistance (MR) ratio. The magnetoresistance effect element includes a laminate in which: an underlayer; a first ferromagnetic metal layer; a tunnel barrier layer; and a second ferromagnetic metal layer are laminated in that order. The underlayer is made of a nitride, the tunnel barrier layer is made of any one selected from a group consisting of MgAl2O4, ZnAl2O4, MgO, and ?-Al2O3, and a degree of lattice mismatching between a lattice constant of the tunnel barrier layer and a lattice constant of a crystal structure to be taken by the underlayer is 5% or less.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: April 16, 2019
    Assignee: TDK CORPORATION
    Inventor: Tomoyuki Sasaki
  • Patent number: 10217934
    Abstract: The present invention is directed to a method for manufacturing a memory cell that includes a magnetic memory element electrically connected to a two-terminal selector.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: February 26, 2019
    Assignee: Avalanche Technology, Inc.
    Inventors: Hongxin Yang, Dong Ha Jung, Jing Zhang, Bing K. Yen
  • Patent number: 10186656
    Abstract: A magnetic memory according to an embodiment includes: a first magnetic layer; a second magnetic layer; a first nonmagnetic layer disposed between the first magnetic layer and the second magnetic layer; a third magnetic layer disposed between the first magnetic layer and the first nonmagnetic layer; and a first layer disposed between the first magnetic layer and the third magnetic layer, wherein the first layer contains at least one element selected from the group consisting of Co, Fe, Ni, and Mn, and at least one element selected from the group consisting of Ta, Mo, Zr, Nb, Hf, V, Ti, Sc, and La.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: January 22, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Shumpei Omine, Takeshi Iwasaki, Masaki Endo, Akiyuki Murayama, Tadaomi Daibou, Tadashi Kai, Junichi Ito
  • Patent number: 10170687
    Abstract: The disclosed technology relates generally to magnetic devices, and more particularly to spin torque majority gate devices such as spin torque magnetic devices (STMG), and to methods of fabricating the same. In one aspect, a majority gate device includes a plurality of input zones and an output zone. A magnetic tunneling junction (MTJ) is formed in each of the input zones and the output zone, where the MTJ includes a non-magnetic layer interposed between a free layer stack and a hard layer. The free layer stack in turn includes a bulk perpendicular magnetic anisotropy (PMA) layer on a seed layer, a magnetic layer formed on and in contact with the bulk PMA layer, and a non-magnetic layer formed on the magnetic layer. Each of the bulk PMA layer and the seed layer is configured as a common layer for each of the input zones and the output zone.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: January 1, 2019
    Assignee: IMEC vzw
    Inventors: Johan Swerts, Mauricio Manfrini, Christoph Adelmann
  • Patent number: 10164177
    Abstract: A magnetic junction usable in a magnetic device and a method for providing the magnetic junction are described. A first portion of a magnetoresistive stack corresponding to the magnetic junction is provided. Providing this portion of the magnetoresistive stack includes providing at least one layer for a free layer of the magnetic junction. A second portion of the magnetoresistive stack is provided after the step of providing the first portion of the magnetoresistive stack. The magnetoresistive stack is patterned to provide the magnetic junction after the step of providing the second portion of the magnetoresistive stack. An ambient temperature for the magnetoresistive stack and the magnetic junction does not exceed a crystallization temperature of the free layer after the step of providing the free layer through the step of patterning the magnetoresistive stack.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: December 25, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sebastian Schafer, Dmytro Apalkov, Vladimir Nikitin, Don Koun Lee
  • Patent number: 10141037
    Abstract: According to one embodiment, a magnetic memory device includes a conductive layer, a first magnetic layer, a second magnetic layer, a first nonmagnetic layer, and a controller. The conductive layer includes a first portion, a second portion, and a third portion. The first magnetic layer is separated from the third portion. The first nonmagnetic layer is provided between the first magnetic layer and the second magnetic layer that is electrically connected with the third portion. The first nonmagnetic layer is curved. The controller is electrically connected to the first portion and the second portion. The controller implements a first operation and a second operation. The controller in the first operation supplies a first current to the conductive layer from the first portion toward the second portion. The controller in the second operation supplies a second current to the conductive layer from the second portion toward the first portion.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: November 27, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuichi Ohsawa, Hiroaki Yoda, Altansargai Buyandalai, Satoshi Shirotori, Mariko Shimizu, Hideyuki Sugiyama, Yushi Kato
  • Patent number: 10119988
    Abstract: An MLU-based accelerometer including: at least one MLU including a tunnel barrier layer between a first magnetic layer having a fixed first magnetization direction and a second magnetic layer having a second magnetization direction that can be varied. A proof-mass includes a ferromagnetic material having a proof-mass magnetization inducing a proof-mass field, the proof-mass being elastically suspended such as to be deflected in at least one direction when subjected to an acceleration vector. The proof-mass is magnetically coupled to the MLU cell via the proof-mass field. A read module is configured for determining a magnetoresistance of each MLU cell such as to determine an acceleration vector from the deflection of the proof-mass relative to any one of the at least one MLU cell.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: November 6, 2018
    Assignee: CROCUS TECHNOLOGY SA
    Inventor: Ali Alaoui
  • Patent number: 10101414
    Abstract: Thin film resistive sensors typically include a number of resistive components. These components should be well matched in order for the sensor to provide accurate readings. When a sensor is incorporated within an integrated circuit, the resistive components may be formed over, or under, metallic traces that form part of other components. As a result, the thin film resistive components are subjected to different levels of stress. This disclosure provides a structure that is arranged to mitigate the effects of stress.
    Type: Grant
    Filed: January 18, 2016
    Date of Patent: October 16, 2018
    Assignee: Analog Devices Global
    Inventors: Jan Kubik, Seamus P. Whiston, Padraig Michael Doran
  • Patent number: 10102870
    Abstract: A magnetic read head including a first read element magnetically coupled to a bottom shield; a second read element magnetically coupled to a top shield; a magnetic shielding structure that magnetically shields the first read element from the second read element; and a first electrical contact electrically coupled to the bottom shield, a second electrical contact electrically coupled to the top shield and a third electrical contact electrically coupled to the magnetic shielding structure.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: October 16, 2018
    Assignee: Seagate Technology LLC
    Inventor: Steven A. Mastain
  • Patent number: 10079338
    Abstract: The present invention is directed to a magnetic memory element including a magnetic free layer structure having a variable magnetization direction perpendicular to a layer plane thereof; an oxide layer formed adjacent to the magnetic free layer structure; an insulating tunnel junction layer formed adjacent to the magnetic free layer structure opposite the oxide layer; a first magnetic reference layer formed adjacent to the insulating tunnel junction layer opposite the magnetic free layer structure; a second magnetic reference layer separated from the first magnetic reference layer by a perpendicular enhancement layer; an antiferromagnetic coupling layer formed adjacent to the second magnetic reference layer; and a magnetic fixed layer structure formed adjacent to the antiferromagnetic coupling layer. The first and second magnetic reference layers have a first invariable magnetization direction substantially perpendicular to layer planes thereof.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: September 18, 2018
    Assignee: Avalanche Technology, Inc.
    Inventors: Yiming Huai, Huadong Gan, Bing K. Yen
  • Patent number: 10069062
    Abstract: A magnetoresistive element includes a laminated structure including a plurality of fixed layers, an intermediate layer formed of a non-magnetic material, and a recording layer, the plurality of fixed layers being laminated via a non-magnetic layer, the plurality of fixed layers having at least a first fixed layer and a second fixed layer, the following formula being satisfied: S1>S2 (wherein S1 is an area of a portion of the first fixed layer adjacent to the intermediate layer, which faces the intermediate layer, and S2 is an area of the fixed layer having the smallest area out of the fixed layers other than the first fixed layer).
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: September 4, 2018
    Assignee: Sony Corporation
    Inventors: Hiroyuki Uchida, Masanori Hosomi, Hiroyuki Ohmori, Kazuhiro Bessho, Yutaka Higo, Kazutaka Yamane
  • Patent number: 10054649
    Abstract: A magnetic sensor assembly includes first and second shields each comprised of a magnetic material. The first and second shields define a physical shield-to-shield spacing. A sensor stack is disposed between the first and second shields and includes a seed layer adjacent the first shield, a cap layer adjacent the second shield, and a magnetic sensor between the seed layer and the cap layer. At least a portion of the seed layer and/or the cap layer comprises a magnetic material to provide an effective shield-to-shield spacing of the magnetic sensor assembly that is less than the physical shield-to-shield spacing.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: August 21, 2018
    Assignee: Seagate Technology LLC
    Inventors: Eric W. Singleton, Qing He, Jae-Young Yi, Matt Johnson, Zheng Gao, Dimitar V. Dimitrov, Song S. Xue
  • Patent number: 10038137
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a magnetoresistive random access memory (MRAM) device in an insulating layer. The MRAM device includes a first electrode, a magnetic tunnel junction (MTJ) over the first electrode, a second electrode over the MTJ, and an insulating spacer surrounding sidewalls of the first electrode, the MTJ, and the second electrode. Top surfaces of the insulating spacer and the second electrode are exposed from the insulating layer. The semiconductor device structure also includes a conductive pad over the insulating layer and electrically connected to the second electrode. The MTJ is entirely covered by the conductive pad.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: July 31, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Harry-Hak-Lay Chuang, Sheng-Haung Huang, Hung-Cho Wang, Kuei-Hung Shen, Shy-Jay Lin
  • Patent number: 10002973
    Abstract: The present disclosure concerns a method of fabricating a magnetic tunnel junction suitable for a magnetic random access memory (MRAM) cell and comprising a first ferromagnetic layer, a tunnel barrier layer, and a second ferromagnetic layer, comprising: forming the first ferromagnetic layer; forming the tunnel barrier layer; and forming the second ferromagnetic layer; wherein said forming the tunnel barrier layer comprises depositing a layer of metallic Mg; and oxidizing the deposited layer of metallic Mg such as to transform the metallic Mg into MgO; the step of forming the tunnel barrier layer being performed at least twice such that the tunnel barrier layer comprises at least two layers of MgO.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: June 19, 2018
    Assignee: CROCUS TECHNOLOGY SA
    Inventors: Ioan Lucian Prejbeanu, Celine Portemont, Clarisse Ducruet
  • Patent number: 9997563
    Abstract: An embodiment integrates memory, such as spin-torque transfer magnetoresistive random access memory (STT-MRAM) within a logic chip. The STT-MRAM includes a magnetic tunnel junction (MTJ) that has an upper MTJ layer, a lower MTJ layer, and a tunnel barrier directly contacting the upper MTJ layer and the lower MTJ layer; wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer. Another embodiment includes a memory area, comprising a MTJ, and a logic area located on a substrate; wherein a horizontal plane intersects the MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the MTJ, and a second ILD material included in the logic area, the first and second ILD materials being unequal to one another. Other embodiments are described herein.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: June 12, 2018
    Assignee: Intel Corporation
    Inventors: Kevin J. Lee, Tahir Ghani, Joseph M. Steigerwald, John H. Epple, Yih Wang
  • Patent number: 9990944
    Abstract: An apparatus, according to one embodiment, includes: a tape head having: a write module, a read module, and a plurality of tunnel valve read transducers arranged in an array extending along the read module. Each of the tunnel valve read transducers includes: a sensor structure, an upper and lower magnetic shield, an upper conducting spacer layer between the sensor structure and the upper magnetic shield, a lower conducting spacer layer between the sensor structure and the lower magnetic shield, and electrically insulating layers opposite the sensor structure. The sensor structure includes a cap layer, a free layer, a tunnel barrier layer, a reference layer and antiferromagnetic layer. A height of the free layer measured in a direction perpendicular to a media bearing surface of the read module is less than a width of the free layer measured in a cross-track direction perpendicular to an intended direction of media travel.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: June 5, 2018
    Assignee: International Business Machines Corporation
    Inventors: Robert G. Biskeborn, Robert E. Fontana, Jr., Calvin S. Lo
  • Patent number: 9963780
    Abstract: A method for forming metal on a dielectric includes forming a seed layer on a surface including a reactant element. A first metal layer is formed on the seed layer wherein the first metal layer wets the seed layer. A second metal layer is formed on the first metal layer wherein the second metal layer wets the first metal layer. Diffuse the reactant element of the seed layer into the first metal layer by annealing to convert the first metal layer to a dielectric layer.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: May 8, 2018
    Assignee: International Business Machines Corporation
    Inventors: Guohan Hu, Daniel C. Worledge
  • Patent number: 9947866
    Abstract: A method of manufacturing a nonvolatile memory device includes sequentially forming, on a first wiring layer extending in a first direction, a first layer containing a first metal and a second layer containing a second metal into which the first metal can diffuse. The method further includes oxidizing the first layer and the second layer, removing oxygen from the oxidized first layer by annealing, forming a conductive third layer on the oxidized second layer after removing oxygen from the oxidized first layer, and forming a second wiring layer on the third layer. The second wiring layer extends in a second direction crossing the first wiring layer.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: April 17, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Kensuke Takahashi
  • Patent number: 9940955
    Abstract: A read head is provided with a scissors sensor. The read head may include a bottom magnetic shield, and a first non-magnetic seed layer, a magnetic seed layer, a second non-magnetic seed layer, an antiferromagnetic layer, a coupling layer, a first free magnetic layer, a spacer layer, and a second free magnetic layer positioned above the bottom magnetic shield, in this order. A pair of magnetic side shield layers may be positioned on respective sides of the second free magnetic layer.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: April 10, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventors: Kouichi Nishioka, Zheng Gao, Ching Tsang, Quang Le, Sangmun Oh
  • Patent number: 9923138
    Abstract: A memory device includes a magnetic tunnel junction comprising a first free layer, a pinned layer, and a tunnel barrier layer disposed between the first free layer and the pinned layer, wherein the first free layer comprises a first free magnetic pattern adjacent to the tunnel barrier layer, and a second free magnetic pattern spaced apart from the tunnel barrier layer with the first free magnetic pattern interposed therebetween, wherein the second free magnetic pattern contacts the first free magnetic pattern, wherein the first and second free magnetic patterns include boron (B), wherein a boron content of the first free magnetic pattern is higher than a boron content of the second free magnetic pattern, and wherein the boron content of the first free magnetic pattern is in a range of about 25 at % to about 50 at %.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: March 20, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang Hwan Park, Kwangseok Kim, Keewon Kim, Jae Hoon Kim, Joonmyoung Lee
  • Patent number: 9915707
    Abstract: Embodiments relate to xMR sensors having very high shape anisotropy. Embodiments also relate to novel structuring processes of xMR stacks to achieve very high shape anisotropies without chemically affecting the performance relevant magnetic field sensitive layer system while also providing comparatively uniform structure widths over a wafer, down to about 100 nm in embodiments. Embodiments can also provide xMR stacks having side walls of the performance relevant free layer system that are smooth and/or of a defined lateral geometry which is important for achieving a homogeneous magnetic behavior over the wafer.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: March 13, 2018
    Assignee: Infineon Technologies AG
    Inventors: Juergen Zimmer, Klemens Pruegl, Olaf Kuehn, Andreas Strasser, Ralf-Rainer Schledz, Norbert Thyssen
  • Patent number: 9880232
    Abstract: A magnetic sensor comprising a first shield and a second shield and a sensor stack between the first and the second shield, the sensor stack having a plurality of layers wherein at least one layer is annealed using in-situ rapid thermal annealing. In one implementation of the magnetic sensor a seed layer is annealed using in-situ rapid thermal annealing. Alternatively, one of a barrier layer, an antiferromagnetic (AFM) layer, and a cap layer is annealed using in-situ rapid thermal annealing.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: January 30, 2018
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Qing He, Wonjoon Jung, Mark William Covington, Mark Thomas Kief, Yonghua Chen
  • Patent number: 9865320
    Abstract: This technology provides an electronic device. An electronic device in accordance with an implementation of this document may include a semiconductor memory, and the semiconductor memory may include free layer having a variable magnetization direction; a tunnel barrier layer formed over the free layer; a pinned layer formed over the tunnel barrier layer and having a pinned magnetization direction; an exchange coupling layer formed over the pinned layer; and a magnetic correction layer formed over the exchange coupling layer, wherein the magnetic correction layer comprises a first magnetic layer, a spacer layer and a second magnetic layer that are sequentially stacked, and the first magnetic layer has a saturation magnetization smaller than a saturation magnetization of the second magnetic layer.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: January 9, 2018
    Assignee: SK hynix Inc.
    Inventors: Jung-Hwan Moon, Jeong-Myeong Kim, June-Seo Kim, Sung-Joon Yoon
  • Patent number: 9842637
    Abstract: A magnetic memory device and a method of fabricating the same are provided. The method includes forming a first magnetic layer on a substrate, forming a tunnel barrier layer on the first magnetic layer, and forming a second magnetic layer on the tunnel barrier layer. The forming of the tunnel barrier layer includes forming a first metal oxide layer on the first magnetic layer, forming a first metal layer on the first metal oxide layer, forming a second metal oxide layer on the first metal layer, and performing a first thermal treatment process to oxidize at least a portion of the first metal layer.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: December 12, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ki Woong Kim, Juhyun Kim, Yong Sung Park, Sechung Oh, Joonmyoung Lee, Woo Chang Lim
  • Patent number: 9793470
    Abstract: A method of manufacturing a magnetoresistive stack/structure comprising etching through a second magnetic region to (i) provide sidewalls of the second magnetic region and (ii) expose a surface of a dielectric layer; depositing a first encapsulation layer on the sidewalls of the second magnetic region and over the dielectric layer; etching (i) the first encapsulation layer which is disposed over the exposed surface of the dielectric layer and (ii) re-deposited material disposed on the dielectric layer, wherein, thereafter a portion of the first encapsulation layer remains on the sidewalls of the second magnetic region. The method further includes depositing a second encapsulation layer: (i) on the first encapsulation layer disposed on the sidewalls of the second magnetic region and (ii) over the exposed surface of the dielectric layer; and etching the remaining layers of the stack/structure (via one or more etch processes).
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: October 17, 2017
    Assignee: Everspin Technologies, Inc.
    Inventors: Sarin A. Deshpande, Kerry Joseph Nagel, Chaitanya Mudivarthi, Sanjeev Aggarwal
  • Patent number: 9768269
    Abstract: An interlayer is used to reduce Fermi-level pinning phenomena in a semiconductive device with a semiconductive substrate. The interlayer may be a rare-earth oxide. The interlayer may be an ionic semiconductor. A metallic barrier film may be disposed between the interlayer and a metallic coupling. The interlayer may be a thermal-process combination of the metallic barrier film and the semiconductive substrate. A process of forming the interlayer may include grading the interlayer. A computing system includes the interlayer.
    Type: Grant
    Filed: September 18, 2014
    Date of Patent: September 19, 2017
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Niloy Mukherjee, Matthew Metz, Jack T. Kavalieros, Nancy M. Zelick, Robert S. Chau
  • Patent number: 9754996
    Abstract: The present disclosure relates to the fabrication of spin transfer torque memory elements for non-volatile microelectronic memory devices. The spin transfer torque memory element may include a magnetic tunneling junction connected with specifically sized and/or shaped fixed magnetic layer that can be positioned in a specific location adjacent a free magnetic layer. The shaped fixed magnetic layer may concentrate current in the free magnetic layer, which may result in a reduction in the critical current needed to switch a bit cell in the spin transfer torque memory element.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: September 5, 2017
    Assignee: Intel Corporation
    Inventors: Brian S. Doyle, David L. Kencke, Charles C. Kuo, Dmitri E. Nikonov, Robert S. Chau
  • Patent number: 9728210
    Abstract: A magnetic field-assisted magnetic recording (MAMR) head is provided, which includes a recording main pole and a texture control layer (TCL), a seed control layer, and a spin torque oscillator (STO) positioned over the main pole, in this order, in a stacking direction from a leading side to a trailing side of the recording head. The STO has a crystallographic preferred growth orientation and includes a spin polarized layer (SPL). The TCL may include a Cu layer.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: August 8, 2017
    Assignee: Western Digital Technologies, Inc.
    Inventors: Susumu Okamura, Yo Sato, Keiichi Nagasaka, Masashige Sato
  • Patent number: 9715892
    Abstract: A data reader can be configured with at least a magnetoresistive stack contacting one or more magnetic shields. The magnetoresistive stack can be separated from a magnetic shield by a seed lamination on an air bearing surface with the seed lamination consisting of at least three sub-layers that are constructed with different material compositions.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: July 25, 2017
    Assignee: Seagate Technology LLC
    Inventors: Sameh Sayad Ali Hassan, Patrick G. McCafferty, Marcus W. Ormston, Kevin A. McNeill
  • Patent number: 9711171
    Abstract: A lateral spin valve reader that includes a detector structure located proximate to a bearing surface and a spin injection structure located away from the bearing surface. The lateral spin valve reader also includes a channel layer extending from the detector structure to the spin injection structure. An exterior cladding, disposed around the channel layer, suppresses spin-scattering at surfaces of the channel layer.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: July 18, 2017
    Assignee: Seagate Technology LLC
    Inventors: David A. Deen, Taras G. Pokhil
  • Patent number: 9666214
    Abstract: A magnetic read apparatus includes a read sensor, a shield structure and a side magnetic bias structure. The read sensor includes a free layer having a side and a nonmagnetic spacer layer. The shield structure includes a shield pinning structure and a shield reference structure. The nonmagnetic spacer layer is between the shield reference structure and the free layer. The shield reference structure is between the shield pinning structure and the nonmagnetic spacer layer. The shield pinning structure includes a pinned magnetic moment in a first direction. The shield reference structure includes a shield reference structure magnetic moment weakly coupled with the pinned magnetic moment. The side magnetic bias structure is adjacent to the side of the free layer.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: May 30, 2017
    Assignee: WESTERN DIGITAL (FREMONT), LLC
    Inventors: Gerardo A. Bertero, Shaoping Li, Qunwen Leng, Yuankai Zheng, Rongfu Xiao, Ming Mao, Shihai He, Miaoyin Wang
  • Patent number: 9653677
    Abstract: The present invention makes it possible to inhibit an MR ratio from decreasing by high-temperature heat treatment in a magnetoresistive effect element using a perpendicular magnetization film. The magnetoresistive effect element includes a data storage layer, a data reference layer, and an MgO film interposed between the data storage layer and the data reference layer. The data storage layer includes a CoFeB film coming into contact with the MgO film, a perpendicular magnetization film, and a Ta film interposed between the CoFeB film and the perpendicular magnetization film. The CoFeB film is magnetically coupled to the perpendicular magnetization film through the Ta film.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: May 16, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Eiji Kariyada, Katsumi Suemitsu
  • Patent number: 9620706
    Abstract: An apparatus includes a capping layer disposed on top of a free layer. The apparatus also includes a magnetic etch stop layer disposed on top of the capping layer. The capping layer and the magnetic etch stop layer are included in a spin-transfer torque magnetoresistive random access memory (STT-MRAM) magnetic tunnel junction (MTJ) device.
    Type: Grant
    Filed: December 2, 2014
    Date of Patent: April 11, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Kangho Lee, Chando Park, Jimmy Kan, Matthias Georg Gottwald, Xiaochun Zhu, Seung Hyuk Kang
  • Patent number: 9620154
    Abstract: A method operates a digital measurement unit and an ambient temperature control unit as to a plurality of TMR sensors, each having a geometry including area Amr and tunnel barrier thickness tB. The method includes dividing the plurality of TMR sensors into test groups. For each test group, the method includes setting the ambient air temperature Tair, applying a voltage pulse at Vdeg and time ?p Npulse times until dielectric breakdown, and appending Npulse and ?p to a dataset. The method includes fitting a survival fraction of form: S ? ( t deg , ? db ) = ? - ( t deg ? db ) ? versus Npulse, wherein tdeg=Npulse·?p, to determine ? and ?db. The method includes determining a temperature rise based on ?p, determining, based on the temperature rise, ?mr(?db,Amr), and determining T mr = T air + P mr ? mr ? ( ? db , A mr ) based on ?mr(?db,Amr).
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: April 11, 2017
    Assignee: International Business Machines Corporation
    Inventor: Icko E. T. Iben
  • Patent number: 9606197
    Abstract: Embodiments relate to xMR sensors having very high shape anisotropy. Embodiments also relate to novel structuring processes of xMR stacks to achieve very high shape anisotropies without chemically affecting the performance relevant magnetic field sensitive layer system while also providing comparatively uniform structure widths over a wafer, down to about 100 nm in embodiments. Embodiments can also provide xMR stacks having side walls of the performance relevant free layer system that are smooth and/or of a defined lateral geometry which is important for achieving a homogeneous magnetic behavior over the wafer.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: March 28, 2017
    Assignee: Infineon Technologies AG
    Inventors: Juergen Zimmer, Klemens Pruegl, Olaf Kuehn, Andreas Strasser, Ralf-Rainer Schledz, Norbert Thyssen
  • Patent number: 9595664
    Abstract: A magnetic cell structure including a nonmagnetic bridge, and methods of fabricating the structure are provided. The magnetic cell structure includes a free layer, a pinned layer, and a nonmagnetic bridge electrically connecting the free layer and the pinned layer. The shape and/or configuration of the nonmagnetic bridge directs a programming current through the magnetic cell structure such that the cross sectional area of the programming current in the free layer of the structure is less than the cross section of the structure. The decrease in the cross sectional area of the programming current in the free layer enables a lower programming current to reach a critical switching current density in the free layer and switch the magnetization of the free layer, programming the magnetic cell.
    Type: Grant
    Filed: January 13, 2015
    Date of Patent: March 14, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Jun Liu, Gurtej Sandhu