Head Amplifier Circuit Patents (Class 360/46)
  • Patent number: 10887167
    Abstract: Cloud-based orchestration may be leveraged to create flexible storage solutions that use continuous adaptation to tailor themselves to their target application workloads that made provide efficiencies in performance, cost, or scalability over conventional designs.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: January 5, 2021
    Assignee: AT&T Intellectual Property I, L.P.
    Inventors: Yu Xiang, Yih-Farn Chen, Kaustubh Joshi, Matti Hiltunen, Richard Schlichting, Keitaro Uehara
  • Patent number: 10854292
    Abstract: A sensing circuit of nonvolatile memory device includes a precharge current generator, an adjusting transistor, and an adaptive control voltage generator. The precharge current generator connected to a sensing node and generates a precharge current provided to a bit-line of the nonvolatile memory device, in response to a precharge signal. The adjusting transistor, connected between the sensing node and a first node, adjusts an amount of the precharge current provided to the bit-line in response to a first control voltage. The adaptive control voltage generator generates a control current proportional to an operating temperature, in response to the precharge signal and a second control voltage and boosts a level of the first control voltage in proportion to the operating temperature. The second control voltage is inversely proportional to the operating temperature.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: December 1, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Hyun-Jin Shin
  • Patent number: 10810990
    Abstract: An active noise cancellation (ANC) system including a selectable decimation rate decimator that receives an oversampled digital input and has an input that selects the decimation rate, a filter that receives an output of the decimator, and a selectable interpolation rate interpolator that receives an output of the filter and has an input that selects the interpolation rate. The selectable decimation rate decimator and the selectable interpolation rate interpolator operate to provide a selectable sample rate for the filter based on the selected decimation and interpolation rates. The filter may be an anti-noise filter, feedback filter, and/or a filter that models an acoustic transfer function of the ANC system. Rate selection may be static, or dynamically controlled based on battery or ambient noise level. A ratio of the decimation rate and the interpolation rate is fixed independent of the dynamically controlled decimation and interpolation rates.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: October 20, 2020
    Assignee: Cirrus Logic, Inc.
    Inventors: Gabriel Vogel, Jeffrey Alderson, Ryan A. Hellman, Nitin Kwatra
  • Patent number: 10797685
    Abstract: Methods, systems, and devices for jitter cancellation with automatic performance adjustment are described. Within a clock distribution system in an electronic device (e.g., a memory device), a jitter cancellation system may be configured to introduce delay between an input clock signal and output clock signal that is directly proportional to the supply voltage for the clock distribution system. In response to supply noise, the delay introduced by the jitter cancellation system may vary directly with respect to the supply voltage fluctuations and thus may offset fluctuations in the delay introduced by other components of the clock distribution system, which may vary inversely with respect to the supply voltage fluctuations. A control component within the jitter cancellation system may execute an algorithm to adjust or regulate the delay introduced by the jitter cancellation system, including its responsiveness to fluctuations in the supply voltage.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: October 6, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Dan Shi, Fangxing Wei, Michael J. Allen
  • Patent number: 10776023
    Abstract: In an embodiment, a storage device is provided. A device controller with a memory is coupled with the storage device. The memory stores an application with instructions that direct the controller to receive a storage device policy. The instructions further direct the controller to store content from a storage request in accordance with the storage device policy, and record storage information, including at least a content identifier, to the memory. Subsequent to storing the content, the instructions further direct the controller to retrieve the content according to the storage information received in a storage request. According to an implementation, the instructions further provide instruction to refuse a delete request in accordance to the storage information. According to an implementation, the instructions provide direction to store the storage information at a remote location.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: September 15, 2020
    Assignee: Gaea LLC
    Inventors: Joshua Johnson, Curt Bruner, Jeffrey Reh, Christopher Squires, Brian Wilson
  • Patent number: 10770100
    Abstract: A bias circuit comprises a closed loop gain stage arranged to determine a difference between a first current in a first branch circuit and a second current in a second branch circuit, where the first branch circuit and second branch circuit are coupled to respective terminals of a magnetic resistor (MR). A first set of current mirrors is arranged to provide a source current to the first terminal of the MR and the second set of current mirrors is arranged to provide a sink current to the second terminal of the MR. The first set of current mirrors and a second set of current mirrors are balanced to reduce a difference in setting time between the source current and sink current. The source current and sink current further reduce the difference between the first current and the second current to provide a constant voltage bias to the MR based on a voltage of a voltage source.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: September 8, 2020
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Xiaowei Huang, Mei Lei, Yunfan Zhang, Su Win Myat
  • Patent number: 10686365
    Abstract: A power supply controller having a shortened reset time due to a small hiccup voltage includes an electrical circuit providing a repeated voltage hiccup of a supply voltage of the controller of a switched-mode power supply (SMPS) when the controller enters a latched state. A plurality of comparators each have an input coupled with the controller supply voltage. A multiplexer and two latches are included, each coupled with one or more comparator outputs, and a restart controller is coupled with an output of one of the latches. The restart controller in various implementations toggles a switch to activate and deactivate a current sink to create the supply voltage hiccup. In other implementations, the switch is excluded and the restart controller toggles a voltage startup transistor to couple and decouple a voltage source with the supply voltage to create the voltage hiccup.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: June 16, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Zdenek Pfof, Jiri Bubla, Ivo Vecera
  • Patent number: 10643658
    Abstract: A disk apparatus includes a disk, a head, a circuit board, and an abnormality detection circuit. The head includes a plurality of loads, including at least a first load and a second load, associated with writing or reading of data to or from the disk, and a plurality of head terminals corresponding to and connected to the plurality of loads, respectively. The circuit board includes board terminals corresponding to and connected to the plurality of head terminals, respectively, and a preamplifier that applies a voltage to the loads via the plurality of board terminals during writing or reading of the data to or from the disk. The abnormality detection circuit detects a short-circuit between a first board terminal, which is the board terminal connected to the head terminal of the first load, and a second board terminal, which is the board terminal connected to the head terminal of the second load.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: May 5, 2020
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Nobuyoshi Yamasaki
  • Patent number: 10606790
    Abstract: In embodiments, an apparatus for serial communication includes a transceiver, to receive a precoding request from a downlink receiver across a serial communication link, and to transmit data bits to the downlink receiver over the serial communication link. In embodiments, the apparatus further includes a precoder, coupled to the transceiver, to: receive scrambled data bits of a subset of the data bits to be transmitted, from a coupled scrambler, and, in response to the request from the downlink receiver, precode the scrambled data bits, and output the precoded scrambled data bits to the transceiver, for transmission to the downlink receiver across the serial communication link together with other unscrambled data bits.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: March 31, 2020
    Assignee: Intel Corporation
    Inventor: Debendra Das Sharma
  • Patent number: 10510367
    Abstract: A method of operating a storage device includes reading data from a storage medium using a detector, processing signals from the detector through a plurality of processing circuits, each respective processing circuit in the plurality of processing circuits being optimized for a different state of a channel condition and providing a respective output metric, selecting a processing circuit from the plurality of processing circuits by comparing the respective output metrics from each processing circuit in a predetermined manner, and designating as output of the detector output of the processing circuit that is selected. The output metrics may be branch metrics or path metrics, and the channel condition may be fly-height or phase shift. The storage device includes a storage medium, and a read channel including a detector, and processing circuits that process signals from the detector. Each respective processing circuit is optimized for a different state of a channel condition.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: December 17, 2019
    Assignee: Marvell International Ltd.
    Inventors: Seyed Mehrdad Khatami, Mats Oberg, Michael Madden
  • Patent number: 10511224
    Abstract: Some embodiments include apparatus and methods using a charge pump coupled to a first supply power node and a second supply power node. The charge pump is arranged to transfer charge from the first supply power node to the second supply power node during a first time interval and to transfer charge from the second supply power node to the first supply power node during a second time interval.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: December 17, 2019
    Assignee: Intel Corporation
    Inventors: Jaydeep Kulkarni, Yong Shim, Pascal A. Meinerzhagen, Muhammad M. Khellah
  • Patent number: 10483999
    Abstract: An apparatus may include a circuit configured to generate, by an analog to digital converter (ADC), one or more ADC samples based on an input signal. The circuit may be further configured to generate a first estimated signal using a first channel pulse response estimation with a gain constraint based on the one or more ADC samples and generate a second estimated signal using a second channel pulse response estimation with a phase constraint based on the one or more ADC samples.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: November 19, 2019
    Assignee: Seagate Technology LLC
    Inventors: Zheng Wu, Jason Vincent Bellorado, Marcus Marrow
  • Patent number: 10476488
    Abstract: Methods, systems, and devices for jitter cancellation with automatic performance adjustment are described. Within a clock distribution system in an electronic device (e.g., a memory device), a jitter cancellation system may be configured to introduce delay between an input clock signal and output clock signal that is directly proportional to the supply voltage for the clock distribution system. In response to supply noise, the delay introduced by the jitter cancellation system may vary directly with respect to the supply voltage fluctuations and thus may offset fluctuations in the delay introduced by other components of the clock distribution system, which may vary inversely with respect to the supply voltage fluctuations. A control component within the jitter cancellation system may execute an algorithm to adjust or regulate the delay introduced by the jitter cancellation system, including its responsiveness to fluctuations in the supply voltage.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: November 12, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Dan Shi, Fangxing Wei, Michael J. Allen
  • Patent number: 10469290
    Abstract: An apparatus may include a circuit configured to process at least one input signal using a set of channel parameters. The circuit may adapt, using a regularized adaptation algorithm, a first set of channel parameters for use by the circuit as the set of channel parameters in processing the at least one input signal, the regularized adaptation algorithm penalizing deviations by the first set of channel parameters from a corresponding predetermined second set of channel parameters. The circuit may then perform the processing of the at least one input signal using the first set of channel parameters as the set of channel parameters.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: November 5, 2019
    Assignee: Seagate Technology LLC
    Inventors: Marcus Marrow, Jason Bellorado
  • Patent number: 10388314
    Abstract: Apparatus and method for reducing the effects of thermal asperities on a rotatable data recording surface. A data transducer writes user data to a first set of tracks at a first fly height above the recording surface. A compensation circuit detects a thermal asperity (TA) on the recording surface, and establishes a guard band as a second set of tracks that are co-radial with the TA. The second set of tracks are deallocated and removed from service. The compensation circuit further defines a reserve band as a third set of tracks immediately adjacent the guard band, and selects an increased, second fly height that allows the data transducer to write data to the reserve band without contacting the TA. The second set of tracks may have a greater track pitch than the first set of tracks to compensate for the greater fly height.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: August 20, 2019
    Assignee: Seagate Technology LLC
    Inventors: Xiong Liu, Lan Xia, Quan Li, Lihong Zhang, Swee Chuan Samuel Gan
  • Patent number: 10366711
    Abstract: A pattern is pre-written using a pre-erase or pre-conditioning magnetic field applied within at least part of a target track of a hard disk via a first write transducer prior to the target track being written. Subsequent to the pre-writing, target user data is written to the part of the target track.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: July 30, 2019
    Assignee: Seagate Technology LLC
    Inventors: Yanzhang Liu, Javier Ignacio Guzman, Zuxuan Lin, Kirill Aleksandrovich Rivkin
  • Patent number: 10355674
    Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a first stage that receives an enable signal and an input clock signal and provides a first intermediate signal based on the enable signal and the input clock signal. The integrated circuit may include a second stage that receives the first intermediate signal and the input clock signal and provides a second intermediate signal based on a ternary logic response to the first intermediate signal and the input clock signal. The integrated circuit may include a third stage that receives the second intermediate signal and the input clock signal and provides an output clock signal based on the second intermediate signal and the input clock signal.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: July 16, 2019
    Assignee: ARM Limited
    Inventors: Anil Kumar Baratam, Nruthya Nagesh Prabhu, Yves Thomas Laplanche
  • Patent number: 10339439
    Abstract: Systems and methods achieving scalable and efficient connectivity in neural algorithms by re-calculating network connectivity in an event-driven way are disclosed. The disclosed solution eliminates the storing of a massive amount of data relating to connectivity used in traditional methods. In one embodiment, a deterministic LFSR is used to quickly, efficiently, and cheaply re-calculate these connections on the fly. An alternative embodiment caches some or all of the LFSR seed values in memory to avoid sequencing the LFSR through all states needed to compute targets for a particular active neuron. Additionally, connections may be calculated in a way that generates neural networks with connections that are uniformly or normally (Gaussian) distributed.
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: July 2, 2019
    Assignee: Thalchemy Corporation
    Inventors: Mikko H. Lipasti, Andrew Nere, Atif Hashmi, John F. Wakerly
  • Patent number: 10255943
    Abstract: An apparatus may include a preamplifier configured to be connected to a plurality of magnetic read/write heads, wherein each of the magnetic read/write heads includes a read sensor to read data from a disc and a write element to write data to the disc. The preamplifier may include a first set of registers configured to indicate a first head of the plurality of magnetic read/write heads that is selected for reading data, a second set of registers configured to indicate a second head of the plurality of magnetic read/write heads that is selected for reading data, an input line configured to receive a control signal to activate reading data from the first head substantially simultaneously with reading data from the second head, a first output to provide data from the first head, and a second output to provide data from the second head.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: April 9, 2019
    Assignee: Seagate Technology LLC
    Inventors: Thomas Lee Schick, Timothy F Ellis
  • Patent number: 10250125
    Abstract: A power supply controller having a shortened reset time due to a small hiccup voltage includes an electrical circuit providing a repeated voltage hiccup of a supply voltage of the controller of a switched-mode power supply (SMPS) when the controller enters a latched state. A plurality of comparators each have an input coupled with the controller supply voltage. A multiplexer and two latches are included, each coupled with one or more comparator outputs, and a restart controller is coupled with an output of one of the latches. The restart controller in various implementations toggles a switch to activate and deactivate a current sink to create the supply voltage hiccup. In other implementations, the switch is excluded and the restart controller toggles a voltage startup transistor to couple and decouple a voltage source with the supply voltage to create the voltage hiccup.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: April 2, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Zdenek Pfof, Jiri Bubla, Ivo Vecera
  • Patent number: 10242708
    Abstract: A disk apparatus includes a disk, a head, a circuit board, and an abnormality detection circuit. The head includes a plurality of loads, including at least a first load and a second load, associated with writing or reading of data to or from the disk, and a plurality of head terminals corresponding to and connected to the plurality of loads, respectively. The circuit board includes board terminals corresponding to and connected to the plurality of head terminals, respectively, and a preamplifier that applies a voltage to the loads via the plurality of board terminals during writing or reading of the data to or from the disk. The abnormality detection circuit detects a short-circuit between a first board terminal, which is the board terminal connected to the head terminal of the first load, and a second board terminal, which is the board terminal connected to the head terminal of the second load.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: March 26, 2019
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Nobuyoshi Yamasaki
  • Patent number: 10218166
    Abstract: Systems and methods for monitoring a regulated voltage output for current consumption are disclosed. An analog component senses the current at the regulated voltage output and converts the sensed current into a digital representation, which is indicative of the sensed current. A digital component inputs and analyzes the digital representation to determine whether to generate an interrupt. The interrupt is indicative to an electronic device, which is using the regulated voltage, to modify its operation. For example, the digital component may analyze the digital representation by counting a number of system clock cycles during a part of the digital representation. The counted number of clock cycles may be compared with a threshold, which may be predetermined or dynamically selected, to determine whether to generate an interrupt. Thus, the sensed current from the regulated voltage output may be used to determine whether to modify operation of the electronic device.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: February 26, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Simon Bass, Vitali Linkovsky, Leonid Minz, Michael Tomashev, Yair Baram
  • Patent number: 10199056
    Abstract: In certain embodiments, an apparatus may comprise a first output driver connected to a first output via a first trace and a second output driver connected to a second output via a second trace. The first output driver may be configured to output a first drive signal to the first output to drive the first output and the first drive signal may cause first induced noise in the second trace. Further, the second output driver may be configured to output a second drive signal based on the first drive signal where the second drive signal may reduce the magnitude of the first induced noise at the second output.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: February 5, 2019
    Assignee: Seagate Technology LLC
    Inventors: Todd Michael Lammers, JianHua Xue, Javier I. Guzman, Andrew Thomas Jaeb, Bruce Douglas Buch
  • Patent number: 10186296
    Abstract: A method for redundantly storing data includes receiving data at a storage controller, partitioning the data into a plurality of data blocks, generating a first error correction code associated with a first page within the plurality of data blocks, and generating a first redundancy code associated with at least two data blocks within the plurality of data block. The first redundancy code provides additional error recovery if the first error correction code fail. The method further includes storing the plurality of data blocks, the first error correction code, and the first redundancy code across a plurality of solid state storage devices.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: January 22, 2019
    Assignee: Marvell World Trade Ltd.
    Inventors: Gregory Burd, Nedeljko Varnica, Heng Tang
  • Patent number: 10135548
    Abstract: An apparatus, system, and method are provided for at least mitigating a signal reflection. Included is a filter configured to receive a data signal for transmission, and filter the data signal to generate a filtered data signal. Also included is a gain regulator in electrical communication with the filter. The gain regulator is configured to receive the filtered data signal for adjusting a gain of the filtered data signal to generate a gain regulator output signal for use in at least mitigating a signal reflection. Further, a controller is provided in electrical communication with the filter and the gain regulator. The controller is configured to receive the filtered data signal, and process the filtered data signal to generate at least one controller output signal for use in controlling the filter and the gain regulator.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: November 20, 2018
    Assignee: FUTUREWEI TECHNOLOGIES, INC.
    Inventors: Hiroshi Takatori, Zhan Duan, Purackal M. Mammen
  • Patent number: 10124758
    Abstract: A microcontroller uses a combination of several synchronized PWM outputs to generate a low distortion sine wave by summing the PWM outputs and filtering the summed signal. The sine wave is used as a guard voltage. The unknown impedance is measured by impinging the guard voltage on the sense electrode by a transistor connected in common base configuration and then transferring the sense current through the common base connected transistor to a transimpedance amplifier made out of a second transistor connected in common emitter configuration. The output voltage at the collector of the second transistor is measured by an ADC input of the microcontroller. The microcontroller translates the ADC output values into the unknown impedance to be measured by doing a software demodulation of the ADC output values. A reference impedance can be connected in parallel to the unknown impeder to eliminate gain errors of the signal sensing circuit.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: November 13, 2018
    Assignee: IEE INTERNATIONAL ELECTRONICS & ENGINEERING S.A.
    Inventor: Laurent Lamesch
  • Patent number: 10073123
    Abstract: Systems and techniques relating to voltage signal peak level detection used in sensor devices, namely in Fly-Height Sensors (FHS) devices include, according to an aspect, an integrated chip device comprising: peak detection circuitry configured to receive a voltage signal and output a peak voltage signal associated with a peak voltage level of the voltage signal, wherein the peak detection circuitry comprises: a linear loop section configured to store the peak voltage level and hold additional voltage levels of the voltage signal at an output terminal of an amplifier to a value greater than zero; and a feedback loop section configured to reduce a leakage current within the peak detection circuitry and generate a guard voltage signal usable to reduce a feedback voltage and prevent the feedback voltage from successively re-entering into the feedback loop section.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: September 11, 2018
    Assignee: Marvell International Ltd.
    Inventor: Xiao Yu Miao
  • Patent number: 10043588
    Abstract: A memory device includes a normal cell array, a parity cell array, and a plurality of normal write drivers suitable for writing normal write data in the normal cell array. The memory device also includes a plurality of parity write drivers suitable for writing parity write data corresponding to the normal write data, in the parity cell array, and an error injection circuit suitable for injecting error write data to at least one among the plurality of the normal write drivers and the plurality of the parity write drivers to exactly analyze an error of the memory device.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: August 7, 2018
    Assignee: SK Hynix Inc.
    Inventor: Sang-Jin Byeon
  • Patent number: 10037779
    Abstract: One or more magnetic recording disks are coupled to a spindle motor, each of the disks having opposing recording surfaces. Two or more actuators are moveable independently over at least a first recording surface of the one or more disks. A first actuator of the two or more actuators comprises a first write head and a first read head. A second actuator of the two or more actuators comprises at least a second read head and may include a second write head. A controller is coupled to the two or more actuators and configured to write data to a track on the first recording surface using the first write head, and perform a read operation on the data written to the track using the second read head. The controller is also configured to verify that the data was successfully written to the track in response to the read operation. The read operation can be performed within less than one revolution of the first recording surface after the write operation.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: July 31, 2018
    Assignee: Seagate Technology LLC
    Inventors: Riyan Mendonsa, Jason Bryce Gadbois, Mark Allen Gaertner, Guy T. Lawrence, Bruce Douglas Buch
  • Patent number: 10013009
    Abstract: A fault tolerant voltage regulator may include a plurality of operational transconductance amplifiers. The plurality of operational transconductance amplifiers may be configured according to a unity-gain configuration. The plurality of operational transconductance amplifiers may be configured to couple in parallel to a load. The plurality of operational transconductance amplifiers may be configured to load share a load current associated with the load approximately equally among the plurality of operational transconductance amplifiers.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: July 3, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Mark Bryan Hamlyn
  • Patent number: 10002624
    Abstract: According to one embodiment, a magnetic disk device includes a disk, a head configured to write data to the disk, and an integrated circuit configured to acquire a detection signal indicative of a first pattern of a first frequency of write data, change a first current of a second pattern of a write current corresponding to the first pattern on the basis of the detection signal, detect a third pattern of a second frequency which is greater than the first frequency from the write data, change a second current of a fourth pattern of the write current corresponding to the third pattern, and output the write current with the changed first current and the changed second current to the head.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: June 19, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshihiro Amemiya
  • Patent number: 10002637
    Abstract: According to one embodiment, a magnetic recording and reproducing device which has a magnetic recording medium, a magnetic head, and a recording current output unit. Magnetic data is recorded on the magnetic recording medium. The magnetic head records the magnetic data on the magnetic recording medium. The recording current output unit supplies a recording current to the magnetic head so as to magnetize the magnetic head. A waveform of the recording current has a first slope for a first period to record data of first information continuously and a second slope for a following second period to switch the data to data of second information and to record the data of the second information. The first slope and the second slope are different from each other.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: June 19, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naoyuki Narita, Kenichiro Yamada, Masayuki Takagishi, Tomoko Taguchi
  • Patent number: 9998136
    Abstract: An apparatus may include a circuit configured to generate, by an analog to digital converter (ADC), one or more ADC samples based on an input signal. The circuit may be further configured to generate a first estimated signal using a first channel pulse response estimation with a gain constraint based on the one or more ADC samples and generate a second estimated signal using a second channel pulse response estimation with a phase constraint based on the one or more ADC samples.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: June 12, 2018
    Assignee: Seagate Technology LLC
    Inventors: Zheng Wu, Jason Vincent Bellorado, Marcus Marrow
  • Patent number: 9953674
    Abstract: A data storage device is disclosed comprising a disk, a head for accessing the disk, and a sensor for generating an alternating sensor signal. The sensor is disconnected from an input of a sensing circuit and while the sensor is disconnected an alternating calibration signal is injected into the input of the sensing circuit, wherein the alternating calibration signal comprises a predetermined offset and amplitude. A response of the sensing circuit to the alternating calibration signal is evaluated to detect at least one of an offset and a gain of the sensing circuit.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: April 24, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventors: Paul Dylan Sherman, Tuyetanh Thi Dang
  • Patent number: 9952265
    Abstract: A display may have a substrate layer to which a display driver integrated circuit and flexible printed circuit are bonded. The display driver integrated circuit may be provided with switches and control circuitry for controlling the operation of the switches during bond resistance measurements. Test equipment may apply currents to pads in the display driver integrated circuit through contacts in the flexible printed circuit while controlling the switching circuitry. Based on these measurements and the measurement of trace resistances in a dummy flexible printed circuit, the test equipment may determine bond resistances for bonds between the display driver integrated circuit and the display substrate and between the flexible printed circuit and the display substrate. Displays may have master and slave display driver integrated circuits that share coarse reference voltages produced by the master from raw power supply voltages.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: April 24, 2018
    Assignee: Apple Inc.
    Inventors: Kingsuk Brahma, David A. Stronks, Hopil Bae, Wei H. Yao
  • Patent number: 9934712
    Abstract: The present invention relates to a display, a timing controller and a column driver IC, and more particularly to a display, timing controller and column driver integrated circuit using clock embedded multi-level signaling. The present invention provides a timing controller including a transmitter for transmitting a transmission signal wherein a transmission clock signal is embedded therein between a transmission data signal to have a signal magnitude different from that of the transmission data signal. The present invention also provides a column driver integrated circuit including a receiving unit for separating a clock signal from a received signal using a magnitude of the received signal, and for performing a sampling of a received data signal from the received signal using the separated clock signal.
    Type: Grant
    Filed: November 10, 2005
    Date of Patent: April 3, 2018
    Assignee: ANAPASS INC.
    Inventor: Yong-Jae Lee
  • Patent number: 9922678
    Abstract: Systems and techniques include a method including: receiving a data request for first data stored at a storage device; reading second data from discrete units of storage of the storage device, the second data comprising the first data read from two or more of the discrete units of storage, error correction code redundancies read from the two or more of the discrete units of storage, and parity data read from at least one of the discrete units of storage; detecting, based on the error correction code redundancies, an error in a first portion of the first data stored in one of the two or more of the discrete units of storage; and recovering the first portion of the first data using the parity data and a second portion of the first data read from one or more remaining ones of the two or more of the discrete units of storage.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: March 20, 2018
    Assignee: Marvell World Trade Ltd.
    Inventors: Gregory Burd, Nedeljko Varnica, Heng Tang
  • Patent number: 9910603
    Abstract: Techniques for storing data on a tape using a heterogeneous data storage technique are described herein. A logical partition from a logical model of a data storage tape is associated with a set of data. If a current location of the data storage tape corresponds to the logical partition of the set of data, a first data transfer operation associated with the set of data is performed using the data storage tape. The data transfer operation is monitored and changes to the data transfer rate of the data transfer operation are used to update the logical extent of the tape and to update the logical model. If the current location of the data storage tape does not correspond to the logical partition of the set of data, the data set is staged for later storage.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: March 6, 2018
    Assignee: AMAZON TECHNOLOGIES, INC.
    Inventor: Bryan James Donlan
  • Patent number: 9898517
    Abstract: Methods and apparatus, including computer systems and program products, related to declarative synchronization of shared data. One method includes receiving one or more changes to data maintained by one of multiple computer programs having respective local copies of the data, identifying an event characterizing synchronization of the data maintained by the computer program with the other computer programs (e.g., with a local copy managed by the other computer program), and initiating synchronization of the changes with one of the other programs having respective local copies (e.g., with the local copy managed by the other program) in response to the event occurring. The event can be characterized by an annotation. Identifying an event can include reading a property of a data object (e.g., in a data object graph of shared data).
    Type: Grant
    Filed: April 21, 2006
    Date of Patent: February 20, 2018
    Assignee: ADOBE SYSTEMS INCORPORATED
    Inventor: Jason Staczek
  • Patent number: 9870789
    Abstract: According to one embodiment, a magnetic disk device includes a magnetic recording medium, a head including a recording magnetic pole, a spin torque oscillator provided near the recording magnetic pole, and a coil which excites the recording magnetic pole, a first current supply which supplies the coil with a first current corresponding to write data, a detector which detects a first signal corresponding to the write data, and outputs a second signal in accordance with the first signal, and a second power supply which varies, in accordance with the second signal, a second current supplied to the spin torque oscillator.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: January 16, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tomomi Funayama
  • Patent number: 9858603
    Abstract: A card reader is provided with a read head with a slot and is configured to be coupled to a mobile device and has a slot for swiping a magnetic stripe of a card. The read head reads data on the magnetic stripe and produces a raw magnetic signal indicative of data stored on the magnetic stripe. A power supply is coupled to wake-up electronics and a microcontroller. An output jack is adapted to be inserted in a port of the mobile device and deliver an output jack signal to the mobile device. The wake-up electronics is powered by a microphone bias of a mobile device.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: January 2, 2018
    Assignee: Square, Inc.
    Inventors: Kartik Lamba, Amish Babu, Michael Shyh-yen Ho, Adam David Peter Rothschild, Gerald Thomas Ryle, Jack Dorsey, James M. McKelvey
  • Patent number: 9812158
    Abstract: A slider of a magnetic recording head comprises a plurality of electrical bond pads coupled to bias sources and a ground pad. Each of a plurality of electrical components of the slider is coupled one or more of the electrical bond pads, wherein at least one of the electrical bond pads is a shared electrical bond pad coupled to at least a first electrical component and a second electrical component. A switching transistor is coupled to the first and second components and the ground pad. The switching transistor is arranged to control powering of the second component in response to biasing of the first component.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: November 7, 2017
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Narayanan Ramakrishnan, Declan Macken
  • Patent number: 9806685
    Abstract: A wide dynamic range trans-impedance amplifier includes a first trans-impedance amplifier configured to receive a first input current and produce a first voltage as a function of the first input current, and a second trans-impedance amplifier configured to receive a second input current and produce a second voltage as a function of the second input current. A current steering element causes a first portion of current from a current source to flow to the first trans-impedance amplifier until the first current portion reaches the first threshold current, and causes a second portion of current from the current source to flow to the second trans-impedance amplifier, until the second current portion reaches the second threshold current. The second current portion is current from the current source that exceeds the first threshold current. The wide dynamic range trans-impedance amplifier may receive, for example, ion collector current from a hot cathode ionization gauge (HCIG).
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: October 31, 2017
    Assignee: MKS Instruments, Inc.
    Inventor: Douglas C. Hansen
  • Patent number: 9787513
    Abstract: The present invention relates to a transmitter, a receiver and to corresponding methods for transmitting and receiving data utilizing sequences of non-return-to-zero, inverted (NRZI) symbols and symbol rates higher than the Nyquist rate in data transmission systems, thus enabling an enlarged spectral efficiency while utilizing simple receivers only having sign information.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: October 10, 2017
    Assignee: VODAFONE GMBH
    Inventors: Lukas Landau, Gerhard Fettweis
  • Patent number: 9761268
    Abstract: A circuit may be configured to precompensate the storage of data on a storage device. The magnitude and polarity of the precompensated time adjustment can be determined by looking up data patterns of storage regions in a table. A boundary can include storage regions of the device used to determine the precompensation.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: September 12, 2017
    Assignee: Seagate Technology LLC
    Inventors: Jon David Trantham, Rodney Blake, William Radich
  • Patent number: 9754610
    Abstract: A storage system includes a magnetic write head, a magnetic storage medium, a write data circuit having a write data output and a magnet length signal output, and a preamplifier that receives the write data and a magnet length signal from the write data circuit, and sets at least one write current characteristic through the magnetic write head based at least in part on the magnet length signal. The write data circuit processes write data to be recorded on the magnetic storage medium by the magnetic write head. The magnet length signal output communicates magnet lengths in the write data.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: September 5, 2017
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Bruce A. Wilson, Ross S. Wilson, Peter J. Windler
  • Patent number: 9741355
    Abstract: The present invention provides methods and systems for narrow bandwidth digital processing of an input audio signal. Particularly, the present invention includes a high pass filter configured to filter the input audio signal. A first compressor then modulates the filtered signal in order to create a partially processed signal. In some embodiments, a clipping module further limits the gain of the partially processed signal. A splitter is configured to split the partially processed signal into a first signal and a second signal. A low pass filter is configured to filter the first signal. A pass through module is configured to adjust the gain of the second signal. A mixer then combines the filtered first signal and the gain-adjusted second signal in order to output a combined signal. In some embodiments, a tone control module further processes the combined signal, and a second compressor further modulates the processed signal.
    Type: Grant
    Filed: February 16, 2016
    Date of Patent: August 22, 2017
    Assignee: Bongiovi Acoustics LLC
    Inventors: Anthony Bongiovi, Glenn Zelniker, Joseph G. Butera, III
  • Patent number: 9715887
    Abstract: A storage system includes a magnetic write head, a magnetic storage medium, a channel circuit comprising a write data output, wherein the channel circuit is operable to process write data to be recorded on the magnetic storage medium by the magnetic write head, and a preamplifier operable to receive the write data from the channel circuit, wherein the preamplifier comprises a number of register pages configured to store pattern dependent write current characteristics for a variety of magnet lengths, and wherein the preamplifier is operable to retrieve the write current characteristics based on magnet lengths and to record data bits on the magnetic storage medium using the write current characteristics.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: July 25, 2017
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Ross S. Wilson, Peter J. Windler, Bruce A. Wilson, Jaydip Bhaumik, Scott M. O'Brien, Jason P. Brenden, Jeffrey A. Gleason, Cameron C. Rabe
  • Patent number: 9691415
    Abstract: According to one embodiment, a disk device includes a disk includes a recording layer, a recording head includes a main pole configured to apply a recording magnetic field onto the recording layer, and a microwave oscillator adjacent to the main pole, configured to apply a microwave magnetic field to the recording layer, a current supply circuit configured to supply a current to the microwave oscillator, and a switching circuit configured to switch a direction of current flow to the microwave oscillator.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: June 27, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Katsuhiko Koui
  • Patent number: 9690484
    Abstract: Various embodiments of the present invention that include arranging a first storage device and second storage device to store data in a mirrored configuration. Upon receiving a message indicating that the first storage device is in an error recovery mode, the host processor can convey a second request to read the data from the second storage device. The storage device is selected from a list comprising a hard disk drive and a solid state disk drive, and the hard disk drive comprises a disk head having a magnetoresistive (MR) element configured to read and write data to and from the storage media, and coupled to an analog/digital (A/D) converter, and wherein the error recovery operation is selected from a list comprising changing an automatic gain control of the A/D converter, positioning the disk head off-track in order to read the data, and adjusting a bias value of the MR element.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: June 27, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven F. Best, Janice M. Girouard, Robert E. Reiland, Yehuda Shiran