Abstract: Apparatus, methods, and systems are disclosed for performing bit error correction on a data stream. In some aspects, the described systems and methods may include a plurality of memory devices, a first interface, and a field programmable gate array. The field programmable gate array may include a memory controller and a plurality of re-programmable gates. At least one of the re-programmable gates may be configured as a read-only memory (ROM) to store a syndrome decode memory table, wherein the syndrome decode memory table may be configured to perform bit error correction on the data stream being read and/or written to at least one memory device of the plurality of memory devices via the first interface.

Abstract: Systems and methods are disclosed for detection of a servo sector on a data storage medium. A circuit may be configured to sample a signal, and determine preamble sample values from the sample values that correspond to a preamble pattern. When a preamble is detected, the circuit may continue to perform preamble detection, as well as determine signal reading parameters to apply during a servo timing mark (STM) search state based on the preamble sample values. In response to locating the STM, the circuit may generate an indication that the STM is located. In response to not locating the STM, the circuit may extend an STM search timeout period when the preamble pattern is still detected, or increment an STM search counter when the preamble pattern is not detected. The circuit may exit the STM search state when the STM search counter exceeds the STM search timeout period.

Abstract: Systems, methods, and circuitries for synchronizing a first phase locked loop (PLL) with a second PLL are provided. In one example a PLL system includes a first PLL configured to generate a first signal; a second PLL configured to generate a second signal; and phase calculation circuitry. The phase calculation circuitry is configured to calculate a phase of the first signal at a given time; and provide the calculated phase to the second PLL for use by the second PLL in synchronizing a phase of the second with the phase of the first signal.

Abstract: A magnetic disc device according to an embodiment has a head, a position detector, and a filter unit. The position detector detects position information of the head on the basis of servo information. The filter unit performs filtering of an estimated frequency estimated by a quadratic adaptive digital filter that performs self-adaptation for a transfer function on the basis of positional difference information between position information and target position information of the head and adjusts all filter coefficients included in the transfer function on the basis of the estimated frequency.

Abstract: A storage apparatus includes a storage disk including a plurality of tracks each of which includes a plurality of sectors, a head configured to write data in and read data from the storage disk, and a controller. The controller is configured to control the head to carry out reading of a group of data units from target sectors in a target track of the storage disk, the group of data units being associated with a command received from an external device, determine whether or not the target sectors include one or more defective sectors based on result of the reading, and control the head to write the group of data units in physically consecutive non-written sectors of the target track or another track, when the target sectors are determined to include the defective sectors.

Abstract: A data storage device is disclosed comprising a disk comprising servo data, and an actuator configured to actuate a head over the disk. A servo controller is configured to generate digital control values at a first sample rate based on the servo data and transmit the digital control values over a serial interface to a driver circuit. The driver circuit is configured to generate predictive oversampled control values at a second sample rate higher than the first sample rate based on at least two of the digital control values received from the servo controller, apply the predictive oversampled control values to a digital-to-analog converter (DAC) to generate an analog control signal, and apply the analog control signal to the actuator.

Abstract: A method of and system for handling latency issues encountered in producing real-time entertainment such as games of skill synchronized with live or taped televised events is described herein. There are multiple situations that are dealt with regarding latencies in receiving a television signal with respect to real-time entertainment based on the unfolding games played along with the telecasts. Systemic delays, arbitrarily imposed delays of a broadcast signal and variances in the precise broadcast times of taped television programs have to be equalized so as to provide fair entertainment.

Abstract: A semiconductor structure includes stack structures. Each of the stack structures comprises a first conductive material, a chalcogenide material over the first conductive material, a second conductive material over the chalcogenide material, and a first dielectric material between the chalcogenide material and the first conductive material and between the chalcogenide material and the second conductive material. The semiconductor structure further comprises a second dielectric material on at least sidewalls of the chalcogenide material. The chalcogenide material may be substantially encapsulated by one or more dielectric materials. Related semiconductor structures and related methods are disclosed.

Abstract: An alternation voltage- or current generator comprises a first switch driving output network whose frequency can be tuned. The tunable network comprises a first Inductor that is coupled with a first capacitor. A second inductor and/or at least a second capacitor and/or at least a series circuit of a third inductor and a third capacitor which is coupled via at a second switch to the network. The second switch is controlled by a controlled delay (PWM) which is synchronized by a sign change of current and/or voltage in the network.

Abstract: A precompensation circuit can include: a rising edge interpolator circuit configured to generate a phase shifted rising edge data signal; a falling edge interpolator circuit configured to generate a phase shifted falling edge data signal; a multiplexer circuit coupled with the rising edge interpolator circuit and with the falling edge interpolator circuit to multiplex the phase shifted rising edge data signal and the phase shifted falling edge data signal into an output data signal responsive to a select signal; and a control circuit coupled with the select input of the multiplexer circuit to control production of the output data signal, wherein the control circuit is further coupled with both the rising edge interpolator circuit and the falling edge interpolator circuit to change the select signal to the multiplexer circuit at times determined by both the phase shifted rising edge data signal and the phase shifted falling edge data signal.

Abstract: The present disclosure includes apparatuses and methods for estimating an error rate associated with memory. A number of embodiments include sensing data stored in a memory, performing an error detection operation on the sensed data, determining a quantity of parity violations associated with the error detection operation, and estimating an error rate associated with the memory based on the determined quantity of parity violations.

Abstract: According to one embodiment, a magnetic disc has N (N is an integer of 2 or more) zones divided in a radial direction, and servo patterns different in servo pattern frequency are recorded in the individual zones. The relationship that the zone width of a K-th (K is an integer of 1 or more and N?1 or less) zone from the outer radial side of the magnetic disc is larger than the zone width of the K+1-th zone adjacent to the K-th zone on the inner diameter side applies to all the K-th zones in which K is 1 or more and N?1 or less.

Abstract: Systems and methods are disclosed for head delay calibration and tracking multi-sensor magnetic recording (MSMR) systems. In certain embodiments, an apparatus may comprise a first reader and a second reader configured to simultaneously read from a single track of a data storage medium, the first reader offset from the second reader such that the first reader and the second reader detect a same signal pattern offset in time. The apparatus may further comprise a circuit configured to determine a relative offset between the first reader and the second reader, including setting a fixed delay for a first signal from the first reader, setting a second delay for a second signal from the second reader, and adjusting the second delay to align the second signal to the first signal using a timing loop, with the first signal used as a reference signal.

Abstract: A model identification system includes an analog to digital converter (ADC). The ADC includes a conversion circuit configured to receive a first analog signal and generate a first digital signal including samples having a first rate by sampling the first analog signal at the first rate. The ADC further includes a first digital signal processing (DSP) circuit configured to generate a second digital signal including samples having a second rate less than the first rate based on the second digital signal and a first sampling matrix. The first sampling matrix is a block diagonal matrix including a plurality of diagonal blocks, each diagonal block is a row vector including a plurality of elements.

Abstract: To encourage viewer participation, games, contests and social interactions are able to be synchronized with programming such as television shows or commercials utilizing a second screen such as a cell phone, iPad® or laptop computer. The programming is able to be television programming, Internet programming (e.g. a video displayed on a webpage or mobile device) or any other programming. The gaming is able to be any game such as a game of skill or chance, for example, a scavenger hunt or a treasure hunt.

Abstract: A method of and system for handling latency issues encountered in producing real-time entertainment such as games of skill synchronized with live or taped televised events is described herein. There are multiple situations that are dealt with regarding latencies in receiving a television signal with respect to real-time entertainment based on the unfolding games played along with the telecasts. Systemic delays, arbitrarily imposed delays of a broadcast signal and variances in the precise broadcast times of taped television programs have to be equalized so as to provide fair entertainment.

Abstract: A method of and system for handling latency issues encountered in producing real-time entertainment such as games of skill synchronized with live or taped televised events is described herein. There are multiple situations that are dealt with regarding latencies in receiving a television signal with respect to real-time entertainment based on the unfolding games played along with the telecasts. Systemic delays, arbitrarily imposed delays of a broadcast signal and variances in the precise broadcast times of taped television programs have to be equalized so as to provide fair entertainment.

Abstract: An apparatus determines that phase errors have exceeded a threshold when reading data previously recorded to a heat-assisted recording medium. In response to the phase errors exceeding the threshold, remedial action is taken to prevent loss of data due changes in power applied to heat the heat-assisted recording medium when recording.

Abstract: The embodiments disclose a method and apparatus for automatic gain control. The apparatus comprises a first gain controlled element, a second gain controlled element, a first gain control device, a second gain control device and a first simulator. The first gain controlled element and the second gain controlled element each has a signal input, a gain control input and a signal output. The first gain controlled element and the second gain controlled element are coupled in series and one or more power elements coupled between the first gain controlled element and the second gain controlled element. The signal input of the first gain controlled element constitutes an input of the automatic gain control apparatus. The first gain control device has a pre-detection input which is coupled to the signal input of the first gain controlled element and an output which drives the gain control input of the first gain controlled element.

Abstract: In an illustrative example, a device includes an operational amplifier of an active bandpass filter circuit. The device further includes an adjustable resistance device configured to adjust a center frequency associated with the active bandpass filter circuit. The device further includes an adjustable capacitance device configured to adjust the center frequency and a bandwidth associated with the active bandpass filter circuit.

Abstract: A compression engine may be designed for more efficient error checking of a compressed stream, to include adaptation of a heterogeneous design that includes interleaved hardware and software stages of compression and decompression. An output of a string matcher may be reversed to generate a bit stream, which is then compared with an input stream to the compression engine as a first error check. A final compressed output of the compression engine may be partially decompressed to reverse entropy code encoding of an entropy code encoder. The partially decompressed output may be compared with an output of an entropy code generator to perform a second error check. Finding an error at the first error check greatly reduces the latency of generating a fault or exception, as does performing computing-intensive aspects of the compression and decompression with software instead of specialized hardware.

Abstract: A quantum-state-refresh module of a memory system is configured to detect an error in an entangled qubit state stored therein by performing a redundant measurement of syndrome values corresponding to a quantum stabilizer code, with the redundant measurement being based on a block error-correction code. The quantum-state-refresh module includes a plurality of measurement sub-modules, each configured to measure a respective syndrome value or a respective parity value corresponding to the entangled qubit state. The total number of the measurement sub-modules is smaller than the codeword length of the block error-correction code, and the initial approximation of the punctured syndrome values is replaced in the decoding process by erasure values.

Abstract: A noise analysis apparatus has a plurality of digital filters and a noise analysis unit. The plurality of digital filters have mutually different filtering characteristics and filter a same input signal to output a plurality of output signals, respectively. The noise analysis unit detects presence or absence of a noise in the input signal, based on the plurality of output signals. More specifically, the noise analysis unit detects the presence or absence of the noise in the input signal, based on whether or not values of the plurality of output signals coincide with each other.

Abstract: In one embodiment, a computer-implemented method for simulating a defect signal in a time based servo system includes determining a start position for a spike, determining an end position for the spike, determining a servo channel, determining an amplitude of the spike, initiating an acquire lock process, creating the spike in the determined servo channel from the determined start position to the determined end position, and storing servo data including at least a portion thereof generated during the spike. The spike has the determined amplitude. In another embodiment, a computer program product for generating defect signals in a storage system includes a computer readable storage medium having program instructions embodied therewith, wherein the computer readable storage medium is not a transitory signal per se. The program instructions are executable by a controller to perform the foregoing method.

Abstract: A heat-assisted magnetic recording (HAMR) device includes transducer head comprising a heat source and a writer. The HAMR device further includes a power controller configured to selectively power on and off the heat source independent of current flowing through a write coil of the writer based on a position of the transducer head relative to an adjacent rotating media.

Abstract: A recording head is configured to write and read data sectors to and from a recording medium, such as a heat-assisted recording medium. A read channel is coupled to the recording head. Phase-locked loop (PLL) circuitry of the read channel is configured to detect a change in a phase error at a location of the data sector. The phase error change may be indicative of a mode-hop that occurred while writing the data sector to the medium. The PLL circuitry is configured to determine a phase offset using the phase error. A controller is configured to effect re-reading of the data sector location using the phase offset to recover the data sector location.

Abstract: The present disclosure includes apparatuses and methods for estimating an error rate associated with memory. A number of embodiments include sensing data stored in a memory, performing an error detection operation on the sensed data, determining a quantity of parity violations associated with the error detection operation, and estimating an error rate associated with the memory based on the determined quantity of parity violations.

Abstract: An integrated circuit implements at least part of a phase locked loop (PLL). The integrated circuit includes a sampled analog loop filter for the PLL. The loop filter includes a first input for receiving a signal representative of a phase difference between a reference clock signal and a first clock signal, a first output for providing a frequency control signal for controlling a frequency of an oscillator, a clock input for accepting a loop timing clock signal for controlling timing of operation of the loop filter, and a digital control input for configuring a response of the loop filter according to a plurality of control values. In some examples, the loop filter includes charge storage elements coupled by controllable switches, and control circuitry for transferring charge among the charge storage elements to yield the configured response of the loop filter.

Abstract: Described is an apparatus which comprises: an amplifier; a first set of samplers to sample data output from the amplifier according to a clock signal, the set of samplers to generate an output; and a converter to convert the output of the first set of samplers to 1 -hot encoded data.

Abstract: A slider having a reader and a writer is moved relative to a magnetic bit pattern medium comprising magnetic dots arranged to include a plurality of pre-written servo sectors, data fields defined between servo sectors to which data can be written and erased, and pre-written timing synchronization fields interspersed within the data fields. In some approaches, two different tone patterns are read from one or more of the timing synchronization fields, and fly height of the slider is determined using the two different tone patterns. In other approaches, two odd harmonics are demodulated from a mixed tone pattern read from one or more of the timing synchronization fields, and fly height of the slider is determined using the two odd harmonics.

Abstract: Host device platforms developed based on older ECC (Error Correcting Code) designs may not be equipped to handle the enhanced error correction capabilities in the newer NAND memories. Error correcting memory employing an error threshold representative of the additional capability of the ECC memory allows determining when a fetch has exceeded a safe level of errors to correct. ECC processing compares an error count to the threshold, and if the error count exceeds the threshold of maximum allowable errors, the ECC status module induces an error in the fetched data to alert the host.

Abstract: A method of synchronizing operations between integrated circuits can include transmitting a first clock signal from a first transmitter associated with a first integrated circuit of a first system, to a receiver associated with a second integrated circuit of a second system, receiving a second clock signal from a second transmitter associated with a third integrated circuit of the second system, receiving at the first system a first phase difference determined by the second system, wherein the first phase difference is determined between the first clock signal at the second system and the second clock signal at the second system, determining a second phase difference at the first system, wherein the second phase difference is determined between the first clock signal at the first system and the second clock signal at the first system, and determining a difference between the first phase difference and the second phase difference.

Abstract: A method and a system are provided for speculative periodic synchronization. A phase value representing a measured phase of the second clock signal relative to the first clock signal measured at least one cycle earlier is received. A period value representing a period of the second clock signal relative to the first clock signal measured at least one cycle earlier is also received. A reduced timing margin is determined based on the phase value and the period value. A speculatively synchronized output signal is generated based on the reduced timing margin.

Abstract: A disk drive is disclosed comprising a disk comprising a plurality of servo sectors defining a plurality of servo tracks. The servo tracks form a plurality of servo zones, where a servo data rate of servo sectors in a first servo zone is different than a servo data rate of servo sectors in a second servo zone. A servo control system servos a head over the disk. An estimated servo state of a servo control system is generated, and when the head crosses from a first servo zone to a second servo zone, the estimated servo state is adjusted to compensate for a transient in a circumferential distance between a servo sector in the first servo zone and a servo sector in the second servo zone.

Abstract: A method for radio frequency (RF) pulse synchronization in a super regenerative receiver (SRR), includes receiving an input signal including an asymmetric preamble, and estimating a phase difference between the input signal and a quench signal based on the asymmetric preamble. The method further includes compensating for the phase difference.

Abstract: A hard disk drive is adapted to take the most recent estimated read head positions (the position error signal or PES values) that are obtained during writing and write those values into the data sectors as written PES (WPES) values. The WPES values are available on readback for use as a predictor of the positions in which subsequent data sectors were written and are also available for use in a data recovery procedure should a particular data sector fail to be recovered. In two-dimensional magnetic recording, the difference between the WPES value and the read PES value is a quantity required to rapidly select the best 2D equalizer. The PES values may be encoded prior to being written into the data sectors. The WPES values are appended to the data sectors after the preamble and sync fields, which occur after every servo sector.

Abstract: An out-of-band (OOB) detection circuit includes: a positive input node; a negative input node; a resistive circuit comprising a first resistor coupled between a first supply node and a first node, a variable resistor coupled between the first node and a second node, and a second resistor coupled between the second node and a ground; a first comparator configured to compare a difference between a positive input signal received at the positive input node and a negative input signal received at the negative input node against a positive threshold value, and a second comparator configured to compare the difference between the positive input signal received at the positive input node and the negative input signal received at the negative input node against a negative threshold value.

Abstract: A clock data recovery (CDR) circuit includes a sampling circuit, a synchronization circuit that synchronizes a frequency of an oscillation clock signal from an oscillation circuit with a frequency of input data of a specific pattern which is sampled in the sampling circuit, and synchronizes a phase of the oscillation clock signal with a phase of the sampled input data, and a data pattern recognition circuit that detects whether the input data sampled in the sampling circuit has a specific pattern. The data pattern recognition circuit starts an operation for detecting whether the input data has a specific pattern in response to a frequency lock start instruction. The synchronization circuit starts an operation for synchronizing the frequency on condition that it is determined by the data pattern recognition circuit that the input data has a specific pattern.

Abstract: A transponder circuit for receiving and processing an ASK signal having modulated communication information is provided. The transponder circuit includes a data receiver configured to receive the ASK signal. A reference clock extractor coupled to the data receiver is configured to extract a reference clock signal from the ASK signal. An amplitude determination unit is coupled to the data receiver and the reference clock extractor, and is configured to determine at least one amplitude value of the received ASK signal in at least one clock cycle of the extracted reference clock signal based on the extracted reference block. A processing unit, which is coupled to the amplitude determination unit, processes the amplitude value such that the communication information is retrieved.

Abstract: On-chip at-speed eye measurements of digitized signals in data and timing recovery circuits are disclosed. Eye diagrams and jitter measurements are used to evaluate signal quality and bath-tub Bit Error Rate characteristics in baseband communication systems. This disclosure describes a method and apparatus for digitally sampling a received signal at speed to produce an eye diagram of the received signal. This involves adding a small amount of circuitry to the existing prior art systems that use an interpolator for timing recovery and data recovery. In the present disclosure a temporary offset is applied to the interpolation index of the interpolator to obtain interpolated samples between the baud center and baud edge. The eye diagram can be produced from the received digitized and interpolated signal before equalization, or alternatively from the equalized signal.

Abstract: The disclosure is related to apparatuses and methods for characterizing and compensating for curvature in a write field generated by a data storage device transducer. In some embodiments, the curvature of a write field generated by a data storage device transducer may be characterized. Some embodiments can include a circuit to apply a phase compensation value based on a deterministic phase offset value, which may correspond with the write field curvature characterization.

Abstract: Method and apparatus for detecting unstable read sensors (readers) for data storage systems. In some embodiments, a transducer is supported adjacent a rotating data recording medium having servo data patterns interspersed with calibration test data patterns. A read sensor of the transducer reads the servo and calibration test data patterns while the transducer is maintained at a passive fly height adjacent the medium. A corresponding location on the medium is identified for an error detected during the reading of the servo and calibration test patterns. The servo and calibration test patterns at the location are reread using the read sensor to characterize the read sensor as an unstable reader.

Abstract: Various embodiments provide a recording medium. The recording medium may include a dedicated servo layer for providing servo information. The dedicated servo layer may include a plurality of tracks. A first track may include a first servo signal. A second track may include a second servo signal. The first servo signal and the second servo signal may include a plurality of common transitions. The transitions may be provided at a pre-determined frequency.

Abstract: Various embodiments of the present invention provide systems and methods for low overhead disk wobble compensation. As an example, a method for performing synchronous wobble compensation processing is disclosed. The method includes providing a medium that includes a servo data region and a user data region. The servo data region includes a clock recovery pattern and a location pattern. A detectable pattern is written to the user data region a known number of bit periods from the location pattern. The detectable pattern is read back, and a fractional processing delay is calculated. Based at least on the fractional processing delay and a known number of bit periods from the location pattern to the end of the servo data region, a wobble compensation pattern is written an integral number of bit periods from the location pattern.

Abstract: A method of operating a multi-reader two-dimensional magnetic recording system includes determining a position of a multi-reader head of the multi-reader two-dimensional magnetic recording system, determining an areal density push according to the position of the multi-reader head, and performing an operation to read data from or write data to a magnetic recording medium according to the areal density push.

Abstract: Embodiments are related to systems and methods for data processing, and more particularly to systems and methods for format efficient processing of data fragments.

Abstract: A method for processing an image having a first bit depth includes performing two or more iterations of a bit depth enhancement operation that increases the bit depth of the image to a second bit depth that is higher than the first bit depth. The bit depth enhancement operation includes dividing the image into a plurality of areas, performing an edge detection operation to identify one or more areas from the plurality of areas that do not contain edge features, and applying a blur to the one or more areas from the plurality of areas that do not contain edge features. In a first iteration of the of the bit depth enhancement operation, the plurality of areas includes a first number of areas, and the number of areas included in the plurality of areas decreases with each subsequent iteration of the bit depth enhancement operation.

Abstract: A method is provided, for example, to implement multiplexed communication on an analog bus between a recording channel and a preamplifier in a storage device. A first input of read data circuitry within the recording channel is switchably connected to a first analog line of the analog bus to receive read data transmitted from the preamplifier to the recording channel over the first analog line during a read operation. In addition, a write data output of write data circuitry within the recording channel is switchably connected to the first analog line of the analog bus to transmit write data from the recording channel to the preamplifier over the first analog line during a write operation.

Abstract: An apparatus for storing data includes a storage medium, a head assembly disposed in relation to the storage medium and operable to read and write data on the storage medium, an analog high pass filter operable to filter an output from the head assembly to yield a filtered analog signal, wherein a high pass corner frequency of the analog high pass filter is below a servo data frequency in the data, an analog to digital converter operable to sample the filtered analog signal to yield digital samples, and a digital filter operable to perform pole-zero compensation for the analog high pass filter on the digital samples to yield filtered digital samples, with a zero at the high pass corner frequency of the analog high pass filter, and with a pole at a frequency higher than the high pass corner frequency of the analog high pass filter.

Abstract: A system for reading data from a storage medium. The system includes a reader and a data determination circuit. The reader is configured to receive a first signal from a first position relative to the storage medium and read a second signal from a second position relative to the storage medium. Each of the first signal and the second signal includes a combination of first data stored in a first track and second data stored in a second track. The data determination circuit is configured to determine third data stored at a predetermined position using the combination of the first data stored in the first track and the second data stored in the second track as received in the first signal and the combination of the first data stored in the first track and the second data stored in the second track as received in the second signal.