Abstract: In an illustrative example, a device includes an operational amplifier of an active bandpass filter circuit. The device further includes an adjustable resistance device configured to adjust a center frequency associated with the active bandpass filter circuit. The device further includes an adjustable capacitance device configured to adjust the center frequency and a bandwidth associated with the active bandpass filter circuit.

Abstract: A compression engine may be designed for more efficient error checking of a compressed stream, to include adaptation of a heterogeneous design that includes interleaved hardware and software stages of compression and decompression. An output of a string matcher may be reversed to generate a bit stream, which is then compared with an input stream to the compression engine as a first error check. A final compressed output of the compression engine may be partially decompressed to reverse entropy code encoding of an entropy code encoder. The partially decompressed output may be compared with an output of an entropy code generator to perform a second error check. Finding an error at the first error check greatly reduces the latency of generating a fault or exception, as does performing computing-intensive aspects of the compression and decompression with software instead of specialized hardware.

Abstract: A quantum-state-refresh module of a memory system is configured to detect an error in an entangled qubit state stored therein by performing a redundant measurement of syndrome values corresponding to a quantum stabilizer code, with the redundant measurement being based on a block error-correction code. The quantum-state-refresh module includes a plurality of measurement sub-modules, each configured to measure a respective syndrome value or a respective parity value corresponding to the entangled qubit state. The total number of the measurement sub-modules is smaller than the codeword length of the block error-correction code, and the initial approximation of the punctured syndrome values is replaced in the decoding process by erasure values.

Abstract: A noise analysis apparatus has a plurality of digital filters and a noise analysis unit. The plurality of digital filters have mutually different filtering characteristics and filter a same input signal to output a plurality of output signals, respectively. The noise analysis unit detects presence or absence of a noise in the input signal, based on the plurality of output signals. More specifically, the noise analysis unit detects the presence or absence of the noise in the input signal, based on whether or not values of the plurality of output signals coincide with each other.

Abstract: In one embodiment, a computer-implemented method for simulating a defect signal in a time based servo system includes determining a start position for a spike, determining an end position for the spike, determining a servo channel, determining an amplitude of the spike, initiating an acquire lock process, creating the spike in the determined servo channel from the determined start position to the determined end position, and storing servo data including at least a portion thereof generated during the spike. The spike has the determined amplitude. In another embodiment, a computer program product for generating defect signals in a storage system includes a computer readable storage medium having program instructions embodied therewith, wherein the computer readable storage medium is not a transitory signal per se. The program instructions are executable by a controller to perform the foregoing method.

Abstract: A heat-assisted magnetic recording (HAMR) device includes transducer head comprising a heat source and a writer. The HAMR device further includes a power controller configured to selectively power on and off the heat source independent of current flowing through a write coil of the writer based on a position of the transducer head relative to an adjacent rotating media.

Abstract: A recording head is configured to write and read data sectors to and from a recording medium, such as a heat-assisted recording medium. A read channel is coupled to the recording head. Phase-locked loop (PLL) circuitry of the read channel is configured to detect a change in a phase error at a location of the data sector. The phase error change may be indicative of a mode-hop that occurred while writing the data sector to the medium. The PLL circuitry is configured to determine a phase offset using the phase error. A controller is configured to effect re-reading of the data sector location using the phase offset to recover the data sector location.

Abstract: The present disclosure includes apparatuses and methods for estimating an error rate associated with memory. A number of embodiments include sensing data stored in a memory, performing an error detection operation on the sensed data, determining a quantity of parity violations associated with the error detection operation, and estimating an error rate associated with the memory based on the determined quantity of parity violations.

Abstract: Described is an apparatus which comprises: an amplifier; a first set of samplers to sample data output from the amplifier according to a clock signal, the set of samplers to generate an output; and a converter to convert the output of the first set of samplers to 1 -hot encoded data.

Abstract: An integrated circuit implements at least part of a phase locked loop (PLL). The integrated circuit includes a sampled analog loop filter for the PLL. The loop filter includes a first input for receiving a signal representative of a phase difference between a reference clock signal and a first clock signal, a first output for providing a frequency control signal for controlling a frequency of an oscillator, a clock input for accepting a loop timing clock signal for controlling timing of operation of the loop filter, and a digital control input for configuring a response of the loop filter according to a plurality of control values. In some examples, the loop filter includes charge storage elements coupled by controllable switches, and control circuitry for transferring charge among the charge storage elements to yield the configured response of the loop filter.

Abstract: A slider having a reader and a writer is moved relative to a magnetic bit pattern medium comprising magnetic dots arranged to include a plurality of pre-written servo sectors, data fields defined between servo sectors to which data can be written and erased, and pre-written timing synchronization fields interspersed within the data fields. In some approaches, two different tone patterns are read from one or more of the timing synchronization fields, and fly height of the slider is determined using the two different tone patterns. In other approaches, two odd harmonics are demodulated from a mixed tone pattern read from one or more of the timing synchronization fields, and fly height of the slider is determined using the two odd harmonics.

Abstract: Host device platforms developed based on older ECC (Error Correcting Code) designs may not be equipped to handle the enhanced error correction capabilities in the newer NAND memories. Error correcting memory employing an error threshold representative of the additional capability of the ECC memory allows determining when a fetch has exceeded a safe level of errors to correct. ECC processing compares an error count to the threshold, and if the error count exceeds the threshold of maximum allowable errors, the ECC status module induces an error in the fetched data to alert the host.

Abstract: A method of synchronizing operations between integrated circuits can include transmitting a first clock signal from a first transmitter associated with a first integrated circuit of a first system, to a receiver associated with a second integrated circuit of a second system, receiving a second clock signal from a second transmitter associated with a third integrated circuit of the second system, receiving at the first system a first phase difference determined by the second system, wherein the first phase difference is determined between the first clock signal at the second system and the second clock signal at the second system, determining a second phase difference at the first system, wherein the second phase difference is determined between the first clock signal at the first system and the second clock signal at the first system, and determining a difference between the first phase difference and the second phase difference.

Abstract: A method and a system are provided for speculative periodic synchronization. A phase value representing a measured phase of the second clock signal relative to the first clock signal measured at least one cycle earlier is received. A period value representing a period of the second clock signal relative to the first clock signal measured at least one cycle earlier is also received. A reduced timing margin is determined based on the phase value and the period value. A speculatively synchronized output signal is generated based on the reduced timing margin.

Abstract: A disk drive is disclosed comprising a disk comprising a plurality of servo sectors defining a plurality of servo tracks. The servo tracks form a plurality of servo zones, where a servo data rate of servo sectors in a first servo zone is different than a servo data rate of servo sectors in a second servo zone. A servo control system servos a head over the disk. An estimated servo state of a servo control system is generated, and when the head crosses from a first servo zone to a second servo zone, the estimated servo state is adjusted to compensate for a transient in a circumferential distance between a servo sector in the first servo zone and a servo sector in the second servo zone.

Abstract: A method for radio frequency (RF) pulse synchronization in a super regenerative receiver (SRR), includes receiving an input signal including an asymmetric preamble, and estimating a phase difference between the input signal and a quench signal based on the asymmetric preamble. The method further includes compensating for the phase difference.

Abstract: A hard disk drive is adapted to take the most recent estimated read head positions (the position error signal or PES values) that are obtained during writing and write those values into the data sectors as written PES (WPES) values. The WPES values are available on readback for use as a predictor of the positions in which subsequent data sectors were written and are also available for use in a data recovery procedure should a particular data sector fail to be recovered. In two-dimensional magnetic recording, the difference between the WPES value and the read PES value is a quantity required to rapidly select the best 2D equalizer. The PES values may be encoded prior to being written into the data sectors. The WPES values are appended to the data sectors after the preamble and sync fields, which occur after every servo sector.

Abstract: An out-of-band (OOB) detection circuit includes: a positive input node; a negative input node; a resistive circuit comprising a first resistor coupled between a first supply node and a first node, a variable resistor coupled between the first node and a second node, and a second resistor coupled between the second node and a ground; a first comparator configured to compare a difference between a positive input signal received at the positive input node and a negative input signal received at the negative input node against a positive threshold value, and a second comparator configured to compare the difference between the positive input signal received at the positive input node and the negative input signal received at the negative input node against a negative threshold value.

Abstract: A clock data recovery (CDR) circuit includes a sampling circuit, a synchronization circuit that synchronizes a frequency of an oscillation clock signal from an oscillation circuit with a frequency of input data of a specific pattern which is sampled in the sampling circuit, and synchronizes a phase of the oscillation clock signal with a phase of the sampled input data, and a data pattern recognition circuit that detects whether the input data sampled in the sampling circuit has a specific pattern. The data pattern recognition circuit starts an operation for detecting whether the input data has a specific pattern in response to a frequency lock start instruction. The synchronization circuit starts an operation for synchronizing the frequency on condition that it is determined by the data pattern recognition circuit that the input data has a specific pattern.

Abstract: A transponder circuit for receiving and processing an ASK signal having modulated communication information is provided. The transponder circuit includes a data receiver configured to receive the ASK signal. A reference clock extractor coupled to the data receiver is configured to extract a reference clock signal from the ASK signal. An amplitude determination unit is coupled to the data receiver and the reference clock extractor, and is configured to determine at least one amplitude value of the received ASK signal in at least one clock cycle of the extracted reference clock signal based on the extracted reference block. A processing unit, which is coupled to the amplitude determination unit, processes the amplitude value such that the communication information is retrieved.

Abstract: On-chip at-speed eye measurements of digitized signals in data and timing recovery circuits are disclosed. Eye diagrams and jitter measurements are used to evaluate signal quality and bath-tub Bit Error Rate characteristics in baseband communication systems. This disclosure describes a method and apparatus for digitally sampling a received signal at speed to produce an eye diagram of the received signal. This involves adding a small amount of circuitry to the existing prior art systems that use an interpolator for timing recovery and data recovery. In the present disclosure a temporary offset is applied to the interpolation index of the interpolator to obtain interpolated samples between the baud center and baud edge. The eye diagram can be produced from the received digitized and interpolated signal before equalization, or alternatively from the equalized signal.

Abstract: The disclosure is related to apparatuses and methods for characterizing and compensating for curvature in a write field generated by a data storage device transducer. In some embodiments, the curvature of a write field generated by a data storage device transducer may be characterized. Some embodiments can include a circuit to apply a phase compensation value based on a deterministic phase offset value, which may correspond with the write field curvature characterization.

Abstract: Method and apparatus for detecting unstable read sensors (readers) for data storage systems. In some embodiments, a transducer is supported adjacent a rotating data recording medium having servo data patterns interspersed with calibration test data patterns. A read sensor of the transducer reads the servo and calibration test data patterns while the transducer is maintained at a passive fly height adjacent the medium. A corresponding location on the medium is identified for an error detected during the reading of the servo and calibration test patterns. The servo and calibration test patterns at the location are reread using the read sensor to characterize the read sensor as an unstable reader.

Abstract: Various embodiments provide a recording medium. The recording medium may include a dedicated servo layer for providing servo information. The dedicated servo layer may include a plurality of tracks. A first track may include a first servo signal. A second track may include a second servo signal. The first servo signal and the second servo signal may include a plurality of common transitions. The transitions may be provided at a pre-determined frequency.

Abstract: A method of operating a multi-reader two-dimensional magnetic recording system includes determining a position of a multi-reader head of the multi-reader two-dimensional magnetic recording system, determining an areal density push according to the position of the multi-reader head, and performing an operation to read data from or write data to a magnetic recording medium according to the areal density push.

Abstract: Various embodiments of the present invention provide systems and methods for low overhead disk wobble compensation. As an example, a method for performing synchronous wobble compensation processing is disclosed. The method includes providing a medium that includes a servo data region and a user data region. The servo data region includes a clock recovery pattern and a location pattern. A detectable pattern is written to the user data region a known number of bit periods from the location pattern. The detectable pattern is read back, and a fractional processing delay is calculated. Based at least on the fractional processing delay and a known number of bit periods from the location pattern to the end of the servo data region, a wobble compensation pattern is written an integral number of bit periods from the location pattern.

Abstract: A method for processing an image having a first bit depth includes performing two or more iterations of a bit depth enhancement operation that increases the bit depth of the image to a second bit depth that is higher than the first bit depth. The bit depth enhancement operation includes dividing the image into a plurality of areas, performing an edge detection operation to identify one or more areas from the plurality of areas that do not contain edge features, and applying a blur to the one or more areas from the plurality of areas that do not contain edge features. In a first iteration of the of the bit depth enhancement operation, the plurality of areas includes a first number of areas, and the number of areas included in the plurality of areas decreases with each subsequent iteration of the bit depth enhancement operation.

Abstract: Embodiments are related to systems and methods for data processing, and more particularly to systems and methods for format efficient processing of data fragments.

Abstract: A method is provided, for example, to implement multiplexed communication on an analog bus between a recording channel and a preamplifier in a storage device. A first input of read data circuitry within the recording channel is switchably connected to a first analog line of the analog bus to receive read data transmitted from the preamplifier to the recording channel over the first analog line during a read operation. In addition, a write data output of write data circuitry within the recording channel is switchably connected to the first analog line of the analog bus to transmit write data from the recording channel to the preamplifier over the first analog line during a write operation.

Abstract: An apparatus for storing data includes a storage medium, a head assembly disposed in relation to the storage medium and operable to read and write data on the storage medium, an analog high pass filter operable to filter an output from the head assembly to yield a filtered analog signal, wherein a high pass corner frequency of the analog high pass filter is below a servo data frequency in the data, an analog to digital converter operable to sample the filtered analog signal to yield digital samples, and a digital filter operable to perform pole-zero compensation for the analog high pass filter on the digital samples to yield filtered digital samples, with a zero at the high pass corner frequency of the analog high pass filter, and with a pole at a frequency higher than the high pass corner frequency of the analog high pass filter.

Abstract: A system for reading data from a storage medium. The system includes a reader and a data determination circuit. The reader is configured to receive a first signal from a first position relative to the storage medium and read a second signal from a second position relative to the storage medium. Each of the first signal and the second signal includes a combination of first data stored in a first track and second data stored in a second track. The data determination circuit is configured to determine third data stored at a predetermined position using the combination of the first data stored in the first track and the second data stored in the second track as received in the first signal and the combination of the first data stored in the first track and the second data stored in the second track as received in the second signal.

Abstract: A method for protecting data in a memory is disclosed. The method generally includes steps (A) to (D). Step (A) converts a logical address of one of a plurality of logical units to a physical address of a corresponding one of a plurality of physical units. Each physical unit is configured to store (i) data from a corresponding one of the logical units, (ii) respective error correction information and (iii) respective verification information. Step (B) writes a particular one of the physical units to the memory. Step (C) reads a portion of the particular physical unit from the memory. The portion includes the respective verification information. The respective verification information includes an indication of the logical address. Step (D) verifies the writing according to the respective verification information in the portion.

Abstract: Systems, methods, and other embodiments associated with unified control of timing recovery and packet processing are described. According to one embodiment, a method for performing unified control of timing recovery and packet processing is provided. The method includes sampling a received signal according to an ADC timing signal to produce a sequence of samples. The received signal corresponds to a packet and was transmitted according to a transmit timing signal. The method includes determining a phase offset between the ADC timing signal and the transmit timing signal and identifying, based, at least in part, on the phase offset, a data portion of the sequence of samples that contains data encoded in the received signal. A re-generated sample sequence that adjusts the data portion based on the phase offset is calculated.

Abstract: According to one embodiment, there is provided a magnetic disk device including a magnetic disk, a storage unit, and a control unit. The magnetic disk includes a recording region. The storage unit is configured to store a value according to number of accesses to each of a plurality of regions obtained by dividing of the recording region of the magnetic disk in association with each of the plurality of regions. The control unit is configured to count a value according to the number of accesses to each of a plurality of regions in a count step unit that is a value determined according to an elapsed time from occurrence of a specific situation and is a value counted per unit access, and to update the value stored in the storage unit.

Abstract: A method for checking the operability of a digital signal processing unit of a position sensor, wherein the digital signal processing unit executes an instruction queue of N instructions one after another in sequences, wherein an additional number of x instructions is executed by the digital signal processing unit during each sequence, wherein the additional instructions are provided in a unit different from the memory, and that the results of the additional instructions are stored. The results of the additional instructions are read by a microcomputer. The results of the additional instructions are compared by the microcomputer with the expected results achieved by execution of identical additional instructions by the microcomputer or with expected results stored in the microcomputer. This includes a position encoder comprising a digital signal processing unit for calculating position information.

Abstract: An apparatus for calibrating a noise predictive filter includes a noise-predictive filter operable to filter digital data samples to yield filtered data samples, a calibration circuit operable to calculate tap coefficients for the noise-predictive filter based at least in part on the digital data samples, and a gating circuit operable to select a portion of the digital data samples for use by the calibration circuit in calculating the tap coefficients.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for detecting patterns in a data stream.

Abstract: An asynchronous bridge includes a transmission unit and a receiving unit. The transmission unit receives a write valid signal and input data from a master circuit, outputs write addresses increment under control of the write valid signal, sequentially stores the input data in memory cells, as directed by write addresses, and then sequentially outputs the stored input data, as directed by read addresses. The receiving unit receives a read ready signal from a slave circuit, determines whether memory cells are valid, based on the write addresses and the read addresses, and then outputs a read valid signal and the input data, based on the determination.

Abstract: An integrated circuit has voltage generating circuitry for generating an on-chip voltage from a supply voltage in response to clock pulses. Clock control circuitry controls transmission of the clock pulses to the voltage generating circuitry. The clock control circuitry receives a reference voltage and a digital offset value comprising a binary numeric value identifying an offset. The clock control circuitry suppresses transmission of the clock pulses if the on-chip voltage is greater than the sum of the reference voltage and the offset identified by the digital offset value, to reduce power consumption. The offset can be tuned digitally to vary the average level of the on-chip voltage. A similar digital tuning mechanism may be used in a clocked comparator to compare a first voltage with a digitally tunable threshold voltage.

Abstract: Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for processing servo data using two or more sensing heads.

Abstract: A data recovery unit includes a phase locked loop configured to receive data samples and generate an output; a first sample selector coupled to the phase locked loop; and an eye scanner coupled to the phase locked loop. The first sample selector is configured to receive the data samples and the output of the phase locked loop. The eye scanner comprises a second sample selector coupled to the phase locked loop via a first horizontal shift module.

Abstract: A disk drive is disclosed comprising a disk having a plurality of tracks, a head, and a voice coil motor (VCM) and a microactuator for actuating the head over the disk in response to a feed-forward compensation value. A sinusoidal disturbance is applied to the microactuator, and the resulting feed-forward compensation value is processed to characterize the microactuator.

Abstract: A method and system for detecting an end of a preamble without interpolation. The method includes receiving information from a zero phase start module, the information including a target phase constraint, a polyant, and a zero phase start phase. The method also includes selecting two samples per preamble cycle of short filter outputs and long filter outputs based on the target phase constraint, the polyant, and the zero phase start phase. The method further includes decimating the short filter outputs and the long filter outputs such that the selected two samples for each of the filters per preamble cycle are output upon decimation. The method additionally includes performing a sign comparison on the corresponding short filter and long filter outputs after decimation, wherein a sign mismatch of the corresponding short filter and long filter outputs indicates an end of a preamble.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing loop feedback in a data processing system.

Abstract: A data storage device is disclosed comprising a head actuated over a disk and a vibration detector configured to generate a vibration signal in response to a vibration affecting the data storage device. A timing loop is configured to generate a disk-locked clock substantially synchronized to a rotation frequency of the disk. An adaptation control signal is generated based on the vibration signal and an error signal of the timing loop. An adaptive filter is adapted based on the adaptation control signal, wherein the adaptive filter filters the vibration signal to generate feed-forward compensation values. The feed-forward compensation values are applied to the timing loop to compensate for the vibration.

Abstract: Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for determining a down track distance between two or more read heads on a read/write head assembly.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for synchronizing operations in a data storage system.

Abstract: A disk drive is disclosed comprising a disk comprising at least one spiral track, a head, and an actuator operable to actuate the head over the disk. A slope of the spiral track is measured at a plurality of radial locations across the disk, and a spiral track error at each radial location is generated based on a difference between the measured slope and a target slope. The head is actuated over the disk based on the spiral track and the spiral track error.

Abstract: According to one embodiment, there is provided a controller including a write control unit. The write control unit is configured to control to, when writing data onto data regions of a magnetic disk, write sync marks to signify beginnings of the data regions such that the sync marks are periodically made different from each other for each neighboring tracks.

Abstract: Disclosed herein are methods and apparatuses that provide for variable data density on a disc data storage medium, where the variable data density may have a circumferential definition and a radial definition. In some examples, devices and methods may include measuring a read or write performance attribute on a disc data storage medium and selectively setting a data density rate that may vary in a circumferential direction for the disc data storage medium based on the read or write performance attribute. In other examples, apparatuses can include a data storage device having a disc data storage medium and a controller configured to measure a performance attribute of the disc data storage medium and to selectively set different Bits Per Inch (BPI) for data storage within different areas of the disc.