Non-self-supporting Electrodes Patents (Class 361/304)
  • Patent number: 10685785
    Abstract: Some embodiments include a capacitive chip having a plurality of capacitive units. The individual capacitive units include alternating electrode layers and dielectric layers in a capacitor stack. The capacitor stack extends across an undulating topography. The undulating topography has peaks and valleys with the peaks being elevationally offset relative to the valleys by a distance within a range of from about 30 microns to about 100 microns. The capacitor stack includes at least about 10 total layers. Some embodiments include apparatuses and multi-chip modules having capacitor chips.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: June 16, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Fred D. Fishburn
  • Patent number: 10483043
    Abstract: Some embodiments include a capacitive chip having a plurality of capacitive units. The individual capacitive units include alternating electrode layers and dielectric layers in a capacitor stack. The capacitor stack extends across an undulating topography. The undulating topography has peaks and valleys with the peaks being elevationally offset relative to the valleys by a distance within a range of from about 30 microns to about 100 microns. The capacitor stack includes at least about 10 total layers. Some embodiments include apparatuses and multi-chip modules having capacitor chips.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: November 19, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Fred D. Fishburn
  • Patent number: 10418182
    Abstract: Some embodiments include a capacitive chip having a plurality of capacitive units. The individual capacitive units include alternating electrode layers and dielectric layers in a capacitor stack. The capacitor stack extends across an undulating topography. The undulating topography has peaks and valleys with the peaks being elevationally offset relative to the valleys by a distance within a range of from about 30 microns to about 100 microns. The capacitor stack includes at least about 10 total layers. Some embodiments include apparatuses and multi-chip modules having capacitor chips.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: September 17, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Fred D. Fishburn
  • Patent number: 10373767
    Abstract: The present invention is a multi-layer modular capacitor that can be adapted to be electrically coupled to other multi-layer modular capacitors and formed into a structural piece that is electrically coupled to an electrical device requiring a power supply. One aspect of the invention includes a method of forming the multi-modular capacitor.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: August 6, 2019
    Assignee: VACTRONIX SCIENTIFIC, LLC
    Inventors: Christian Gaston Palmaz, Julio C. Palmaz
  • Patent number: 10236127
    Abstract: Some embodiments include a capacitive chip having a plurality of capacitive units. The individual capacitive units include alternating electrode layers and dielectric layers in a capacitor stack. The capacitor stack extends across an undulating topography. The undulating topography has peaks and valleys with the peaks being elevationally offset relative to the valleys by a distance within a range of from about 30 microns to about 100 microns. The capacitor stack includes at least about 10 total layers. Some embodiments include apparatuses and multi-chip modules having capacitor chips.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: March 19, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Fred D. Fishburn
  • Patent number: 10200007
    Abstract: A filter chip includes a substrate, a plurality of external terminals formed on the substrate for external connection, and a plurality of passive element forming regions provided in the regions between the plurality of external terminals in plan view when viewed along a direction normal to the surface of the substrate, the plurality of passive element forming regions including at least a resistor forming region where a resistor is formed. The resistor forming region includes a resistive conductive film formed on the substrate with one end and the other end thereof electrically connected to different ones of the external terminals, and a fuse portion integrally formed with the resistive conductive film. The fuse portion is cuttably provided to electrically connect a part of the resistive conductive film to the external terminals, or to electrically separate a part of the resistive conductive film from the external terminals.
    Type: Grant
    Filed: July 16, 2016
    Date of Patent: February 5, 2019
    Assignee: ROHM CO., LTD.
    Inventors: Keisuke Fukae, Yasuhiro Kondo, Katsuya Matsuura, Hiroyuki Okada, Junya Yamagami
  • Patent number: 10126899
    Abstract: A detection device includes a substrate; a plurality of first conductive thin wires provided in a plane parallel to the substrate and extending in a first direction; a plurality of second conductive thin wires provided in the same layer as that of the first conductive thin wires and extending in a second direction forming an angle with the first direction; first groups that are disposed in first strip-like regions respectively having a first width, each of the first groups including at least two of the first conductive thin wires displaced from one another in the second direction; and second groups that are disposed in second strip-like regions respectively having a second width, each of the second groups including at least two of the second conductive thin wires displaced from one another in the first direction.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: November 13, 2018
    Assignee: Japan Display Inc.
    Inventors: Koji Ishizaki, Hayato Kurasawa
  • Patent number: 9437367
    Abstract: A winding-type solid electrolytic capacitor package structure without using any lead frame includes a winding capacitor and a package body. The winding capacitor has a winding body enclosed by the package body, a positive conductive lead pin extended from a first lateral side of the winding body, and a negative conductive lead pin extended from a second lateral side of the winding body. The positive conductive lead pin has a first embedded portion enclosed by the package body and a first exposed portion exposed outside the package body and extended along the first lateral surface and the bottom surface of the package body. The negative conductive lead pin has a second embedded portion enclosed by the package body and a second exposed portion exposed outside the package body and extended along the second lateral surface and the bottom surface of the package body.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: September 6, 2016
    Assignee: Apaq Technology Co., Ltd.
    Inventors: Ming-Tsung Chen, Ching-Feng Lin
  • Patent number: 9431174
    Abstract: An element body has a substantially rectangular parallelepiped shape whose length in a longitudinal direction and length in a width direction are larger than a length in a height direction. The element body has first and second principal faces opposed to each other in the height direction, first and second side faces opposed to each other in the width direction, and third and fourth side faces opposed to each other in the longitudinal direction. A plurality of internal electrodes are alternately arranged in the element body so as to be opposed to each other in the height direction. Each internal electrode has a main electrode portion and a leading portion. Each of a plurality of terminal electrodes has a first electrode portion arranged on the first principal face, and a second electrode portion arranged on the first side face and connected to the leading portion of each corresponding internal electrode.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: August 30, 2016
    Assignee: TDK CORPORATION
    Inventor: Takeshi Onuma
  • Patent number: 9418791
    Abstract: A folded stack, segmented capacitor having a continuous capacitor base element which is folded two or more times, in one or more first stack folds and one or more second stack folds, to form three or more stack layers. Each of the stack layers has a primary electrode, which may be a continuous metallic film, and a segmented secondary electrode comprised of a plurality of secondary electrode elements electrically connected to a conductor element by a fuse element. The primary electrode is separated from the segmented secondary electrode and the plurality of secondary electrode elements by a continuous primary dielectric element. The secondary electrode elements are separated from the conductor element by a conductor insulation layer. The fuse elements pass through the conductor insulation layer from the secondary electrode elements to the conductor element.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: August 16, 2016
    Assignee: Black Night Enterprises, Inc.
    Inventor: Neldon P. Johnson
  • Patent number: 9208931
    Abstract: A composition of voltage switchable dielectric (VSD) material that comprises a concentration of core shelled particles that individually comprise a conductor core and a conductor shell, so as to form a conductor-on-conductor core shell particle constituent for the VSD material.
    Type: Grant
    Filed: December 15, 2009
    Date of Patent: December 8, 2015
    Assignee: Littelfuse, Inc.
    Inventors: Lex Kosowsky, Robert Fleming, Junjun Wu, Pragnya Saraf, Thangamani Ranganathan
  • Patent number: 9153380
    Abstract: A ceramic short circuit resistant capacitor that is bendable and/or shapeable to provide a multiple layer capacitor that is extremely compact and amenable to desirable geometries. The capacitor that exhibits a benign failure mode in which a multitude of discrete failure events result in a gradual loss of capacitance. Each event is a localized event in which localized heating causes an adjacent portion of one or both of the electrodes to vaporize, physically cleaning away electrode material from the failure site. A first metal electrode, a second metal electrode, and a ceramic dielectric layer between the electrodes are thin enough to be formed in a serpentine-arrangement with gaps between the first electrode and the second electrode that allow venting of vaporized electrode material in the event of a benign failure.
    Type: Grant
    Filed: January 29, 2013
    Date of Patent: October 6, 2015
    Assignee: Delphi Technologies, Inc.
    Inventors: Ralph S. Taylor, John D. Myers, William J. Baney
  • Patent number: 9153383
    Abstract: A winding-type solid electrolytic capacitor package structure without using any lead frame includes a winding capacitor and a package body. The winding capacitor has a winding body enclosed by the package body, a positive conductive lead pin extended from a first lateral side of the winding body, and a negative conductive lead pin extended from a second lateral side of the winding body. The positive conductive lead pin has a first embedded portion enclosed by the package body and a first exposed portion exposed outside the package body and extended along the first lateral surface and the bottom surface of the package body. The negative conductive lead pin has a second embedded portion enclosed by the package body and a second exposed portion exposed outside the package body and extended along the second lateral surface and the bottom surface of the package body.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: October 6, 2015
    Assignee: Apaq Technology Co., Ltd.
    Inventors: Ming-Tsung Chen, Ching-Feng Lin
  • Patent number: 9147528
    Abstract: A winding-type solid electrolytic capacitor package structure includes a winding capacitor unit, a package body and a conductive unit. The winding capacitor has a winding body enclosed by the package body, a positive conductive lead pin having a cutting surface, and a negative conductive lead pin having a grinding surface. The conductive unit includes a positive conductive terminal electrically connected to the positive conductive lead pin and a negative conductive terminal electrically connected to the negative conductive lead pin. The positive conductive terminal has a first embedded portion enclosed by the package body and a first exposed portion exposed outside the package body. The negative conductive terminal has a second embedded portion enclosed by the package body and a second exposed portion exposed outside the package body. The first and the second exposed portions are extended along the outer surface of the package body.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: September 29, 2015
    Assignee: Apaq Technology Co., Ltd.
    Inventors: Ming-Tsung Chen, Ching-Feng Lin
  • Publication number: 20150138691
    Abstract: A metallized film capacitor includes: a first dielectric film; a first metal deposition electrode provided to a first surface of the first dielectric film; a second dielectric film; and a second metal deposition electrode that is provided to a first surface of the second dielectric film and that faces the first dielectric film. The metallized film capacitor further includes: a low resistance provided above at least one of a first end of the first metal deposition electrode and a first end of the second metal deposition electrode; and a first film that covers at least a portion of the low resistance and that comprises mainly aluminum oxide.
    Type: Application
    Filed: May 23, 2013
    Publication date: May 21, 2015
    Inventors: Hiroki Takeoka, Kazuhiro Nakatsubo, Hiroshi Kubota
  • Publication number: 20150109718
    Abstract: A multilayer ceramic electronic component may include a ceramic body including a dielectric layer and having first and second main surfaces, first and second side surfaces, and first and second end surfaces, a length of the ceramic body being 1300 ?m or less; a first external electrode; a second external electrode; a third external electrode; a first internal electrode connected to the first and second external electrodes; and a second internal electrode connected to the third external electrode. When a thickness of the first to third external electrodes formed on the first and second main surfaces and the first and second side surfaces is defined as to and an interval between adjacent external electrodes among the first to third external electrodes is defined as G, 5?G/te is satisfied.
    Type: Application
    Filed: September 2, 2014
    Publication date: April 23, 2015
    Inventor: Young Don CHOI
  • Patent number: 8982532
    Abstract: A system and method for sealing a capacitor bottom in a filtered feedthrough. The feedthrough comprises a ferrule, a capacitor, at least one terminal pin and a support structure. The support structure includes at least one projection that extends into an aperture of the capacitor. The projection includes an opening through which the at least one terminal pin extends such that, in an assembled state, the terminal pin extends through the opening of the projection and the aperture of the capacitor.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: March 17, 2015
    Assignee: Medtronic, Inc.
    Inventor: Rajesh V. Iyer
  • Patent number: 8971014
    Abstract: A capacitor structure includes first and second sets of electrodes and a plurality of line plugs. The first set of electrodes has a first electrode and a second electrode formed in a first metallization layer among a plurality of metallization layers, wherein the first electrode and the second electrode are separated by an insulation material. The second set of electrodes has a third electrode and a fourth electrode formed in a second metallization layer among the plurality of metallization layers, wherein the third electrode and the fourth electrode are separated by the insulation material. The line plugs connect the second set of electrodes to the first set of electrodes.
    Type: Grant
    Filed: January 5, 2011
    Date of Patent: March 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chun Hua, Chung-Long Chang, Chun-Hung Chen, Chih-Ping Chao, Jye-Yen Cheng, Hua-Chou Tseng
  • Patent number: 8885322
    Abstract: A capacitor includes a pair of electrodes and a metalized dielectric layer disposed between the pair of electrodes, in which the metalized dielectric layer has a plurality of metal aggregates distributed within a dielectric material. The distribution is such that a volume fraction of metal in the metalized dielectric layer is at least about 30%. Meanwhile, the plurality of metal aggregates are separated from one another by the dielectric material. A method for forming a metal-dielectric composite may include coating a plurality of dielectric particles with a metal to form a plurality of metal-coated dielectric particles and sintering the plurality of metal-coated dielectric particles at a temperature of at least about 750° C. to about 950° C. to transform the metal coatings into discrete, separated metal aggregates.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: November 11, 2014
    Assignee: Apricot Materials Technologies, LLC
    Inventor: Liang Chai
  • Patent number: 8885320
    Abstract: Provided is a laminated ceramic electronic component which has excellent mechanical characteristics, internal electrode corrosion resistance, high degree of freedom in ceramic material design, low cost, low defective rate, and various properties. The laminated ceramic electronic component includes: a laminate which has a plurality of laminated ceramic layers and Al/Mn alloy internal electrodes at a plurality of specific interfaces between the ceramic layers and an external electrode formed on the outer surface of the laminate, wherein the Al/Mn ratio of the Al/Mn alloy is 80/20 or more.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: November 11, 2014
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Shoichiro Suzuki, Koichi Banno, Masanori Nakamura, Masahiro Otsuka, Taisuke Kanzaki, Akihiro Shiota
  • Patent number: 8861178
    Abstract: A film capacitor element including a base dielectric film layer 12, a vapor-deposition metal film layer 14 formed on the base dielectric film layer 12 and consisting of a first film portion 20 and a second film portion 22 that are spaced apart from each other by a margin portion 18, and a dielectric covering film layer 16 which is formed integrally on the second film portion 22 by vapor-deposition polymerization or coating and which has a covering portion 30 which fills the margin portion 18 and covers an entire area of an end face of the second film portion 22 on the side of the margin portion 18. The first film portion 20 including a non-covered portion 34 which is not covered by the dielectric covering film layer 16.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: October 14, 2014
    Assignee: Kojima Press Industry Co., Ltd.
    Inventors: Akito Terashima, Munetaka Hayakawa, Kaoru Ito
  • Publication number: 20140226259
    Abstract: With respect to the construction and manufacture of well known prior art metallized polymer film capacitors, a technique is described to mitigate the effects of cracks that may develop in the arc sprayed metal connections to the capacitor electrodes when the capacitor diameter becomes large.
    Type: Application
    Filed: February 13, 2013
    Publication date: August 14, 2014
    Applicant: SBE, INC.
    Inventors: Terry Hosking, Samantha Ryan
  • Publication number: 20140092523
    Abstract: An orthogonal finger capacitor includes a layer having an anode bone frame adjacent a cathode bone frame, the anode bone frame having a first portion extending along an axis and a second portion extending perpendicular to the axis. A set of anode fingers extends from the first portion. A set of cathode fingers extends from the cathode bone frame, interdigitated with the set of anode fingers. An overlaying layer has another anode bone frame having a first portion parallel to the axis and a perpendicular second portion. A via couples the overlaying anode bone frame to the underlying anode bone frame. The via is located where the first portion of the overlaying anode bone frame overlaps the second portion of the underlying anode bone frame or, optionally, where the second portion of the overlying anode bone frame overlaps the first portion of the underlying anode bone frame.
    Type: Application
    Filed: March 13, 2013
    Publication date: April 3, 2014
    Applicant: QUALCOMM Incorporated
    Inventors: John J. Zhu, PR Chidambaram, Lixin Ge, Bin Yang, Jihong Choi
  • Patent number: 8649157
    Abstract: An integrated capacitive device includes an electrically conducting comb, at least some of whose teeth form first electrodes of capacitors, and electrically conducting fingers extending between the teeth of the comb so as to form second electrodes of the capacitors. The device includes a first finger-teeth set having a single reference finger forming a reference capacitor having a reference capacitive value, at least one second finger-teeth set including several fingers, the reference finger and the number of fingers of the second finger-teeth set or sets forming a geometric series with ratio two. At least one additional set includes a single additional finger forming, with at least one tooth of the comb, an additional capacitor having an additional capacitive value substantially equal to half the reference capacitive value.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: February 11, 2014
    Assignee: STMicroelectronics SA
    Inventors: Stephane Letual, Sarah Verhaeren
  • Patent number: 8629488
    Abstract: An energy storage device such as a metal-insulator-metal capacitor and a method for manufacturing the energy storage device. The metal-insulator-metal capacitor includes an insulating material positioned between a bottom electrode or bottom plate and a top electrode or top plate. The surface area of the bottom electrode is greater than the surface area of the insulating material and the surface area of the insulating material is greater than the surface area of the top electrode. The top electrode and the insulating layer have edges that are laterally within and spaced apart from edges of the bottom electrode. A protective layer covers the top electrode, the edges of the top electrode, and the portions of the insulating layer that are uncovered by the top electrode. The protective layer serves as an etch mask during the formation of the bottom electrode.
    Type: Grant
    Filed: April 23, 2008
    Date of Patent: January 14, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Sallie Hose, Derryl Allman, Peter A. Burke, Ponce Saopraseuth
  • Publication number: 20140009865
    Abstract: A metallized film capacitor includes a dielectric film and two metal vapor-deposition electrodes facing each other across the dielectric film. At least one of the metal vapor-deposition electrodes is made of substantially only aluminum and magnesium. This metallized film capacitor has superior leak current characteristics and moisture resistant performances, and can be used for forming a case mold type capacitor with a small size.
    Type: Application
    Filed: September 10, 2013
    Publication date: January 9, 2014
    Applicant: Panasonic Corporation
    Inventors: Hiroki TAKEOKA, Hiroshi KUBOTA, Yukikazu OHCHI, Hiroshi FUJII, Yukihiro SHIMASAKI
  • Patent number: 8593785
    Abstract: A laminate includes insulating layers laminated to each other. Capacitor conductors are embedded in the laminate and have exposed portions exposed between the insulating layers at respective surfaces of the laminate. The capacitor conductors define a capacitor. External electrodes are provided by plating on the respective surfaces of the laminate so as to directly cover the respective exposed portions. When the laminate is viewed in plan in a y axis direction, the length of each of the exposed portions is approximately 35% to approximately 45% of the length of an outer periphery of the insulating layer.
    Type: Grant
    Filed: April 25, 2011
    Date of Patent: November 26, 2013
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Takehisa Sasabayashi, Takumi Taniguchi
  • Patent number: 8493708
    Abstract: The disclosure relates generally to capacitor structures and more particularly, to capacitor structures having interdigitated metal fingers. Metal finger capacitors may have at least one layer, the at least one layer including: a first set of fingers, wherein each finger of the first set includes an end integrally connected to a bus segment of a first bus; a second set of fingers interdigitated with the first set of fingers, wherein each finger of the second set includes an end integrally connected to a bus segment of a second bus; an in port integrally connected to the first bus and an out port integrally connected to the second bus; and wherein a width of the first and second bus is non-uniform across a length of the first and second bus.
    Type: Grant
    Filed: February 21, 2011
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventor: Ning Lu
  • Publication number: 20130148260
    Abstract: A thin-film device system includes a substrate and a plurality of pillars. The plurality of pillars project from a surface of the substrate. Each of the plurality of pillars have a perimeter that includes at least four protrusions that define at least four recessed regions between the at least four protrusions. Each of the at least four recessed regions of each of the plurality of pillars receives one protrusion from an adjacent one of the plurality of pillars. A thin-film device is fabricated over the plurality of pillars.
    Type: Application
    Filed: February 5, 2013
    Publication date: June 13, 2013
    Applicant: MEDTRONIC, INC.
    Inventor: Medtronic, Inc.
  • Publication number: 20130063860
    Abstract: Disclosed herein is a lead unit of an energy storage device including a lead frame for fixing withdrawal electrodes of the energy storage device, including: an output terminal unit formed on an upper portion of the lead frame; a lead unit formed to extend from the output terminal unit to a lower portion of the lead frame and allowing end portions of the withdrawal electrodes to be inserted therein; and an expanding unit formed at an end portion of the lead unit and being brought into contact with the withdrawal electrodes in a compressed manner. The fabrication process can be simplified compared with the existing welding method, and a contact area between the withdrawal electrodes and the lead unit can be increased to thus reduce contact resistance.
    Type: Application
    Filed: August 9, 2012
    Publication date: March 14, 2013
    Inventors: Young Hak JEONG, Chan YOON, Hyun Chul JUNG, Bae Kyun KIM
  • Patent number: 8373965
    Abstract: A system and method for sealing a capacitor bottom in a filtered feedthrough. The feedthrough comprises a ferrule, a capacitor, at least one terminal pin and a support structure. The support structure includes at least one projection that extends into an aperture of the capacitor. The projection includes an opening through which the at least one terminal pin extends such that, in an assembled state, the terminal pin extends through the opening of the projection and the aperture of the capacitor.
    Type: Grant
    Filed: February 10, 2009
    Date of Patent: February 12, 2013
    Assignee: Medtronic, Inc.
    Inventor: Rajesh V. Iyer
  • Publication number: 20130003255
    Abstract: An integrated capacitive device includes an electrically conducting comb, at least some of whose teeth form first electrodes of capacitors, and electrically conducting fingers extending between the teeth of the comb so as to form second electrodes of the capacitors. The device includes a first finger-teeth set having a single reference finger forming a reference capacitor having a reference capacitive value, at least one second finger-teeth set including several fingers, the reference finger and the number of fingers of the second finger-teeth set or sets forming a geometric series with ratio two. At least one additional set includes a single additional finger forming, with at least one tooth of the comb, an additional capacitor having an additional capacitive value substantially equal to half the reference capacitive value.
    Type: Application
    Filed: June 14, 2012
    Publication date: January 3, 2013
    Applicant: STMicroelectronics SA
    Inventors: Stephane Letual, Sarah Verhaeren
  • Patent number: 8243451
    Abstract: A cooling member for withdrawing heat from a heat containing device is disclosed. The cooling member can have a housing with a fluid inlet, a fluid outlet and a plurality of irregular-shaped fins located at least partially therewithin. In addition, a plurality of irregular-shaped and hierarchical branched fluid pathways can be located between the plurality of fins and the housing and/or the plurality of fins can be in physical contact with the heat containing device.
    Type: Grant
    Filed: June 8, 2010
    Date of Patent: August 14, 2012
    Assignee: Toyota Motor Engineering & Manufacturing North America, Inc.
    Inventors: Ercan Mehmet Dede, Brian Joseph Robert, Serdar H. Yonak
  • Patent number: 8228661
    Abstract: A film capacitor is provided which has a smaller size and improved capacity while securing a sufficient withstand voltage. The film capacitor comprising a basic element 10 containing a plurality of dielectric layers and at least one vapor-deposited metal film layer 14a, 14b, where the plurality of dielectric layers consisting of a resin film layer 12 and at least one vapor-deposited polymer film layer 16a, and the at least one vapor-deposited polymer film layer 16a is formed on at least one of the resin film layer 12 and the at least one vapor-deposited metal film layer 14a, 14b.
    Type: Grant
    Filed: August 9, 2010
    Date of Patent: July 24, 2012
    Assignee: Kojima Press Industry Co., Ltd.
    Inventors: Kaoru Ito, Masumi Noguchi
  • Patent number: 8139341
    Abstract: A film capacitor comprises a wound body, a first terminal part electrically connected to one end of the wound body, and a second terminal part electrically connected to the other end of the wound body. The wound body is structured by winding into a laminate a first film laminate formed of a laminate of dielectric films and having therein a floating electrode and a second film laminate formed of a laminate of first and second metal films sandwiching the first film laminate and dielectric films and having therein a floating electrode (22). Each of the floating electrodes (22) is composed of integrated small electrodes independent of each other.
    Type: Grant
    Filed: May 30, 2007
    Date of Patent: March 20, 2012
    Assignee: Soshin Electric Co., Ltd.
    Inventors: Yoshikuni Kato, Katsuo Koizumi, Kanji Machida
  • Publication number: 20090154056
    Abstract: A film capacitor includes metallization that is sectionalized, patterned and configured to provide interconnections on only one face of a rolled or stacked film capacitor.
    Type: Application
    Filed: December 17, 2007
    Publication date: June 18, 2009
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: Eladio Clemente Delgado, Michael Andrew de Rooij, Patricia Chapman Irwin, Yang Cao
  • Patent number: 7531112
    Abstract: Disclosed is a composition for forming a dielectric, which is applied to an embedded capacitor with a high dielectric constant, a capacitor produced using the composition, and a PCB provided with the capacitor. The composition includes 40 to 99 vol % of thermoplastic or thermosetting resin, and 1 to 60 vol % of semiconductive filler. Alternatively, the composition includes 40 to 95 vol % of thermoplastic or thermosetting resin, and 5 to 60 vol % of semiconductive ferroelectric substance. Furthermore, the present invention provides the capacitor, produced using the composition, and the PCB provided with the capacitor. Therefore, the dielectric, which is produced using the composition including the semiconductive filler or semiconductive ferroelectric substance, is advantageous in that the dielectric constant is high and a dielectric loss is low. The dielectric is usefully applied to produce an embedded capacitor with the high dielectric constant and the PCB provided with the embedded capacitor.
    Type: Grant
    Filed: June 25, 2004
    Date of Patent: May 12, 2009
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Hyo Soon Shin, Jin Ho Kim, Jeong Joo Kim, Min Ji Ko
  • Publication number: 20080123245
    Abstract: A capacitor structure includes an insulating layer, first conductive patterns, second conductive patterns, an insulating interlayer, third conductive patterns, and fourth conductive patterns. The first and second conductive patterns are alternately arranged on the insulating layer to be spaced apart from one another. The first and second conductive patterns have side faces where concave portions and convex portions are formed. The insulating interlayer is formed on the insulating layer to cover the first and second conductive patterns. The third and fourth conductive patterns are alternately arranged on the insulating interlayer to be spaced apart from one another. The third and fourth conductive patterns have side faces where concave portions and convex portions are formed.
    Type: Application
    Filed: November 28, 2007
    Publication date: May 29, 2008
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Keun-Bong Lee, Jung-Hyeon Kim
  • Patent number: 7326367
    Abstract: This invention is related to thick film conductor compositions comprising electrically conductive gold powder, one or more glass frit or ceramic oxide compositions and an organic vehicle. It is further directed to the composition's uses for LTCC (low temperature co-fired ceramic) tape, for fabrication of multilayer electronic circuits and in high frequency microelectronic applications.
    Type: Grant
    Filed: April 5, 2006
    Date of Patent: February 5, 2008
    Assignee: E.I. du Pont de Nemours and Company
    Inventors: Patricia J. Ollivier, Kenneth Warren Hang
  • Patent number: 7301752
    Abstract: Disclosed is a method of fabricating a metal-insulator-metal (MIM) capacitor. In this method, a dielectric layer is formed above a lower conductor layer and an upper conductor layer is formed above the dielectric layer. The invention then forms an etch stop layer above the upper conductor layer and the dielectric layer, and forms a hardmask (silicon oxide hardmask, a silicon nitride hardmask, etc.) over the etch stop layer. Next, a photoresist is patterned above the hardmask, which allows the hardmask, the etch stop layer, the dielectric layer, and the lower conductor layer to be etched through the photoresist.
    Type: Grant
    Filed: June 4, 2004
    Date of Patent: November 27, 2007
    Assignee: International Business Machines Corporation
    Inventors: Douglas D. Coolbaugh, Ebenezer E. Eshun, Natalie B. Feilchenfeld, Michael L. Gautsch, Zhong-Xiang He, Matthew D. Moon, Vidhya Ramachandran, Barbara Waterhouse
  • Patent number: 7042701
    Abstract: A high-voltage stacked capacitor includes a first capacitor and a second capacitor. Each capacitor includes a first plate having a first semiconductive body and a second plate having a floating electrode. The first and second semiconductive bodies are electrically isolated from each other. The floating electrode includes an intercapacitor node configured to self-adjust to a value less than a working voltage impressed on the stacked capacitor.
    Type: Grant
    Filed: September 1, 2004
    Date of Patent: May 9, 2006
    Assignee: Impinj, Inc.
    Inventors: Christopher J. Diorio, Frederic J. Bernard
  • Patent number: 6922328
    Abstract: The invention provides a semiconductor device and a method for manufacturing the same that are capable of contributing to a further chip downsizing in the cross-point FeRAM. More particularly, a first local wiring can be formed on a first interlayer insulating layer so as to connect a drain region and part of a gate electrode in a MOS transistor and a top layer wiring. A second local wiring can be formed on a second interlayer insulating layer so as to connect a source region in the MOS transistor and a lower electrode layer in a ferroelectric capacitor, and further to connect part of a gate electrode in the MOS transistor and the top layer wiring. The MOS transistor that makes up of a peripheral circuitry using only the first and second local wiring can be formed directly under a capacitor array forming region of cross-point FeRAM.
    Type: Grant
    Filed: May 20, 2004
    Date of Patent: July 26, 2005
    Assignee: Seiko Epson Corporation
    Inventor: Shinichi Fukada
  • Patent number: 6917129
    Abstract: An electro-mechanical drive device for adjustment devices of a motor vehicle, more particularly for a window lifter, has a gearing with a gear housing, an electric motor mechanically connected to the gearing, a control device mounted in the gearing housing and having at least one power semi-conductor for controlling the electric motor, and means as a heat sink thermally coupled to the power semi-conductor to draw off the waste heat from the power semi-conductor. The means which as heat sink draws off the waste heat from the power semi-conductor is integrated in the gear housing. With the integration of the means for drawing off the waste heat into the gear housing it is possible for the means to undertake further mechanical or thermal functions extending beyond the function as heat sink.
    Type: Grant
    Filed: April 20, 2001
    Date of Patent: July 12, 2005
    Assignee: Brose Fahrzeugteile GmbH & Co. KG., Coburg
    Inventors: Herbert Becker, Gerhard Schelhorn, Volker Aab, Reiner Kurzendoarfer, Karl-Heinz Rosenthal
  • Patent number: 6903916
    Abstract: The present invention provides a technique which permits the withstand voltage measurement of a laminate web for capacitor layer manufactured by a continuous laminating method in a roll state wound around a core tube. The invention provides a roll of laminate for capacitor layer which is obtained by manufacturing a laminate web for capacitor layer by laminating a first electrically conductive layer, a dielectric layer and a second electrically conductive layer and winding this laminate web for capacitor layer from a start end side to a terminal end side thereof around a core tube.
    Type: Grant
    Filed: November 21, 2003
    Date of Patent: June 7, 2005
    Assignee: Mitsui Mining & Smelting Co., Ltd.
    Inventors: Kazuhiro Yamazaki, Takashi Syoujiguchi
  • Patent number: 6831529
    Abstract: A feed-through filter capacitor assembly using an electrically conductive adhesive modified with a filler of low coefficient of thermal expansion (CTE) to provide a conductive relation between the conductive pin and the electrode plates of the ceramic capacitor. The conductive adhesive contains an organic polymer-based adhesive component that has a CTE greater than the CTE of the capacitor ceramic body and a conductive metal filler having a CTE lower than the adhesive component. The conductive adhesive is further provided with a CTE-lowering filler that has a CTE lower than the CTE of the conductive metal filler, thereby lowering the overall CTE of the adhesive to a value closer to the CTE of the capacitor ceramic body.
    Type: Grant
    Filed: May 20, 2003
    Date of Patent: December 14, 2004
    Inventors: Lambert Devoe, Alan Devoe
  • Patent number: 6819542
    Abstract: A capacitor has at least two layers of substantially parallel interdigitated strips. The strips of each layer are alternately connected to a first and a second bus. The first and second buses of each layer are interconnected to first and second buses of an adjacent layer. The strips of each layer are approximately perpendicular to strips of an adjacent layer. The capacitor further includes dielectric material between strips of the same and different layers. A method of fabricating the capacitor includes forming at least two layers of substantially parallel interdigitated strips which are alternately connected to first and second buses of each layer. The buses of each layer are connected to the respective buses of an adjacent layer. The strips of one layer are approximately perpendicular to the strips of an adjacent layer. Dielectric material is formed between strips of the same and different layers.
    Type: Grant
    Filed: March 4, 2003
    Date of Patent: November 16, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tse-Lun Tsai, Yu-Tai Chia, JC Guo
  • Patent number: 6798642
    Abstract: This invention relates to capacitor films that have increased moisture and breakdown resistance. The capacitor films include a polymer coating that helps prevent air entrapment.
    Type: Grant
    Filed: January 24, 2003
    Date of Patent: September 28, 2004
    Assignee: Toray Plastics (America), Inc.
    Inventors: Wolfgang Decker, Shawn Early
  • Publication number: 20040150940
    Abstract: The present invention is directed to a method for fabricating a thin film capacitor of a metal/insulator/metal (MIM) structure, which is capable of enabling small-sizing of a semiconductor device while maintaining electrostatic capacity of a capacitor. The method comprises the steps of: forming a heterogeneous film on a lower insulation film on a structure of a semiconductor substrate; forming a plurality of projections by selectively etching the heterogeneous film; and forming a first electrode layer, a dielectric layer, and a second electrode layer on the lower insulation including the plurality of projections in order along a surface shape of the projections such that a plurality of projecting parts are formed in the first electrode layer, the dielectric layer and the second electrode layer, respectively.
    Type: Application
    Filed: December 30, 2003
    Publication date: August 5, 2004
    Applicant: Anam Semiconductor Inc.
    Inventor: Young-Hun Seo
  • Patent number: 6594134
    Abstract: A polymer film capacitor is provided, utilizing a metallized film formed by a first vacuum-formed plasma treated surface, a vacuum-deposited, first radiation polymerized acrylate monomer film having first and second surfaces, the first surface being disposed on the first plasma-treated surface of the polymer substrate, and a metal layer disposed on the second surface of the first polymerized film. The metallized film is wound into a capacitor.
    Type: Grant
    Filed: February 21, 2001
    Date of Patent: July 15, 2003
    Assignee: Sigma Laboratories of Arizona, Inc.
    Inventor: Angelo Yializis
  • Patent number: 6573584
    Abstract: The present invention provides a thin film capacitor which comprises: a carrier substrate; a thin film element provided on the carrier substrate and having an insulating layer and a plurality of electrode layers, the thin film element including areas formed with no insulating layer; and a plurality of external terminals electrically connected to the corresponding electrode layers for receiving electrical signals of different potentials applied thereto, the plurality of external terminals being respectively provided in the areas formed with no insulating layer and bonded to the carrier substrate via the electrode layers connected thereto. The thin film capacitor according to the invention features a sufficient insulating property and a higher break down voltage.
    Type: Grant
    Filed: October 27, 2000
    Date of Patent: June 3, 2003
    Assignee: Kyocera Corporation
    Inventors: Shoken Nagakari, Shunichi Kuwa, Shigeo Kounushi