Abstract: A ceramic electronic component includes an element body, a first external electrode, and a second external electrode. The element body includes a dielectric, at least one first internal electrode, and at least one second internal electrode laminated over the first internal electrode via the dielectric interposed therebetween. The element body has a top surface, a bottom surface, a pair of side surfaces, a first end surface, and a second end surface, thereby the element body having a generally cuboid shape. The first internal electrode is exposed on the first end surface. The second internal electrode is exposed on the second end surface. The side surfaces of the element body are concavely curved along a longitudinal direction, so that the element body has a longitudinal central part at which a width is less than a width at the end surface. The first external electrode is formed on the first end surface and electrically connected with the first internal electrode.

Abstract: A multilayer ceramic capacitor includes a multilayer body, and two external electrodes. The multilayer body includes a multilayer body main portion including an inner layer portion including dielectric layers and internal electrode layers that are stacked, and two outer layer portions on opposite sides of the inner layer portion in a stacking direction, two side gap portions on opposite sides of the multilayer main body in a width direction, two main surfaces on opposite sides in the stacking direction, two side surfaces on opposite sides in the width direction, and two end surfaces on opposite sides in a length direction. Each of the two external electrodes are at an end surface of the multilayer body, and extend from the end surface to a portion of the main surface. An end of the side gap portion on a side of the main surface protrudes farther than the multilayer main body.

Abstract: An apparatus includes a case capable of receiving a plurality of capacitive elements, each capacitor element having at least two capacitors, and each capacitor having a capacitive value. The apparatus also includes a cover assembly with a peripheral edge secured to the case. The cover assembly includes, for each of the plurality of capacitive elements, a cover terminal that extends upwardly from the cover assembly generally at a central region of the cover assembly. Each cover terminal is connected to one of the at least two capacitors of the respective one of the plurality of capacitive elements. The cover assembly also includes, for each of the plurality of capacitive elements, a cover terminal that extends upwardly from the cover assembly at a position spaced apart from the cover terminal generally at the central region of the cover assembly.

Abstract: Disclosed herein is a multi-planar circuit board, as well as related structures and methods. In an embodiment, a circuit board may include a first surface, a first section having the first surface in a first plane, a second section having the first surface in a second plane, and a third section connecting the first and second sections, where the third section defines a gradient between the first and second planes, and where all sections are sections within a contiguous board. In another embodiment, circuit board may further include a first component having a first thickness coupled on the first face of the first section, and a second component having a second thickness, greater than the first component, coupled on the first face of the second section, where the second section is in a lower plane, and where the overall thickness is the circuit board thickness plus the second thickness.

Abstract: A memory cell arrangement is provided that may include: a control circuit configured to supply a precondition signal and one of at least two write signals to a memory cell of the memory cell arrangement, the memory cell including a field-effect transistor structure and a remanent-polarizable layer, wherein the precondition signal is configured to bring the memory cell from an actual condition into a predefined condition, wherein the predefined condition is associated with a predefined threshold voltage of the field-effect transistor structure of the memory cell, and wherein the at least two write signals are configured to write the memory cell selectively into a first memory state or into a second memory state.

Abstract: An electronic device includes at least two chip components, a hold member with insulation, a first conductive terminal piece, a second conductive terminal piece, and an intermediate connection piece. The hold member holds the chip components side by side. The intermediate connection piece connects the terminal electrode of one of the chip components and the terminal electrode of the other chip component.

Abstract: An electronic device includes a chip component and a metal terminal. The chip component includes a terminal electrode formed on an element body. The metal terminal is connectable with the terminal electrode of the chip component. The metal terminal includes a terminal body and a pair of holding pieces. The terminal body faces an end surface of the terminal electrode of the chip component. The holding pieces are formed on the terminal body. A connection member configured to connect the terminal body and the end surface of the terminal body exists in a joint region between the terminal body and the end surface of the terminal electrode. A pair of reinforcement pieces is formed on the terminal body so as not to overlap with the joint region in a direction extending from one to the other of the pair of holding pieces.

Abstract: The present disclosure relates to a component structure, a power module and a power module assembly structure having the component structure. The component structure comprises: a first bus bar, having one end extending to a first plane to form a first connecting terminal; a second bus bar, comprising a front portion of the second bus bar and a rear portion of the second bus bar, wherein the front portion of the second bus bar is laminated in parallel with the first bus bar, and the rear portion of the second bus bar is extended to a second plane to form a second connecting terminal; and an external circuit comprising a third bus bar, wherein the third bus bar is settled in parallel with the rear portion of the second bus bar, to reduce a parasitic inductance between the first connecting terminal and the second connecting terminal.

Abstract: An electronic component includes a capacitor body, and first and second external electrodes disposed and spaced apart from each other on a mounting surface of the capacitor body. The electronic component further includes first and second connection terminals respectively connected to the first and second external electrodes and having first and second cutouts, respectively. The electronic component also includes a first plating layer covering the first external electrode and the first connection terminal, and a second plating layer covering the second external electrode and the second connection terminal.

Abstract: A thin film capacitor includes a body including a dielectric layer, a first internal electrode layer and a second internal electrode layer, a melting point of a material included in the first internal electrode layer being lower than a melting point of a material included in the second internal electrode layer, and a first external electrode and a second external electrode disposed on an upper surface of the body, the second internal electrode layer being disposed on an upper surface of the first internal electrode layer and a lower surface of the first internal electrode layer opposing the upper surface of the first internal electrode layer.

Abstract: Disclosed is a method for the manufacture of a multilayer structure comprising a first layer, a second layer and a third layer for example to form a capacitor. The multilayer structure comprises a first layer, a second layer and a third layer, wherein the first layer and the third layer each form at least one of at least two electrodes and comprise one or more pyrolyzed carbon nanomembranes or one or more layers of graphene, and the second layer is a dielectric comprising one or more carbon nanomembranes.

Abstract: An electrical connector includes a first pass-through connector, a second pass-through connector, and a center portion coupled between the first pass-through connector and the second pass-through connector. The center portion includes a plurality of electrical connection points on an exterior surface of the center portion. The electrical connector also includes a plurality of pass-through wires extending from the first pass-through connector to the second pass-through connector through the center portion, wherein the plurality of electrical connection points are electronically coupled to the plurality of pass-through wires.

Abstract: The invention relates to a contact part (20) for electrically connecting end-face contact layers on the end faces of a plastic film capacitor winding (10) of an encased electric single-phase or three-phase capacitor to a terminal wire (18, 34) or a connecting wire, comprising a preferably flat contact support with a terminal region for contacting a terminal wire (18, 34) or a connecting wire; comprising at least one contact piece (26) with at least one contact tip, said contact piece (26) extending upwards or downwards from the contact support in a substantially vertical manner, in order to establish an electric connection to an end-face contact layer (12, 14) by pressing the contact tip into said end-face contact layer (12, 14); and comprising a penetration depth-limiting device for limiting the penetration depth of the contact tip or the contact tips in the end-face contact layer (12, 14). The invention also relates to encased single-phase and three-phase capacitors comprising said contact part.

Abstract: In an embodiment, a multilayer ceramic capacitor 20 has a first external electrode 22 having a second part 22b, and a second external electrode 23 having a second part 23b, and each second part have an external shape where length L21 becomes the largest at a width-direction center portion 22b1 or 23b1 and length L22 becomes the smallest at a width-direction edge 22b3 or 23b3, with the length decreasing gradually from the width-direction center portion 22b1 or 23b1 to the width-direction edge 22b3 or 23b3.

Abstract: A capacitor provides a plurality of selectable capacitance values, by selective connection of six capacitor sections of a capacitive element each having a capacitance value. The capacitor sections are provided in a plurality of wound cylindrical capacitive elements. Two vertically stacked wound cylindrical capacitance elements may each provide three capacitor sections. There may be six separately wound cylindrical capacitive elements each providing a capacitor section. The capacitor sections have a common element terminal.

Abstract: A composite electronic component includes: a composite body in which a multilayer ceramic capacitor and a ceramic chip are coupled to each other. The multilayer ceramic capacitor includes a first ceramic body, and first and second external electrodes disposed on both end portions of the first ceramic body. The ceramic chip includes a second ceramic body disposed on a lower portion of the multilayer ceramic capacitor, and first and second terminal electrodes disposed on both end portions of the second ceramic body and connected to the first and second external electrodes. A width of first regions of the second ceramic body in which the first and second terminal electrodes are disposed is wider than a width of a second region of the second ceramic body between the first regions.

Abstract: A multilayer ceramic capacitor includes an active region including a plurality of dielectric layers, and first and second internal electrodes alternately disposed with each of the dielectric layers interposed therebetween; and upper and lower cover regions including at least one ferromagnetic layer and disposed on and below the active region, respectively.

Abstract: An integrated circuit may include a gate, having gate fingers. The integrated circuit may also include a body, having semiconductor pillars interlocking with the gate fingers of the gate. The integrated circuit may also include a backside contact(s) coupled to the body. The integrated circuit may further include a backside metallization. The backside metallization may be coupled to the body through the backside contact(s).

Abstract: In a multilayer ceramic capacitor, SG represents an average of a distance between end portions of inner electrodes in a width direction and side surfaces of a ceramic body, OT represents an average of a distance between inner electrodes closest to main surfaces and the main surfaces, ET1 represents an average of dimensions of each portion of third and fourth terminal electrodes located on the main surfaces, and ET2 represents an average of dimensions of each portion of the third and fourth terminal electrodes located on the side surfaces. A dimension of the ceramic body in the width direction is larger than a dimension of the ceramic body in the height direction and Equations (1) and (2) are satisfied: SG>OT??(1) ET1>ET2??(2).

Abstract: In one general aspect, a method can include forming a redistribution layer on a substrate using a first electroplating process, and forming a conductive pillar on the redistribution layer using a second electroplating process. The method can include coupling a semiconductor die to the redistribution layer, and can include forming a molding layer encapsulating at least a portion of the redistribution layer and at least a portion of the conductive pillar.

Abstract: A multilayer ceramic electronic part may include: a ceramic body; an active layer including a plurality of first and second internal electrodes disposed to be alternately exposed to both end surfaces of the ceramic body, having the dielectric layer therebetween; an upper cover layer formed on an upper portion of the active layer; a lower cover layer formed on a lower portion of the active layer and having a thickness thicker than that of the upper cover layer; and first and second external electrodes electrically connected to the first and second internal electrodes, wherein the first and second external electrodes include: first and second conductive layers extended from both end surfaces of the ceramic body onto upper and lower main surfaces thereof; and first and second insulation layers formed on the first and second conductive layers disposed on both end surfaces of the ceramic body.

Abstract: A pin structure of a modular jack has eight resilient pins. The two intermediate resilient pins have two electrically conducting segments vertically spaced apart and are each wide and have two electrically contacting segments transversely spaced apart and are each slender, whereas the other resilient pins are transversely and consecutively spaced apart and disposed on two sides of the two intermediate resilient pins and are each slender. The electrically fixing ends of the first, third, fifth, seventh resilient pins lie in a first straight line. The electrically fixing ends of the second, fourth, sixth, eighth resilient pins lie in a second straight line. The first and second straight lines are spaced apart and lie on the same plane. The resilient pins have V-shaped electrically contacting portions lying in a third straight line. Hence, the pin structure of a modular jack reduces crosstalk and loss and thereby meets strict standards.

Abstract: Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided herein. A semiconductor arrangement comprises a cap wafer, a microelectromechanical systems (MEMS) wafer, and a complementary metal-oxide-semiconductor (CMOS) wafer. The cap wafer comprises one or more spring structures, such as a first spring structure and a second spring structure. The first spring structure and the second spring structure relieve stress as portions of the semiconductor arrangement, such as a membrane and a poly layer, move. An ambient pressure chamber is formed between the CMOS wafer and the MEMS wafer, such as for CMOS outgassing relief. One or more thermal insulator structures are formed between the CMOS wafer and the MEMS wafer to protect the MEMS wafer from heat originating from the CMOS wafer.

Abstract: A DC link capacitor assembly is provided. The DC link capacitor assembly according to the embodiment includes a DC link capacitor disposed in a housing. The housing includes a top surface, a bottom surface disposed spaced downward from the top surface, at least one side surface connecting the top surface to the bottom surface, an opening defined at a front side between the top surface and the bottom surface and an external capacitor accommodation part disposed outside the side surface.

Abstract: Embodiments of a high-permittivity, low-leakage energy storage device, such as a capacitor, and methods of making the energy storage device are disclosed. The disclosed device includes electrically conductive first and second electrodes, and a sterically constrained dielectric film disposed between the first and second electrodes. The sterically constrained dielectric film comprises a plurality of polymeric molecules, and at least some of the polymeric molecules are bound to the first electrode. The disclosed device may include an insulative layer between the first electrode and the dielectric film and/or between the second electrode and the dielectric film.

Abstract: A connector insert comprising a plurality of layers of conductive elastomer, and a concomitant method of employing a connector insert, the method comprising the steps of fabricating a plurality of layers of conductive elastomer as an insert and placing the insert into a connector.

Abstract: Provided is a laminated capacitor that achieves low impedance in a wide band. The laminated capacitor 1 includes an element assembly 2, terminal electrodes 3, 4, internal electrodes 7, 8 that are connected to the terminal electrodes 3, 4, and an internal electrode 9 that is not connected to the terminal electrodes 3, 4. In the laminated capacitor 1, an interval between each of the first electrode parts 3a, 4a of the first and second terminal electrodes 3, 4 and the internal electrode 9 is smaller than an interval between the internal electrode 9 and the internal electrode 7 or the internal electrode 8 located adjacent to the internal electrode 9.

Abstract: The present disclosure is directed to a device and a method for achieving a precise capacitance of a capacitor. The method includes trimming a first capacitance of the capacitor to a second capacitance, the capacitor having a first conductive layer separated from a second conductive layer by a dielectric layer. Changing a first dielectric constant of the dielectric layer to a second dielectric constant, where the first dielectric constant corresponding to the first capacitance and the second dielectric constant corresponding to the second dielectric constant includes heating the dielectric layer above a threshold temperature for a time period. The heat is provided by either one of the plates of the capacitor or from a separate heater.

Abstract: In one embodiment, an apparatus includes a first reference voltage coupled to a first metal layer and a second reference voltage coupled to a second metal layer. A first finger type in the plurality of fingers is coupled to the first metal layer at a first area and coupled to the first metal layer and the second metal layer at a second area. A second finger type in the plurality of fingers is coupled to the second metal layer at the first area and coupled to the first metal layer and the second metal layer at the second area. Also, the first finger type and the second finger type alternately positioned next to each other.

Abstract: A system and method for sealing a capacitor bottom in a filtered feedthrough. The feedthrough comprises a ferrule, a capacitor, at least one terminal pin and a support structure. The support structure includes at least one projection that extends into an aperture of the capacitor. The projection includes an opening through which the at least one terminal pin extends such that, in an assembled state, the terminal pin extends through the opening of the projection and the aperture of the capacitor.

Abstract: An electronic component includes a laminate including a plurality of insulating layers that are laminated on each other. A capacitor conductor is embedded in the laminate and includes an exposed portion exposed between the insulating layers at a predetermined surface of the laminate. An external electrode is provided on the predetermined surface by direct plating so as to cover the exposed portion. An outer edge of the external electrode is spaced away from the exposed portion by about 0.8 ?m or more.

Abstract: An improved electronic component is described. The electronic component has a capacitor with first planer internal electrodes in electrical contact with a first termination and second planer internal electrodes in electrical contact with a second termination. A dielectric is between the first planer electrodes and the second planer internal electrodes. The electronic component further comprises at least one of: an inductor comprising a conductive trace wherein said conductive trace is between the first termination and a third termination; and an overvoltage protection component comprising: a third internal electrode contained within the dielectric and wherein the third internal electrode is electrically connected to the first termination; a fourth internal electrode contained within the ceramic and electrically connected to a fourth termination; and a gap between the third internal electrode and the fourth internal electrode.

Abstract: Stacked arrays of components are disclosed. In one embodiment, a first and a second layer of components are electrically and mechanically coupled to a thin interposer disposed between the first and second layers. The first layer can be configured to attach the stacked array to a host printed circuit board. The interposer can insulate the components from one another and also couple signals between the components on the first and second layers. In one embodiment, the components in the first and second layers are passive components.

Abstract: A laminated chip electronic component includes: a ceramic body including internal electrodes and dielectric layers; external electrodes covering end portions of the ceramic body in length direction; an active layer in which the internal electrodes are disposed in opposing manner, while having the dielectric layers interposed therebetween, to form capacitance; and upper and lower cover layers formed on upper and lower portions of the active layer in thickness direction, the lower cover layer thicker than the upper cover layer.

Abstract: According to exemplary embodiments of the present disclosure, a capacitor may be connected to a gate electrode of a transistor. The capacitor includes a first gate electrode connected to the gate electrode of the transistor, a gate insulation layer formed on the first gate electrode, and an upper electrode formed on the gate insulation layer. The upper electrode is formed to cover a region where the first gate electrode and the upper electrode are overlapped. The capacitor is applicable to at least one of a light emitting driving circuit and a scan driving circuit, and at least one of the light emitting driving circuit and the scan driving circuit may be included in a display device.

Abstract: Electrode protective films 13a and 13b are formed on the surface of the metal layer using imidazole preflux, as terminal electrodes 35a and 35b of an electronic component. The terminal electrodes of an electronic component on which the protective films are formed are fixed by electroconductive adhesives 33a and 33b supplied to mounting lands 40a and 40b. Thereby an electronic component mounting structure without change in resistance caused by electroconductive adhesives is provided.

Abstract: A printed wiring board includes a core substrate having a penetrating hole, a first conductive layer on a first surface of the substrate, a second conductive layer on a second surface of the substrate, a first electronic component having an electrode and accommodated in the hole such that the electrode faces the first surface, a first structure on the first surface and including a pad for mounting a second electronic component on the first structure and a via conductor connected to the electrode, and a second structure on the second surface. The electrode has an upper surface facing toward the first surface, the first layer has an upper surface facing away from the first surface, and the first component is positioned in the hole such that the upper surface of the electrode forms a gap with the upper surface of the first layer.

Abstract: A method for fabricating a supercapacitor-like electronic battery includes forming a first current collectors on a substrate. A first electrode is formed on the first current collector. A first electrode is formed from a first solid state electrolyte and a first conductive material where the first conductive material is irreversible to the mobile ions contained in the first solid state electrolyte and the first conductive material exceeds the percolation limit. An electrolyte is formed on the first electrode. A second electrode is formed on the electrolyte. The second electrode is formed from a second solid state electrolyte and a second conductive material where the second conductive material is irreversible to the mobile ions contained in the second solid state electrolyte and the second conductive material exceeds the percolation limit. A second current collector is formed on the second electrode.

Abstract: A packaged capacitor component such as a surface mount technology capacitor component may be formed with multiple self-resonant frequencies. The capacitor component may include multiple capacitor portions separated by dielectric layers. The capacitor portions may each be formed from interleaving conductive layers. Additional dielectric layers may be interposed between the interleaving conductive layers. Each capacitor portion may be characterized by a corresponding self-resonance frequency. If desired, a packaged capacitor component having multiple self-resonant frequencies may be formed by stacking multiple surface-mount capacitor components. Each of the stacked surface-mount capacitor components may include interleaving conductive layers that are centered between top and bottom surfaces of that component. Packaged capacitor components having multiple self-resonance frequencies may be used as direct-current blocking capacitors or decoupling capacitors.

Abstract: Disclosed is a ferroelectric material and methods for its use in capacitors that includes a polymer blend of at least two polymers, wherein the first polymer is a ferroelectric polymer and the second polymer has a low dielectric constant.

Abstract: There is provided a multilayer ceramic electronic component including: a ceramic body including a dielectric layer; a plurality of internal electrodes disposed within the ceramic body to face each other, having the dielectric layer interposed therebetween; and external electrodes electrically connected to the plurality of internal electrodes, wherein the ceramic body includes an active layer corresponding to a capacitance forming part and a cover layer formed on at least one of an upper surface and a lower surface of the active layer and corresponding to a non-capacitance forming part, an average thickness of the cover layer is 15 ?m or less, the external electrodes include a conductive metal and glass portions, and when an average length of the glass portions in a length direction of the external electrodes is Ls, Ls?10 ?m is satisfied.

Abstract: Stacked arrays of components are disclosed. In one embodiment, a first and a second layer of components are electrically and mechanically coupled to an interposer with an encapsulated third layer of components disposed between the first and second layers. The first layer can be configured to attach the stacked array to a host printed circuit board. The interposer can couple signals between the components on the first and second layers.

Abstract: A capacitor forming method includes forming an electrically conductive support material over a substrate, with the support material containing at least 25 at % carbon. The method includes forming an opening through at least the support material where the opening has an aspect ratio of at least 20:1 within a thickness of the support material. After forming the opening, the method includes processing the support material to effect a reduction in conductivity, and forming a capacitor structure in the opening.

Abstract: A high power, low passive inter-modulation capacitor is presented, which is formed using metal clad substrates, which are broad-side coupled through a thin air gap. Each substrate may include metal layers affixed on both sides which are electrical coupled together to form a single capacitor plate, or each substrate may have only a single metal layer on the surface adjacent to the air gap. The capacitor has particular application in low cost RF and microwave filters, which may be used in communication equipment and communication test equipment such a diplexers, for low PIM applications.

Abstract: Substrates having power planes, such as, for example, printed circuit boards, include at least one noise suppression structure configured to suppress electrical waves propagating through at least one of a first power plane and a second power plane. The at least one noise suppression structure may include a first power plane extension that extends from the first power plane generally toward the second power plane, and a second power plane extension that extends from the second power plane generally toward the first power plane. Methods for suppressing noise in at least one of the first power plane and second power plane include providing such noise suppression structures between the power planes.

Abstract: Some novel features pertain to a capacitor structure that includes a first conductive layer, a second conductive layer and a non-conductive layer. The first conductive layer has a first overlapping portion and a second overlapping portion. The second conductive layer has a third overlapping portion, a fourth overlapping portion, and a non-overlapping portion. The third overlapping portion overlaps with the first overlapping portion of the first conductive layer. The fourth overlapping portion overlaps with the second overlapping portion of the first conductive layer. The non-overlapping portion is free of any overlap (e.g., vertical overlap) with the first conductive layer. The non-conductive layer separates the first and second conductive layers. The non-conductive layer electrically insulates the third overlapping portion and the fourth overlapping portion from the first conductive layer.

Abstract: A multi-layered capacitor includes three or more capacitor layers. A first layer includes a first DC-biased, tunable capacitor. A second layer, acoustically coupled to the first layer, includes a second DC-biased, tunable capacitor. A third layer, acoustically coupled to the second layer, includes a third DC-biased, tunable capacitor. Each dielectric of the first, second, and third capacitors has a resonance of about the same frequency, within 5%, and inner electrodes of the first, second, and third capacitors have a resonance of about the same frequency, within 5%. The resonance of each layer is a function of at least thickness, density, and material. The first, second, and third layers are biased to generate destructive acoustic interference, and the multi-layer capacitor is operable at frequencies greater than 0.1 GHz.

Abstract: A capacitor device prevents capacitor failure and pixel failure by preventing the capacitor from experiencing a short circuit caused by disconnection of a bridge formed between electrodes of the capacitor and a display apparatus having the capacitor device. A display device comprises a thin film transistor, a light emitting device, and the capacitor device described above.

Abstract: A process for forming a laminate with capacitance and the laminate formed thereby. The process includes the steps of providing a substrate and laminating a conductive foil on the substrate wherein the foil has a dielectric. A conductive layer is formed on the dielectric. The conductive foil is treated to electrically isolate a region of conductive foil containing the conductive layer from additional conductive foil. A cathodic conductive couple is made between the conductive layer and a cathode trace and an anodic conductive couple is made between the conductive foil and an anode trace.

Abstract: Provided is a laminated capacitor that achieves low impedance in a wide band. The laminated capacitor 1 includes an element assembly 2, terminal electrodes 3, 4, internal electrodes 7, 8 that are connected to the terminal electrodes 3, 4, and an internal electrode 9 that is not connected to the terminal electrodes 3, 4. In the laminated capacitor 1, an interval between each of the first electrode parts 3a, 4a of the first and second terminal electrodes 3, 4 and the internal electrode 9 is smaller than an interval between the internal electrode 9 and the internal electrode 7 or the internal electrode 8 located adjacent to the internal electrode 9.