With Coupling Or Decoupling Capacitor Patents (Class 361/734)
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Patent number: 11830804Abstract: Techniques are disclosed herein for creating over and under interconnects. Using techniques described herein, over and under interconnects are created on an IC. Instead of creating signaling interconnects and power/ground interconnects on a same side of a chip assembly, the signaling interconnects can be placed on an opposing side of the chip assembly as compared to the power interconnects.Type: GrantFiled: April 1, 2020Date of Patent: November 28, 2023Assignee: Invensas LLCInventors: Belgacem Haba, Stephen Morein, Ilyas Mohammed, Rajesh Katkar, Javier A. Delacruz
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Patent number: 11751930Abstract: An ablation apparatus for creating a lesion in target tissue, the ablation apparatus including a handle, an elongate shaft extending from the handle to a distal tip, where the shaft includes a first portion, an ablation portion distal to the first portion and having an outer sheath, and at least one ablation energy element disposed within the outer sheath, where a space is formed between the at least one ablation energy element and the outer sheath. The ablation apparatus further includes a thermally conductive liner disposed within the space.Type: GrantFiled: January 8, 2019Date of Patent: September 12, 2023Assignee: ADAGIO MEDICAL, INC.Inventors: Alexei V. Babkin, Thomas Chien, Kevin D. Rupp, Steven W. Kovalcheck
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Patent number: 11631974Abstract: A snubber circuit includes a snubber substrate including an electrically insulating carrier and an electrically conducting structured layer applied thereon, the electrically conducting structured layer including two segments. The snubber circuit further includes two electrically resistive layers, each resistive layer being applied onto the two segments of the electrically conducting structured layer of the snubber substrate, and a capacitor disposed on the electrically resistive layers and having two terminals, each terminal being electrically connected to one of the electrically resistive layers. Further, a power semiconductor module having such a snubber circuit is disclosed.Type: GrantFiled: July 2, 2020Date of Patent: April 18, 2023Assignee: Infineon Technologies AGInventors: Michael Schlueter, Andre Uhlemann
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Patent number: 10420216Abstract: A video camera head is comprised of at least two rigid printed circuit boards (PCBS) arranged in parallel planes. The at least two PCBs are mechanically supported one above the other by pins made of an electricity conducting material that conduct electrical power from the bottom PCB to electronic components or illumination means mounted on the other PCBs and signals from a solid state sensor chip mounted on one of the other PCBs of the at least two PCBs to the bottom PCB. Several embodiments of the video camera head are described.Type: GrantFiled: June 9, 2016Date of Patent: September 17, 2019Assignee: Medigus Ltd.Inventors: Amir Govrin, Minelu Sonnenschein
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Patent number: 10404575Abstract: A switching device comprising a substrate and multiple switches connected to the substrate to provide a switching function. Each of the multiple switches includes a plurality of ports that each utilize a corresponding connection to another switch or to an external device. Each of the ports of each switch are associated with an independently sized buffering queue, with a buffering queue size of at least a first port being different than a buffering queue size of a second port.Type: GrantFiled: September 25, 2017Date of Patent: September 3, 2019Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LPInventors: Nicholas McDonald, Alan Davis
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Patent number: 10068886Abstract: A method and apparatus are provided for implementing an enhanced three dimensional (3D) semiconductor stack. A chip carrier has an aperture of a first length and first width. A first chip has at least one of a second length greater than the first length or a second width greater than the first width; a second chip attached to the first chip, the second chip having at least one of a third length less than the first length or a third width less than the first width; the first chip attached to the chip carrier by connections in an overlap region defined by at least one of the first and second lengths or the first and second widths; the second chip extending into the aperture; and a heat spreader attached to the chip carrier and in thermal contact with the first chip for dissipating heat from both the first chip and second chip.Type: GrantFiled: April 29, 2015Date of Patent: September 4, 2018Assignee: International Business Machines CorporationInventors: Paul W. Coteus, Shawn A. Hall, Todd E. Takken
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Patent number: 9882655Abstract: An optical network-on-chip and a method and an apparatus for dynamically adjusting optical link bandwidth is presented, wherein each fixedly interconnected optical transceiver in a cluster in the optical network-on-chip is configured to establish a link between the cluster and one cluster in other n-x clusters to exchange an optical signal; and a main controller is configured to allocate x adaptively interconnected transceivers to k fixed links with the heaviest communication traffic according to a set rule and communication traffic of fixed links established by n-x fixedly interconnected optical transceivers in the cluster; and for an adaptively interconnected optical transceiver in the x adaptively interconnected optical transceivers, control the adaptively interconnected optical transceiver to establish a link, except the fixed link, between two clusters connected by the fixed link.Type: GrantFiled: September 19, 2016Date of Patent: January 30, 2018Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Yang Li, Qinye Huang, Xiaosong Cui
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Patent number: 9153476Abstract: A prefabricated multi-die leadframe having a plurality of contact pads is mounted over a temporary carrier. A first semiconductor die is mounted over the carrier between the contact pads of the leadframe. A second semiconductor die is mounted over the contact pads of the leadframe and over the first die. An encapsulant is deposited over the leadframe and first and second die. The carrier is removed. A first interconnect structure is formed over the leadframe and the first die and a first surface of the encapsulant. A channel is cut through the encapsulant and leadframe to separate the contact pads. A plurality of conductive vias can be formed through the encapsulant. A second interconnect structure is formed over a second surface of the encapsulant opposite the first surface of the encapsulant. The second interconnect structure is electrically connected to the conductive vias.Type: GrantFiled: November 30, 2012Date of Patent: October 6, 2015Assignee: STATS ChipPAC, Ltd.Inventors: HeeJo Chi, YeongIm Park, HyungMin Lee
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Publication number: 20150124412Abstract: Systems, methods, and devices are provided for coupling a direct current (DC) pre-charging circuit to a motor drive. In one embodiment, an industrial automation device may include an enclosed module that may include a pre-charge circuit. The pre-charge circuit may pre-charge a direct current (DC) bus. Further, the DC bus may couple to an inverter. The enclosed module may also include a power input that may couple the pre-charge circuit to a DC power source and an electrical output structure that may couple the pre-charge circuit to the inverter. Additionally, the pre-charge circuit may be removeably coupled to the inverter and the DC power source via a sliding action of the enclosed module.Type: ApplicationFiled: November 6, 2013Publication date: May 7, 2015Applicant: Rockwell Automation Technologies, Inc.Inventors: Jeremy Jon Keegan, Yogesh Patel, Bruce William Weiss, James Allen Carter
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Patent number: 8929084Abstract: A compact radio core engine (CE) module uniquely small in size and power consumption, in which only two circuit boards provide all the modem and transceiver functions needed for modern military radios. A modem circuit board has modem devices and a first connector mounted on the board, and a radio frequency (RF) circuit board has RF devices and a second connector mounted on the board. A module frame has an interior wall, and a side wall about the periphery of the interior wall. The modem and the RF circuit boards are positioned on opposite sides of the interior wall, and the connectors on the two boards mate with one another through an opening in the interior wall to exchange operating data and signals between the devices on the boards. The modem circuit board is seated entirely within a recess formed by the interior and the side walls of the frame.Type: GrantFiled: May 8, 2012Date of Patent: January 6, 2015Assignee: BAE Systems Information and Electronic Systems Integration Inc.Inventors: Michael S. Vogas, Boris Radovcic, Todd R. DeLuck, George M. Horihan, Minh Le, Kenneth E. Kolodziej
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Patent number: 8922972Abstract: An integral solar module power conditioning system includes one or more solar module support frames. Each frame includes a plurality of plug-and-play electrical connectors integrated therewith. A microinverter or microinverter connector is also integrated with each frame. Each frame is configured to receive a respective solar electric module and to carry electrical power through a plurality of solar electric modules and corresponding microinverters connected together via a plurality of solar module support frames connected together via the plurality of integrated plug-and-play electrical connectors.Type: GrantFiled: August 12, 2011Date of Patent: December 30, 2014Assignee: General Electric CompanyInventors: Charles Steven Korman, Neil Anthony Johnson, Michael Andrew de Rooij
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Patent number: 8767404Abstract: Integrated circuits with decoupling capacitor circuitry are provided. The decoupling capacitor circuitry may include density-compliance structures. The density-compliance structures may be strapped to metal paths driven by power supply lines. Strapping density-compliance dummy structures in this way may increase the capacitance per unit area of the decoupling capacitor circuitry. Strapping density-compliance dummy structures in this way may shield the decoupling capacitor from nearby noisy signal sources.Type: GrantFiled: July 1, 2011Date of Patent: July 1, 2014Assignee: Altera CorporationInventor: Chin Hieang Khor
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Patent number: 8743548Abstract: The present invention provides an electric circuit device in which it is possible to achieve simultaneously the improvement of cooling performance and reduction in operating loss due to line inductance. The above object can be attained by constructing multiple plate-like conductors so that each of these conductors electrically connected to multiple semiconductor chips is also thermally connected to both chip surfaces of each such semiconductor chip to release heat from the chip surfaces of each semiconductor chip, and so that among the above conductors, a DC positive-polarity plate-like conductor and a DC negative-polarity plate-like conductor are opposed to each other at the respective conductor surfaces.Type: GrantFiled: September 23, 2011Date of Patent: June 3, 2014Assignee: Hitachi, Ltd.Inventors: Takeshi Tokuyama, Kinya Nakatsu, Atushi Kawabata
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Patent number: 8659119Abstract: An electronic module including a substrate having at least one structure that reduces stress flow through the substrate, wherein the structure comprises at least one trench in a surface of the substrate.Type: GrantFiled: May 20, 2010Date of Patent: February 25, 2014Assignee: International Business Machines CorporationInventors: Vijayeshwar D. Kharma, Jennifer V. Muncy, Arun Sharma, Sri M. Sri-Jayantha, Lorenzo Valdevit, David Questad
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Patent number: 8379403Abstract: A spacer-connector and connection arrangements between daughter boards and motherboards are disclosed. Assemblies may include a daughter board one or more spacer-connectors spacing the daughter board above a motherboard and conductive elastomers providing electrical connections between the daughter board and spacer-connector and between the spacer-connector and the motherboard. The spacer-connector may include ground, power, digital and/or controlled impedance RF pathways to conduct signals between the daughter board to the mother board.Type: GrantFiled: March 30, 2010Date of Patent: February 19, 2013Assignee: QUALCOMM, IncorporatedInventors: David W. Waite, James L. Blair, Ashish Lohiya, Arvid G. Sammuli, Jeffrey T. Smith, Saritha Narra
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Patent number: 8304854Abstract: Disclosed are a semiconductor integrated circuit chip, a multilayer chip capacitor, and a semiconductor integrated circuit chip package. The semiconductor integrated circuit chip includes a semiconductor integrated circuit chip body, an input/output terminal disposed on the outside of the semiconductor integrated circuit chip body, and a decoupling capacitor disposed at a side face of the semiconductor integrated circuit chip body and electrically connected to the input/output terminal. The semiconductor integrated circuit chip cab be obtained, which can maintain an impedance of a power distribution network below a target impedance in a wide frequency range, particularly at a high frequency, by minimizing an inductance between a decoupling capacitor and a semiconductor integrated circuit chip.Type: GrantFiled: November 13, 2008Date of Patent: November 6, 2012Assignees: Samsung Electro-Mechanics Co., Ltd., Clemson UniversityInventors: Byoung Hwa Lee, Min Cheol Park, Ho Cheol Kwak, Haixin Ke, Todd Harvey Hubing
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Patent number: 8306652Abstract: In one embodiment, a communication system for a multi-blade server system includes a multi-drop serial bus network interconnecting a management module with each of a plurality of servers in a multi-server chassis. A first transceiver subsystem is configured for communicating over the serial bus network between the management module and each server within a first frequency band. A second transceiver subsystem is configured for simultaneously communicating over the serial bus network between the management module and the servers within a second frequency band higher than the first frequency band. A first signal-filtering subsystem substantially filters out signals in the second frequency band from the first transceiver subsystem. A second signal-filtering subsystem substantially filters out the signals in the first frequency band from the second transceiver subsystem.Type: GrantFiled: March 14, 2008Date of Patent: November 6, 2012Assignee: International Business Machines CorporationInventors: Justin Potok Bandholz, Clifton Ehrich Kerr, Pravin Patel, Bruce James Wilkie
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Patent number: 8279610Abstract: An electronic component package has a base in the shape of a rectangle as viewed from the top, and a metal lid. A terminal electrode on a base bottom surface and a circuit substrate are joined using a conductive adhesive material. In the electronic component package, a first terminal electrode group including two or more terminal electrodes formed in parallel is formed eccentrically to one corner position of the base bottom surface, and a single second terminal electrode, or a second terminal electrode group including two or more terminal electrodes formed in parallel, is formed eccentrically only to a first diagonal position diagonally opposite the one corner position. Also, no-electrode regions in which no terminal electrode is formed along a short side of the base are provided at another corner position facing the one corner position in a short side direction of the base, and a second diagonal position diagonally opposite the other corner position.Type: GrantFiled: August 21, 2008Date of Patent: October 2, 2012Assignee: Daishinku CorporationInventors: Minoru Iizuka, Koichi Kishimoto, Kozo Shibutani, Kentaro Nakanishi
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Publication number: 20120176750Abstract: A wireless terminal device includes: a conduction and connection module, and a first Printed Circuit Board, PCB, connected to the conduction and connection module, and the wireless terminal device further includes a first conductor, where one of the conduction and connection module and the first PCB is connected to one end of the first conductor through a first capacitance coupling module, and the other one of the conduction and connection module and the first PCB is connected to the other end of the first conductor. Through the foregoing processing, capacitance coupling and grounding between the conduction and connection module and the PCB can be implemented through the first capacitance coupling module.Type: ApplicationFiled: March 16, 2012Publication date: July 12, 2012Inventors: Yanping XIE, Qing Liu, Ping Lei, Yao Lan, Shuhui Sun
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Patent number: 8145258Abstract: A radio communication apparatus includes housings that are connected via a hinge unit in an openable/closeable manner, and circuit boards in the housings. The circuit boards are connected via circuit connecting lines functioning as an inductor. One end of the hinge unit is connected to an end portion of the housing and the other end thereof is connected to a portion located farther inside than an end portion of the housing. When the housings are unfolded, a region extending from the portion to the end portion of the housing overlaps a region near the end portion of the housing in a projection domain. A high dielectric member is provided in this overlapped region, and a capacitor is constituted by the high dielectric member and ground areas.Type: GrantFiled: September 9, 2009Date of Patent: March 27, 2012Assignee: Murata Manufacturing Co., Ltd.Inventors: Jin Sato, Kengo Onaka
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Patent number: 8107245Abstract: A system that facilitates high-speed signaling between integrated circuit chips comprising a cable, wherein the cable includes a first and second active connector that facilitate communication between integrated circuit chips. The first active connector includes a capacitive receiver which receives a signal from a corresponding capacitive transmitter located on a first integrated circuit chip through capacitive coupling, and a transmitter which transmits a signal received by the capacitive receiver, through the interconnect medium within the cable, to the second active connector. The second active connector includes a receiver which receives a signal transmitted through the interconnect medium of the cable, and a capacitive transmitter which transmits the signal to a corresponding capacitive receiver located on a second integrated circuit chip through capacitive coupling.Type: GrantFiled: June 24, 2005Date of Patent: January 31, 2012Assignee: Oracle America, Inc.Inventors: Ashok V. Krishnamoorthy, Arthur Zingher, Danny Cohen, Robert Drost
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Patent number: 8027170Abstract: An electronic device which includes a feedthrough capacitor mounted on a front surface of a substrate. A feedthrough electrode penetrates a laminate (body of the capacitor). External electrodes are electrically connected to opposite ends of the feedthrough electrode. A capacitor electrode is disposed to form capacity in cooperation with the feedthrough electrode. A wiring conductor is formed on a rear surface of the substrate or inside the substrate, and via-hole conductors are connected to the wiring conductor. The feedthrough electrode and the external electrodes constitute a first current path. The wiring conductor and the via-hole conductors constitute a second current path electrically connected in parallel to the first current path.Type: GrantFiled: December 22, 2008Date of Patent: September 27, 2011Assignee: Murata Manufacturing Co., Ltd.Inventors: Kazuo Hattori, Isamu Fujimoto
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Patent number: 7961472Abstract: The present invention provides an electric circuit device in which it is possible to achieve simultaneously the improvement of cooling performance and reduction in operating loss due to line inductance. The above object can be attained by constructing multiple plate-like conductors so that each of these conductors electrically connected to multiple semiconductor chips is also thermally connected to both chip surfaces of each such semiconductor chip to release heat from the chip surfaces of each semiconductor chip, and so that among the above conductors, a DC positive-polarity plate-like conductor and a DC negative-polarity plate-like conductor are opposed to each other at the respective conductor surfaces.Type: GrantFiled: April 26, 2007Date of Patent: June 14, 2011Assignee: Hitachi, Ltd.Inventors: Takeshi Tokuyama, Kinya Nakatsu, Atsushi Kawabata
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Patent number: 7948078Abstract: A semiconductor device has a package structure provided with leads that are external connection terminals. A base substance is an island, and at least the surface thereof is formed of a conductive material. A semiconductor substrate is mounted on the surface of the base substance, and a ground potential is supplied from the surface of the base substance. A shunt capacitor is provided with an electrode pair of a first electrode and a second electrode formed in parallel, and mounted with the first electrode being electrically connected to the surface of the base substance. An internal bonding wire connects a pad provided on the semiconductor substrate for external connection, to the second electrode of the shunt capacitor. The lead is the external connection terminal of the semiconductor device. An external bonding wire connects the lead to the second electrode of the shunt capacitor.Type: GrantFiled: July 24, 2007Date of Patent: May 24, 2011Assignee: Rohm Co., Ltd.Inventor: Noriaki Hiraga
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Patent number: 7919804Abstract: An improved technique for power distribution for use by high speed integrated circuit devices. A mixture of high dielectric constant, Er and low Er materials are used in a dielectric layer sandwiched between the voltage and ground planes of a printed circuit board that is used to fixture one or more integrated circuit devices. The low Er material is used in an area contained by the location of the integrated circuit device and its corresponding decoupling capacitors located nearby. High Er material is used in areas between the regions of low Er material. The low Er material improves that speed at which current from an adjoining decoupling capacitor can propagate to a power pin of the integrated circuit device. The high Er material mitigates cross-coupling of noise between the low Er regions.Type: GrantFiled: December 1, 2006Date of Patent: April 5, 2011Assignee: Oracle America, Inc.Inventors: Kevin Horn, Forest Dillinger, Otto Richard Buhler, Karl Sauter
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Patent number: 7818704Abstract: The present invention is directed to a capacitive decoupling module and method for an integrated circuit that features providing multiple capacitive elements to decouple the power rails from the integrated circuit. The multiple capacitive elements are spaced-apart, along a first direction, from the integrated circuit. A first set of capacitive elements is closer to the integrated circuit than a second set of capacitive elements. The first set has a smaller capacitance than the second set.Type: GrantFiled: May 16, 2007Date of Patent: October 19, 2010Assignee: Altera CorporationInventors: Andrew E. Oishei, Gregory Moore
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Patent number: 7808797Abstract: A microelectronic substrate, a method of forming the same, and a system including the same. The microelectronic substrate comprises: a conductive layer; a spacer layer disposed onto the conductive dielectric layer; a dielectric build-up layer disposed onto the spacer layer, the spacer layer being made of a material that has a lower shrinkage than a material of the embedding dielectric-build-up layer during curing, and a higher viscosity than a material of the embedding dielectric build-up layer in its pre-cure form and during curing; and active or passive microelectronic components embedded within the dielectric build-up layer.Type: GrantFiled: December 11, 2006Date of Patent: October 5, 2010Assignee: Intel CorporationInventors: Islam Salama, Huankiat Seh
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Patent number: 7795728Abstract: An electronic component includes a multi-layer substrate having an upper side and under side, and at least one integrated impedance converter. The electronic component also includes at least one chip component having external contacts. The at least one chip component is disposed on the upper side of the multi-layer substrate, and is electrically connected to the at least one integrated impedance converter.Type: GrantFiled: May 7, 2003Date of Patent: September 14, 2010Assignee: Epcos AGInventor: Andreas Przadka
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Patent number: 7684204Abstract: A circuit board including: a substrate having a mounting area for mounting a vertical multilayer chip capacitor having first and second external electrodes of a first polarity and a third external electrode of a second polarity; first to third pads arranged on the mounting area, the first and second pads having the first polarity and disposed separately from each other on the mounting area, the third pad having the second polarity and disposed between the first and second pads to be connected to the third external electrode; at least one first via formed in the substrate and connected to the first pad; at least one second via formed in the substrate and connected to the second pad; and a plurality of third vias formed in the substrate and connected to the third pad.Type: GrantFiled: June 6, 2008Date of Patent: March 23, 2010Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Byoung Hwa Lee, Sung Kwon Wi, Hae Suk Chung, Dong Seok Park, Sang Soo Park, Min Cheol Park
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Patent number: 7656670Abstract: An electronic ballast with remote capacitor placement includes a first housing (34); a second housing (36); an AC/DC converter (22); a DC bus (24) operably connected to the AC/DC converter (22); a lamp driver (26) operably connected to the DC bus (24); and a storage capacitor (32) connected to the DC bus (24) with capacitor wires (30). The AC/DC converter (22), the DC bus (24), and the lamp driver (26) are disposed in the first housing (34); the storage capacitor (32) is disposed in the second housing (36); and the first housing (34) is thermally isolated and physically separated from the second housing (36).Type: GrantFiled: November 3, 2005Date of Patent: February 2, 2010Assignee: Koninklijke Philips Electronics, N.V.Inventors: Seymour Perkins, III, Jeffrey Lord, Subramanian Muthu, Bernd Clauberg
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Patent number: 7642131Abstract: An integrated circuit module, decoupling capacitor assembly and method are disclosed. The integrated circuit module includes a substrate and integrated circuit die mounted on the substrate and having die pads and an exposed surface opposite from the substrate. A plurality of substrate bonding pads are positioned on the substrate adjacent the integrated circuit die. A decoupling capacitor assembly is mounted on each integrated circuit die and includes a capacitor carrier secured onto the exposed surface of the integrated circuit die and a decoupling capacitor carried by the capacitor carrier. A wire bond extends from the decoupling capacitor assembly to a die pad and from a die pad to a substrate bonding pad.Type: GrantFiled: November 8, 2006Date of Patent: January 5, 2010Assignee: Harris CorporationInventors: Robert S. Vinson, Joseph B. Brief, Donald J. Beck, Gregory M. Jandzio
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Publication number: 20090073664Abstract: A decoupling capacitor/integrated circuit assembly including: an integrated circuit assembly comprising a carrier containing an integrated circuit, the carrier comprising connectors on a base thereof defining a space on the base having no connectors, the connectors providing an electrical connection to the integrated circuit, one of the connectors designated as a power connector and another of the connectors designated as a ground connector; and a decoupling capacitor provided in the space on the base of the carrier and electrically connected to the power and ground connectors, wherein the decoupling capacitor is sized to fit between the integrated circuit assembly and a structure to which the integrated circuit assembly is to be connected.Type: ApplicationFiled: September 18, 2007Publication date: March 19, 2009Applicant: Research In Motion LimitedInventor: Lyall WINGER
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Patent number: 7489035Abstract: A semiconductor package features a ring-shaped silicon decoupling capacitor that reduces simultaneous switching noise. The decoupling capacitor is fabricated on a substrate from silicon using a wafer fabrication process and takes the form of an annular capacitive structure that extends around a periphery of a substrate-mounted integrated circuit (IC). The decoupling capacitor has a reduced thickness on or below a chip level and takes the place of a conventional power/ground ring. Therefore, the decoupling capacitor can be disposed within the package without increasing the thickness and the size of the package. The decoupling capacitor may be coupled to various power pins, allowing optimum wire bonding, shortened electrical connections, and reduced inductance. Bonding wires connected to the decoupling capacitor have higher specific resistance, lowering the peak of the resonance frequency and thereby reducing simultaneous switching noise.Type: GrantFiled: October 25, 2005Date of Patent: February 10, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Eun-Seok Song, Hee-Seok Lee
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Patent number: 7490189Abstract: A switch contains a first semiconductor die, which is configured to receive signals on a plurality of input ports and to output the signals on a plurality of output ports. The first semiconductor die is further configured to selectively couple the signals between the input and output ports using a plurality of switching elements in accordance with a set of control signals, which correspond to a configuration of the switch. During this process, a plurality of proximity connectors, proximate to a surface of the semiconductor die, are configured to communicate the signals by capacitive coupling.Type: GrantFiled: June 14, 2006Date of Patent: February 10, 2009Assignee: Sun Microsystems, Inc.Inventors: Hans Eberle, Nils Gura, Wladyslaw Olesinski
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Patent number: 7455532Abstract: An electronic component pin connector comprising a non-conductive housing with a substrate end and an electronic component connection end, the housing comprising one or more electrical contacts, the or each electrical contact extending from the substrate end to the component connection end to provide one or more electrical contact points to a substrate at the substrate and one or more electrical contact points for a electronic component at the component connection end, the housing comprising a filter aperture extending from the component connection end to the substrate end, the aperture dimensioned to house one or more filters in an electrically connected position to provide filtering of signalling between a substrate connected at the substrate end and a electronic component connected at the component connection end.Type: GrantFiled: January 18, 2006Date of Patent: November 25, 2008Assignee: Nokia CorporationInventors: Timo T. Laitinen, Matti Uusimäki
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Patent number: 7453360Abstract: An identification carrier is disclosed. In one embodiment, the identification data carrier, includes a carrier substrate, having an electronic chip fitted on and/or in the carrier substrate, and having a transmitting/receiving antenna formed on and/or in the carrier substrate and serving for transmitting and for receiving electromagnetic radiation, and having a first capacitance, the chip being capacitively coupled to the transmitting/receiving antenna by means of the first capacitance.Type: GrantFiled: July 15, 2005Date of Patent: November 18, 2008Assignee: Infineon Technologies AGInventor: Rupert Glaser
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Patent number: 7432593Abstract: A semiconductor package assembly and method for electrically isolating modules, having a capacitor within the semiconductor package assembly. The package assembly and method are suitable for electrically isolating modules according to IEEE 1394.Type: GrantFiled: January 20, 2005Date of Patent: October 7, 2008Assignee: Micron Technology, Inc.Inventors: Sion C. Quinlan, Tim J. Bales
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Patent number: 7414299Abstract: A semiconductor package assembly and method for electrically isolating modules, having a capacitor within the semiconductor package assembly. The package assembly and method are suitable for electrically isolating modules according to IEEE 1394.Type: GrantFiled: January 20, 2005Date of Patent: August 19, 2008Assignee: Micron Technology, Inc.Inventors: Sion C. Quinlan, Tim J. Bales
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Patent number: 7355265Abstract: A semiconductor integrated circuit comprising a power supply wiring and a ground wiring and a decoupling capacitor formed between the power supply wiring and the ground wiring, wherein at least one electrode of the decoupling capacitor consists of a shield layer formed in a plane shape on a semiconductor substrate, and the shield layer is electrically connected directly to the semiconductor substrate and is fixed to a power supply potential or the ground potential.Type: GrantFiled: September 25, 2003Date of Patent: April 8, 2008Assignee: NEC CorporationInventor: Yasushi Kinoshita
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Patent number: 7301217Abstract: A thin-dielectric unit capacitor is disclosed having a first node coupled to a first circuit connection point and a second node coupled to a second circuit connection point. It further contains a first and second thin-dielectric capacitors connected in series between the first and second nodes, wherein a thickness of a gate dielectric for each thin-dielectric capacitor is less than 50 angstroms.Type: GrantFiled: November 19, 2004Date of Patent: November 27, 2007Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Shine Chien Chung
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Patent number: 7197348Abstract: A mobile phone with an interchangeable housing. The mobile phone includes a body, a front housing, a rear cover, a battery cover, and a battery pack. The body includes an engaging member. The front housing is detachably disposed on the body via the engaging member. The rear cover is detachably disposed on the body via the engaging member. The battery cover is detachably disposed on the body. The body is covered by the front housing, the rear cover, and the battery cover. The battery pack is disposed on the body, and includes a projecting portion. The projecting portion is abutted by the engaging member so as to move the engaging member.Type: GrantFiled: January 20, 2004Date of Patent: March 27, 2007Assignee: BENQ CorporationInventor: Long-Jyh Pan
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Patent number: 7177158Abstract: A press-activated electronic component discharging facilitating apparatus is proposed, which is designed for use with a battery-powered electronic component, such as a CMOS (Complementary Metal Oxide Semiconductor) memory unit installed on a computer motherboard, for providing the CMOS memory unit with a user-operated press-activated discharging facilitating function, and which is characterized by the capability of allowing the user to facilitate the discharging of the CMOS memory unit simply by pressing the battery cell used to power the CMOS memory unit, without having to dismount the battery cell from the motherboard and flip hardware jumpers as in the case of prior art. This feature allows the discharging process of the CMOS memory to be carried out more conveniently and efficiently.Type: GrantFiled: February 28, 2006Date of Patent: February 13, 2007Assignee: Inventec CorporationInventors: Zi-Gui Luo, Fred Chen
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Patent number: 7148554Abstract: An electronic component arrangement includes a discrete electronic component having first and second terminals and a centre-exposed pad. A substrate has a first electrical conductor electrically connected to the first terminal, a second electrical conductor electrically connected to the second terminal, and a third electrical conductor. A thermally conductive element is in direct thermal communication with both the centre-exposed pad of the electronic component and the third electrical conductor of the substrate.Type: GrantFiled: December 16, 2004Date of Patent: December 12, 2006Assignee: Delphi Technologies, Inc.Inventors: Chih Kai Nah, Morris D Stillabower, Binghua Pan, Sim Ying Yong, Przemyslaw Gromala
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Patent number: 7145233Abstract: An integrated circuit module, decoupling capacitor assembly and method are disclosed. The integrated circuit module includes a substrate and integrated circuit die mounted on the substrate and having die pads and an exposed surface opposite from the substrate. A plurality of substrate bonding pads are positioned on the substrate adjacent the integrated circuit die. A decoupling capacitor assembly is mounted on each integrated circuit die and includes a capacitor carrier secured onto the exposed surface of the integrated circuit die and a decoupling capacitor carried by the capacitor carrier. A wire bond extends from the decoupling capacitor assembly to a die pad and from a die pad to a substrate bonding pad.Type: GrantFiled: October 30, 2003Date of Patent: December 5, 2006Assignee: Harris CorporationInventors: Robert S. Vinson, Joseph B. Brief, Donald J. Beck, Gregory M. Jandzio
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Patent number: 7123118Abstract: Systems and methods are taught for blocking the propagation of electromagnetic waves in parallel-plate waveguide (PPW) structures. Periodic arrays of resonant vias are used to create broadband high frequency stop bands in the PPW, while permitting DC and low frequency waves to propagate. Particular embodiments include clusters of small vias that effectively function as one large via, thereby increasing stop band bandwidth and maximizing parallel plate capacitance. Cluster vias can be configured to additionally provide a shielded and impedance matched route within the interior area of the cluster through which signal vias can connect transmission lines disposed in planes lying above and below the PPW. Important applications include electromagnetic noise reduction in layered electronic devices such as circuit boards, ceramic modules, and semiconductor chips.Type: GrantFiled: April 19, 2004Date of Patent: October 17, 2006Assignee: Wemtec, Inc.Inventor: William E. McKinzie, III
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Patent number: 7091607Abstract: A semiconductor package includes a substrate, a chip, and at least one capacitor. The chip adheres to the substrate and has an active surface, a grounding area disposed on the active surface and at least one power pad mounted on the active surface. The capacitor is disposed on the grounding area of the chip and has a power end and a grounding end electrically connected to the grounding area. At least one bonding wire electrically connects the power end of the capacitor to the power pad.Type: GrantFiled: December 7, 2004Date of Patent: August 15, 2006Assignee: Advanced Semiconductor Engineering Inc.Inventor: Sheng Tsung Liu
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Patent number: 7053466Abstract: A contact-less high-speed signaling interface and method provide for the communication of high-speed signals across an interface, such as a die-substrate interface or die-die interface. The interface includes a transmission-line structure disposed on a dielectric medium to carry a high-speed forward incident signal, and another transmission-line structure disposed on another dielectric medium and substantially aligned with the other transmission-line structure to generate a coupled high-speed signal in a direction opposite to the incident signal.Type: GrantFiled: December 17, 2002Date of Patent: May 30, 2006Assignee: Intel CorporationInventors: Victor Prokoflev, Henning Braunisch
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Patent number: 7039374Abstract: A transmitting and amplifying unit for a wireless communication device. The transmitting and amplifying unit includes a C-shaped frame having an upper plate having a first cutout, a lower plate having a second cutout aligned with the first cutout, and a side plate connecting the upper plate and the lower plate; a main amplifier unit fixed to the lower plate and having a concentrated heating portion; and a subamplifier unit fixed to the upper plate. The transmitting and amplifying unit further includes a radiating fin unit mounted on the concentrated heating portion of the main amplifier unit and extending upward through the first cutout of the lower plate and the second cutout of the upper plate. The radiating fin unit has an upper end fixed to the subamplifier unit.Type: GrantFiled: September 14, 2001Date of Patent: May 2, 2006Assignee: Fujitsu LimitedInventors: Yuuji Hasegawa, Kazuo Hirafuji, Toshimitsu Kobayashi, Manabu Miyamoto
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Patent number: 6995747Abstract: Capacitive proximity sensing is carried out by detecting a relative change in the capacitance of a “scoop” capacitor formed by a conductor and a surrounding ground plane. The conductor may be a plate provided in the form of an adhesive label printed with conductive ink. Charge is transferred between the “scoop” capacitor and a relatively large “bucket” capacitor, and a voltage of the bucket capacitor is applied to an input threshold switch. A state transition (e.g., from low to high, or high to low) of the input threshold switch is detected and a value (TouchVal) indicative of a number of cycles of charge transfer required to reach the state transition is determined. The presence or absence of an object or body portion in close proximity to or contact with a device can be determined by comparing TouchVal with a predetermined threshold value (TouchOff). TouchOff can be adjusted to take into account environmentally induced (non-touch related) changes in the capacitance of the scoop capacitor.Type: GrantFiled: November 5, 2004Date of Patent: February 7, 2006Assignee: Microsoft CorporationInventors: Mark W. Casebolt, Gino S. Garcia
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Patent number: 6974909Abstract: An IC module includes a lead frame having terminals that are to be connected to an antenna coil of an IC card, and an IC chip and multilayer chip capacitors for tuning mounted on the lead frame and encapsulated by a resin. The multilayer chip capacitors are mounted in grooves on the lead frame.Type: GrantFiled: May 23, 2003Date of Patent: December 13, 2005Assignee: Sony CorporationInventors: Junichi Tanaka, Hiroyuki Takubo, Shigenobu Abe