Solder Connection Patents (Class 361/743)
  • Patent number: 6608384
    Abstract: A semiconductor device includes a bonding-structure for electrically and mechanically bonding a solder ball to the electrode pad. The bonding-structure includes flexible arms that are connected to a common supporting layer that allows a relative displacement of the solder ball in relation to the semiconductor chip. The arms extending in one direction are supported by one supporting layer and the arms extending in an opposite direction are supported by another supporting layer.
    Type: Grant
    Filed: August 3, 2001
    Date of Patent: August 19, 2003
    Assignee: Nec Corporation
    Inventor: Seiya Isozaki
  • Patent number: 6603663
    Abstract: The invention relates to an electronic unit having a mounting board (4) and electronic components (1-3) mounted on it, with the mounting board (4) having metal webs (41) which are embedded in an electrically insulating material (40), the metal webs (41) having a first side (411), which is in the form of a contact surface for making contact with the electronic components (1-3) and having a second side (412) facing away from this. According to the invention, cutout(s) are arranged in the electrically insulating material (40), via which the second side (412) of each metal web (41) is accessible for a voltage or current measurement apparatus.
    Type: Grant
    Filed: September 24, 2001
    Date of Patent: August 5, 2003
    Assignee: Patent-Treuhand-Gesellscahft fuer Elektrische Gluehlampen mbH
    Inventor: Matthias Burkhardt
  • Patent number: 6594152
    Abstract: A first printed circuit board has a contact area, and a second printed circuit board has a contact area. An electrically conductive band is to couple the contact area of the first printed circuit board to the contact area of the second printed circuit board. The conductive band may be selected from the group consisting essentially of a band formed from solder, a band coupled by a weld, a band coupled by a wire bond, a band comprising conductive adhesive, a band comprising conductive film, a band comprising conductive tape, and a band comprising conductive rope. The conductive band may couple the first printed circuit board and the second printed circuit board in a substantially coplanar position.
    Type: Grant
    Filed: September 30, 1999
    Date of Patent: July 15, 2003
    Assignee: Intel Corporation
    Inventor: David Dent
  • Publication number: 20030101584
    Abstract: A bump used for electric contact with an electric part is formed by arranging on a conductor a conductive material including a substantially same electric characteristic as the bump by fusing, and forming the arranged conductive material into a desired shape by die pressing with a bump forming die in which a recess having a given shape is defined.
    Type: Application
    Filed: January 16, 2003
    Publication date: June 5, 2003
    Inventor: Shigeru Matsumura
  • Publication number: 20030103336
    Abstract: The packaging architecture for a multiple array transceiver using a flexible cable and stiffener for customer attachment of the present invention provides a 90 degree transition between an optical signal input/output at a communication chassis bulkhead, and an provides for a ball grid array attachment to a common host board. The packaging architecture system comprises a forward vertical carrier having an optical converter; a stiffener block, the stiffener block oriented about 90 degrees from the forward vertical carrier; and a flexible cable electrically connecting the optical converter of the forward vertical carrier to a solder ball array aligned with the stiffener block. The multiple array transceiver makes the 90 degree transition within a narrow gap established by industry and manufacturing standards.
    Type: Application
    Filed: December 5, 2001
    Publication date: June 5, 2003
    Applicant: International Business Machines Corporation
    Inventors: Johnny R. Brezina, Brian M. Kerrigan, Gerald D. Malagrino, James R. Moon
  • Patent number: 6574113
    Abstract: An electronic package which includes first and second circuitized substrates secured together by a solder member which includes a first contact portion for attachment to a printed circuit board and a second contact portion used to bond the two substrates together (e.g., to form a multi-chip module). Semiconductor chips can be positioned on and electrically coupled to the formed solder members.
    Type: Grant
    Filed: January 17, 2001
    Date of Patent: June 3, 2003
    Assignee: International Business Machines Corporation
    Inventors: Gregg J. Armezzani, Matthew A. Heller
  • Patent number: 6552277
    Abstract: The invention is directed to techniques for forming a connection between a pin and a circuit board using a pin having protruding portions and grooved surfaces that extend between the protruding portions. The protruding portions (i) prevent the pin from inadvertently slipping through a via of the circuit board, and (ii) maintains the pin's proper position relative to the circuit board via. The grooved surfaces enable gas to vent from a cavity in the via during the solder process thus enabling solder to flow within the via and form a reliable and robust solder joint between the pin and the circuit board via. In one arrangement, the protruding portions and grooved surfaces are at both ends of the pin enabling the pin to be soldered between two circuit board sections. In one arrangement, the pin is simultaneously soldered to both circuit board sections. In another arrangement, the pin is initially soldered to one circuit board section, and subsequently soldered to another circuit board section.
    Type: Grant
    Filed: September 8, 2000
    Date of Patent: April 22, 2003
    Assignee: EMC Corporation
    Inventor: Stuart D. Downes
  • Patent number: 6496381
    Abstract: A contact arrangement for an electrically contactable module that is arranged on a card-shaped carrier, having a first contact bank with a plurality of contact areas, of which at least one is disposed outside of a predefined region. A second contact bank is provided having at least one contact area within the predefined region, and the contact areas of the first contact bank that are arranged outside of the predefined region are in each case electrically connected to contact areas of the second contact bank. Consequently, for example, both chip cards according to ISO 7816 and multimedia card modules can be evaluated by a chip-card reader provided for evaluating ISO-7816 chip cards. At the same time, the ability of the MMC modules to be evaluated by an MMC-module reader provided for that purpose is retained.
    Type: Grant
    Filed: March 14, 2001
    Date of Patent: December 17, 2002
    Assignee: Robert Bosch GmbH
    Inventor: Klaus-Erwin Groeger
  • Patent number: 6493238
    Abstract: A method and system of utilizing inexpensively manufactured, electrically conductive and mechanically compliant disks to interconnect an area grid array (“AGA”) chip to a printed wiring board. The conductive disk shaped leads are stamped from a thin sheet of conductive material. To increase solderability and protect the disk surface, the disks can be plated with tin or an equivalent material. Each disk is positioned tangent to the surface of an AGA chip in a specific orientation. One edge of each disk is electrically connected and mechanically secured to a corresponding conductive pad located on the surface of the AGA chip. The opposite edge of each conductive disk is positioned to align with a corresponding conductive surface pad on a printed wiring board (“PWB”). Each opposite edge is electrically connected and mechanically secured to the surface of the PWB, thereby establishing a compliant electrical connection between the AGA chip and the PWB.
    Type: Grant
    Filed: April 30, 2001
    Date of Patent: December 10, 2002
    Assignee: General Dynamics Information Systems, Inc.
    Inventor: Deepak K. Pai
  • Patent number: 6493240
    Abstract: The present invention is an interposer for electrically coupling a microcard with a mother board. The interposer includes a frame which is interposed between the microcard and the motherboard, electrically connecting the microcard and the motherboard by means of plated via-holes. The substrate is organic and a plurality of chips are mounted on both sides of the substrate. On the opposite sides of the interposer are pluralities of metal pads which are coupled by metallized via holes, the pads in turn connected to the chips, thereby coupling chips or cards on one side of the interposer to chips or boards on the other side. Electrical connection between the chips on the top side of the substrate and the metal pads on the lower side of the substrate is provided by the metallized via holes.
    Type: Grant
    Filed: May 17, 2001
    Date of Patent: December 10, 2002
    Assignee: International Business Machines Corporation
    Inventors: Patrizio Broglia, Francesco Garbelli, Alberto Monti
  • Patent number: 6465747
    Abstract: A microelectronic assembly includes a component having one or more conductive pads, with each conductive pad having a plurality of solder-wettable strips extending outwardly away from a center, the solder wettable strips being bounded by non solder-wettable material. The microelectronic assembly also includes a composite conductive element positioned atop at least one of the conductive pads, the composite conductive element including a solid conductive core and a layer of solder material overlying the solid conductive core, the solid conductive core having a higher melting temperature than the layer of solder material.
    Type: Grant
    Filed: September 13, 2001
    Date of Patent: October 15, 2002
    Assignee: Tessera, Inc.
    Inventors: Thomas H. DiStefano, Joseph Fjelstad
  • Publication number: 20020126459
    Abstract: A stackable microcircuit layer formed from a plastic encapsulated microcircuit (PEM) and method of making the same is disclosed. The method involves the steps of starting with a commercially available PEM (e.g. a plastic Thin Small Outline Package or TSOP) that contains a microcircuit or die within an encapsulant and modifying the PEM to expose conductive members that are electrically connected to the microcircuit's bond pads. In the case of a TSOP, the preferred modifying step is accomplished by top grinding the TSOP in order to remove the lead frame that was secured above the die and encapsulated along with it in the TSOP. Next, reroute metallization is applied in order to connect the conductive members that were exposed by the top grinding, to an edge of the modified PEM. Finally, if appropriate, the modified PEM is thinned through backside grinding and diced to a desired area, in order to provide a stackable microcircuit layer that may form a part of a dense electronic package.
    Type: Application
    Filed: May 10, 2002
    Publication date: September 12, 2002
    Inventors: Douglas M. Albert, Keith D. Gann
  • Patent number: 6442033
    Abstract: Resistance and parasitic inductance resulting from interconnection of semiconductor chips in power modules are reduced to negligible levels by a robust structure which completely avoids use of wire bonds through use of ball bonding and flip-chip manufacturing processes, possibly in combination with chip scale packaging and hourglass shaped stacked solder bumps of increased compliance and controlled height/shape. Turn-off voltage overshoot is reduced to about one-half or less than a comparable wire bond packaged power module. Hourglass shaped solder bumps provide increased compliance and reliability over much increased numbers of thermal cycles over wide temperature excursions.
    Type: Grant
    Filed: September 13, 2000
    Date of Patent: August 27, 2002
    Assignee: Virginia Tech Intellectual Properties, Inc.
    Inventors: Xingsheng Liu, Guo-Quan Lu
  • Patent number: 6437989
    Abstract: This circuit board contains electronic components having electrical contacts. At least one of the electrical contacts is initially glued to the circuit board using a conductive adhesive and at least one of the electrical contacts is connected to the circuit board by soldering. The circuit board is suitable for fast mechanical mass production. Further a method for the manufacture of the connection between the circuit board and the electronic components is disclosed, in which a solder is applied to soldering points and a conductive adhesive is applied to adhesive points. The circuit board with the components is then placed in a furnace to connect the components to the circuit board.
    Type: Grant
    Filed: May 24, 2000
    Date of Patent: August 20, 2002
    Assignee: Endress + Hauser GmbH + Co.
    Inventors: Sergej Lopatin, Dietmar Birgel, Karl-Peter Hauptvogel
  • Patent number: 6424535
    Abstract: A plate-shaped ceramic circuit substrate (6), which is adapted to be vertically mounted on a mother board, has near a lower edge (7) thereof a series of contact areas (solder pads) (1) for contacting the circuit with terminals of the mother board. For improved solderability also in case of small contact area (1), these contact areas extend down as far as the lower edge (7), and there is provided one recess (2) each which constitutes a solder deposit (3) and which extends through the circuit substrate (6) and runs from the lower face side (5) of the circuit substrate (6) upwardly into the respective contact area (1).
    Type: Grant
    Filed: November 13, 2000
    Date of Patent: July 23, 2002
    Assignee: Tyco Electronics Logistics AG
    Inventors: Karl Rehnelt, Frank Templin
  • Patent number: 6407927
    Abstract: A method and connecting structure includes a first surface and a connection pad on said first surface, wherein, said first surface includes an opening adjacent to said connection pad, and wherein, upon sufficient stress, said opening forms a flap allowing a portion of said connection pad to separate from said first surface.
    Type: Grant
    Filed: August 31, 1999
    Date of Patent: June 18, 2002
    Assignee: International Business Machines Corporation
    Inventor: Benjamin V. Fasano
  • Patent number: 6399889
    Abstract: A head interconnect circuit for connecting transducer elements of a data head to drive circuitry including an alignment finger on a lead tip for aligning leads relative to connectors or solder pads for electrically connecting heads to drive circuitry. A method for connecting a head interconnect circuit to a printed circuit supported on an head actuator including aligning an alignment finger on the lead tip with a printed surface of a drive circuit for soldering leads on the lead tip to solder pads or connectors on the drive circuit.
    Type: Grant
    Filed: September 13, 1999
    Date of Patent: June 4, 2002
    Assignee: Seagate Technology LLC
    Inventors: Kurt J. Korkowski, Kenneth R. Fastner, Adam K. Himes, Gregory P. Myers, Andrew R. Motzko
  • Patent number: 6377468
    Abstract: Circuit elements of surface-mounting type such as MOSFETs etc. are mounted on a circuit board by soldering. The circuit board is retained slantingly by a base so that any one of the MOSFET falls out by its self-weight when the solder melts due to an abnormal heat generation of the MOSFET. The falling of the MOSFET is stopped by a stopper member, and then the MOSFET becomes in an electrically open state and retained at the stopped position in consequence of the subsequent cooling of the solder. Accordingly, even if one or more of the MOSFETs cause the abnormal heat generation, the continuous heat generation of the MOSFET is stopped and also the other circuit elements are prevented from being short-circuited.
    Type: Grant
    Filed: June 15, 2000
    Date of Patent: April 23, 2002
    Assignees: ANDEN Co., Ltd., DENSO Corporation
    Inventors: Hideyuki Ohtani, Fukuo Ishikawa, Hideki Kabune, Hiroshi Hattori
  • Patent number: 6373714
    Abstract: The present invention is to provide a surface mounting part, capable of corresponding to high density mounting of a mother board and capable of achieving a small size, to be mounted on a mother board by reflow. Electronic parts are mounted on both sides of a printed board. Terminal electrodes of the electronic parts mounted on the rear side are provided as terminals for connecting with the mother board.
    Type: Grant
    Filed: October 5, 1999
    Date of Patent: April 16, 2002
    Assignee: TDK Corporation
    Inventors: Kazuo Kudoh, Masashi Katsumata
  • Patent number: 6372998
    Abstract: An electrical component connecting structure for an electrical component having a terminal is disclosed. The electrical component connecting structure comprises an insulating plate and a bus bar. The insulating plate comprises a first surface side for mounting the electrical component thereon and a second surface side. The insulating plate further comprises an opening portion formed at a predetermined position and defined by an inner wall extending from the first surface side to the second surface side. The bus bar comprises a pattern portion, an insertion plate portion, and a connecting plate portion. The insertion plate portion extends from the pattern portion to the second surface side of the insulating plate along at least part of the inner wall of the opening portion. The connection plate portion extends from the insertion plate portion so as to close the opening portion on the second surface side of the insulating plate.
    Type: Grant
    Filed: October 11, 2000
    Date of Patent: April 16, 2002
    Assignee: Yazaki Corporation
    Inventors: Masataka Suzuki, Hiroyuki Ashiya, Yayoi Maki
  • Patent number: 6362436
    Abstract: Printed wiring board for a chip size scale package, which overcomes the poor adhesion of solder balls to a base material which poor adhesion is caused by a recent decrease in the size of the solder balls, and in the chip size scale package. The distortion of the printed wiring board is decreased and the distortion of a semiconductor plastic package formed by mounting a semiconductor chip on the printed wiring board by wire bonding or flip chip bonding is decreased. The board has at least two blind via holes in one solder-balls-fixing pad.
    Type: Grant
    Filed: February 4, 2000
    Date of Patent: March 26, 2002
    Assignee: Mitsubishi Gas Chemical Company, Inc.
    Inventors: Hidenori Kimbara, Nobuyuki Ikeguchi, Katsuji Komatsu
  • Patent number: 6362437
    Abstract: A mounting structure of an integrated circuit device includes an integrated circuit device, a mounting board, a first solder bump, and a second solder bump. The integrated circuit device is mounted on the mounting board. The interposer board is interposed between the integrated circuit device and the mounting board. The first solder bump electrically connects the interposer board to the mounting board. The first solder bump is provided between the interposer board and the mounting board. The second solder bump buffers a stress. The second solder bump is provided between the interposer board and the mounting board.
    Type: Grant
    Filed: June 19, 2000
    Date of Patent: March 26, 2002
    Assignee: NEC Corporation
    Inventor: Osamu Arai
  • Patent number: 6359790
    Abstract: Semiconductor chips are mounted in flip-chip technology on the multilayer wiring of the silicon carrier substrate. The underside of the substrate is provided with soldering contacts in the form of solder agglomerations forming a ball grid array (BGA). The underside is structured such that a cavity which narrows in the shape of a funnel from the underside up to the lowest conductor track plane is formed for each soldering contact. The cavities are each filled by the respective solder agglomeration and the solder agglomeration itself makes contact with the multilayer wiring.
    Type: Grant
    Filed: July 3, 2000
    Date of Patent: March 19, 2002
    Assignee: Infineon Technologies AG
    Inventor: Georg Meyer-Berg
  • Publication number: 20020029905
    Abstract: A blanking plate is attached to the bottom surfaces of a split board and a remaining board, which are separated from one bare board. After depositing solder paste on a back electrode of the split board, a solder ball is attached on the solder paste. The split board is then heated to melt the solder ball. The molten solder flows along the back electrode and an edge electrode into a through-hole. A portion of the molten solder swells out of the bottom surface of the bare board, and solidifies and bonds to the back electrode and the edge electrode.
    Type: Application
    Filed: April 26, 2001
    Publication date: March 14, 2002
    Inventors: Masanobu Okada, Kazuyoshi Nakaya, Hiroyuki Nakaji, Hirofumi Doi, Iku Nagai, Junichi Nakasone
  • Patent number: 6344781
    Abstract: An electrically conductive wire wound into a conical coil 1 with leads from the small and large ends of the coil. The coil is filled with fine-grained magnetic material 11, and is mounted in a thin-walled, electrically non-conductive carrier 21 designed for precise automated assembly onto a circuit board 15. The wire leads are plastic-welded onto the carrier, and no metallic pads are used, greatly increasing the effective bandwidth of the choke. The small end 4 of the coil is positioned precisely on a micro-strip 17 on the circuit board. Attachment of the wire lead from the small end of the coil to the microstrip is done with minimum lead length and minimum conductive material for the highest possible frequency response. Precise coil positioning, minimal lead length, and a totally non-conductive carrier virtually eliminates electrical reflections and resonances to yield a broadband choke with exceptional frequency range.
    Type: Grant
    Filed: April 14, 2001
    Date of Patent: February 5, 2002
    Inventor: Stephen Amram Slenker
  • Patent number: 6324754
    Abstract: Solder pads for microelectronic connections are formed with a set of solder-wettable strips extending radially outwardly from a central point. A solid core solder ball is positioned on each pad and reflowed. The pad configuration helps to center the solder ball and keeps the solder ball down in the desired position thereby minimizing variations in height of the resulting solder bumps. Also, the solder pad may include non-wettable surfaces defined by a non-wettable metal, a metal compound or a dielectric material. The non-wettable areas on the pad confine the solder and avoid the need for a separate solder mask.
    Type: Grant
    Filed: March 25, 1998
    Date of Patent: December 4, 2001
    Assignee: Tessera, Inc.
    Inventors: Thomas H. DiStefano, Joseph Fjelstad
  • Patent number: 6294742
    Abstract: A surface mount solder pad that is adapted to function as a heat sink for an electronic component soldered to the pad. Included is a printed wiring board having solder pads disposed on its surface that are adapted for soldering to leads of surface mount components. The solder pads are electrically interconnected by conductive traces also disposed on the surface. At least one of the solder pads has an enhanced surface area that is selected larger than necessary for the soldering, and that is selected sufficiently large so as to sink enough heat generated by one of the surface mount components to provide for its proper operation.
    Type: Grant
    Filed: July 27, 1999
    Date of Patent: September 25, 2001
    Assignee: Agilent Technologies, Inc.
    Inventor: Ted B Ziemkowski
  • Patent number: 6295206
    Abstract: A memory card is disclosed which has a card body (2) having a concavity (9) formed at the forward end thereof in the inserting direction and in which terminals (5) are disposed and projections (10) are formed between the terminals (5) to prevent the terminals (5) from being touched or accessed from outside. A receptacle for the memory card is also disclosed. The memory card has a simple structure designed to positively protect the terminals and easily let out dust or the like from inside, thereby permitting to assure a positive connection with the receptacle.
    Type: Grant
    Filed: January 18, 2000
    Date of Patent: September 25, 2001
    Assignee: Sony Corporation
    Inventors: Yoshio Kondo, Toshiharu Kobayashi, Takumi Okaue, Akira Sassa
  • Patent number: 6291894
    Abstract: A method for packaging a semiconductor device includes connecting a plurality of wire leads to a corresponding plurality of electrical connection pads on the semiconductor device, covering at least a portion of the semiconductor device and at least a portion of each of the wire leads with an encapsulating material, and removing a portion of the encapsulating material and a portion of each of the wire leads to form a packaged semiconductor device wherein each of the wire leads has an exposed portion only at an end. The invention also includes a packaged semiconductor device having an integrated circuit device with a plurality of electrical connection pads, a plurality of wire leads coupled to the plurality of electrical connection pads, and a covering of encapsulating material covering at least a portion of the integrated circuit device and covering each of the wire leads, wherein each of the wire leads has an exposed end.
    Type: Grant
    Filed: August 31, 1998
    Date of Patent: September 18, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Warren Farnworth, Larry Kinsman, Walter Moden
  • Publication number: 20010018987
    Abstract: An embodiment of the present invention is a method for wafer level IC packaging that includes the steps of: (a) forming compliant, conductive bumps on metalized bond pads or conductors; and (b) surrounding the compliant, conductive bumps in a supporting layer.
    Type: Application
    Filed: February 21, 2001
    Publication date: September 6, 2001
    Inventors: George Tzanavaras, Mihalis Michael
  • Patent number: 6243268
    Abstract: A cooling assembly for an integrated circuit chip module wherein an evaporator-cooled IC module mounted on a printed circuit board is enclosed within an insulated housing, and the area of the printed circuit board adjacent the cooled IC module is encapsulated in an insulated jacket.
    Type: Grant
    Filed: October 12, 1999
    Date of Patent: June 5, 2001
    Assignee: International Business Machines Corporation
    Inventors: Sukhvinder Kang, Howard Victor Mahaney, Jr., Roger R. Schmidt, Prabjit Singh
  • Patent number: 6208524
    Abstract: Electronic apparatus, battery powerable apparatus, and radio frequency communication devices are disclosed. In but one implementation, an electronic apparatus comprises a substrate having a component mounted thereto. An encapsulant mass is received over and adheres to the gasifiable component and to the substrate. An opening is formed through the substrate and extends to the encapsulant mass. In another considered implementation, an electronic apparatus comprises a substrate having a component mounted thereto, with the component comprising a lateral periphery. An encapsulant mass is received over and adheres to the gasifiable component and to the substrate. An opening extends through the substrate from a location proximate the component within a region bounded by the component lateral periphery to externally of the substrate.
    Type: Grant
    Filed: July 23, 1998
    Date of Patent: March 27, 2001
    Assignee: Micron Technology, Inc.
    Inventor: Mark E. Tuttle
  • Patent number: 6201350
    Abstract: In a discharge lamp lighting apparatus for a discharge lamp, each circuit component including a starter transformer is assembled to a bus bar casing, and a high voltage terminal of the starter transformer is connected to one end of a connecting terminal. The bus bar casing is adhesive-cemented to a metal base to which a HIC is attached. Then, a sealing resin fills the bus bar casing to seal the starter transformer and the HIC with the sealing resin. After the sealing resin solidifies, the other end of the connecting terminal and an output cable are connected, and subsequently a resin cover is assembled to the metal base. A shielding sheath covering the output cable is fixed to the bus bar casing by a clip. A ground connection part of the bus bar connectable to the ground side of an electric power source is shaped to protrude from the bus bar casing. The cover, the clip, the ground connection part and the base are ground-connected by a thread.
    Type: Grant
    Filed: November 1, 1999
    Date of Patent: March 13, 2001
    Assignee: Denso Corporation
    Inventors: Hiroaki Okuchi, Hiromi Hiramatsu, Yasutoshi Horii, Noboru Yamamoto
  • Patent number: 6191472
    Abstract: A semiconductor package substrate includes at least one insulative layer, at least two metal lines next to one another on a first side of the insulative layer, and a first metal layer on a second side of the insulative layer opposing the first side. An opening is formed in the first metal layer in an area between the metal lines. Two lands remain part of the first metal layer. The lands are located adjacent the opening and each land opposes a respective one of the metal lines located next to one another.
    Type: Grant
    Filed: January 5, 1999
    Date of Patent: February 20, 2001
    Assignee: Intel Corporation
    Inventor: Mohiuddin M. Mazumder
  • Patent number: 6184576
    Abstract: A packaging and interconnection for connecting a contact structure to an outer peripheral component with a short signal pass length to achieve a high frequency operation. The packaging and interconnection is formed of a contact structure made of conductive material and formed on a contact substrate through a photolithography process, a contact trace formed on the contact substrate and electrically connected to the contact structure at one end, and the other end of the contact trace is extended toward an edge of the contact substrate, a connection target provided at an outer periphery of the contact structure to be electrically connected with the other end of the contact trace, an elastomer provided under the contact substrate for allowing flexibility in the interconnection and packaging of the contact structure, and a support structure provided between for supporting the contact structure, the contact substrate and the elastomer.
    Type: Grant
    Filed: September 21, 1998
    Date of Patent: February 6, 2001
    Assignee: Advantest Corp.
    Inventors: Mark R. Jones, Theodore A. Khoury
  • Patent number: 6137690
    Abstract: An electronic assembly (10) comprises one or more electronic components (18) having solder terminations (20), and a printed circuit substrate (12) having printed circuit traces (14, 16), wherein at least one of the solder terminations of the one or more electronic components (18) and the printed circuit traces (14, 16) of the printed circuit substrate (12) has a secondary finish produced by application of an electrolessly deposited nickel film (26) containing phosphorus which is further plated with gold (28). An indium-tin-lead solder paste (22) is utilized in a soldering process to attached the one or more electronics components (18) to the printed circuit traces (14,16) on the printed circuit board (12), such that the indium-tin-lead solder (22) provides improved solder joint integrity with the secondary finish. The electronic components (18) include semiconductor devices such as ball grid arrays (1000) and flip-chip integrated circuits (1010).
    Type: Grant
    Filed: August 18, 1997
    Date of Patent: October 24, 2000
    Assignee: Motorola
    Inventors: Robert Thomas Carson, Arnold William Hogrefe, Frank Juskey
  • Patent number: 6133626
    Abstract: A multi-chip module (MCM) assembly has three stacked integrated circuit (IC) layers. The first IC layer is electrically flip-chip connected to a substrate. The back of the second IC layer may be glued to the back of the first IC layer, and the second and third IC layers are electrically flip-chip connected to each other. In one embodiment, the third IC layer is electrically connected to the substrate through a vertical interconnect element for high circuit density. In another, the second IC layer is electrically connected to the substrate using wire bonding for greater post-fabrication customization flexibility. In still another embodiment, the MCM assembly comprises two stacked IC layers where the second IC layer is electrically flip-chip connected to the first IC layer and the second layer is electrically connected to the substrate through a vertical interconnect element.
    Type: Grant
    Filed: September 24, 1998
    Date of Patent: October 17, 2000
    Assignee: Gennum Corporation
    Inventors: Robert E. Hawke, Atin J. Patel, Sukhminder S. Binapal, Charles Divita, Lynn McNeil, Thomas G. Fletcher
  • Patent number: 6075708
    Abstract: A partly bent electric circuit is formed including a main circuit substrate in which electric parts such as IC are carried to form an electric circuit, a sub-circuit substrate in which electric parts such as LED which can be recognized from the surface of the set, and a ribbon form metal piece for electrically connecting the main circuit substrate with the sub-circuit substrate, so that, due to the metal piece being bent, the sub-circuit substrate is bent against the above main circuit substrate. As a result, there is obtained an electric circuit substrate wherein the main circuit substrate can be inserted in a narrow place and the sub-circuit substrate part provided with the predetermined parts can be bent to arrange the predetermined parts in an accurate place at a low cost using a low priced print substrate or the like.
    Type: Grant
    Filed: September 2, 1998
    Date of Patent: June 13, 2000
    Assignee: Rohm Co., Ltd.
    Inventor: Satoshi Nakamura
  • Patent number: 6010061
    Abstract: With the present invention, a reflow soldering method is provided for soldering a nonvertically approaching lead, which is part of a nonvertically approaching device (e.g, an edge connector), to a corresponding soldering surface (e.g., a pad on a circuit card) that includes solder. The soldering surface and solder are heated in an oven to melt the solder. While the solder is liquids, the nonvertically approaching lead is mated with the soldering surface as it is inserted into the solder. The soldering surface, solder, and nonvertically approaching lead are then cooled, and the solder solidifies to conductively mount the nonvertically approaching lead to the soldering surface.
    Type: Grant
    Filed: March 27, 1998
    Date of Patent: January 4, 2000
    Assignee: Micron Custom Manufacturing Services Inc.
    Inventor: David A. Howell
  • Patent number: 5996880
    Abstract: A memory module has DRAM chips mounted on both a front and a back surface but decoupling capacitors mounted on only the front surface. Each decoupling capacitor is for suppressing current spikes from a pair of DRAM chips. The pair of DRAM chips includes a first DRAM chip on the same surface as the capacitor and a second DRAM chip opposite the first DRAM chip on the back surface of the module. The first DRAM chip belongs to a first bank while the second DRAM chip belongs to a second bank. Two RAS signals are for controlling access to the two banks. Since only one bank is accessed at any time, and access causes current spikes, only one bank and only one DRAM chip in the pair of DRAM chips creates a current spike at any time. Thus a capacitor can be shared between the two DRAM chips in the pair. The shared capacitor can be mounted next to or under one of the DRAM chips, or formed within the multi-layer substrate itself.
    Type: Grant
    Filed: April 6, 1998
    Date of Patent: December 7, 1999
    Assignee: Ma Laboratories, Inc.
    Inventors: Tzu-Yih Chu, Abraham C. Ma
  • Patent number: 5941447
    Abstract: A processor module has a cache of SRAM chips mounted on both a back and a front surface but de-coupling capacitors mounted on only the back surface. Each de-coupling capacitor is for suppressing current spikes from a pair of SRAM chips. The pair of SRAM chips includes a first SRAM chip on the same surface as the capacitor and a second SRAM chip opposite the first SRAM chip on the front surface of the module. The first SRAM chip belongs to a first bank while the second SRAM chip belongs to a second bank. Two chip-enable signals control access to the two banks. Since only one bank is accessed at any time, and access causes current spikes, only one bank and only one SRAM chip in the pair of SRAM chips creates a current spike at any time. Thus, a capacitor can be shared between the two SRAM chips in the pair. The shared capacitor can be mounted next to or under one of the SRAM chips, or formed within the multi-layer substrate itself.
    Type: Grant
    Filed: September 28, 1998
    Date of Patent: August 24, 1999
    Assignee: MA Laboratories, Inc.
    Inventors: Tzu-Yih Chu, Abraham C. Ma
  • Patent number: 5936840
    Abstract: The invention is component module (20) for combining a plurality of components (21, 23, 25, 27 and 29)into a single module (20) for use with a printed wiring board. A plurality of components, each component having a pair of contacts (21a,21b), are formed into the module with a plurality of insulating spacers (2,24,26 and 28). There is one spacer between adjacent components, said spacers serving to insulate adjacent components from each other and to secure the components together to form the module.
    Type: Grant
    Filed: November 3, 1997
    Date of Patent: August 10, 1999
    Assignee: Texas Instruments Incorporated
    Inventor: Malhi Satwinder
  • Patent number: 5929745
    Abstract: A high-voltage variable resistor unit including a terminal connection structure capable of preventing upward movement or rotation of the terminal by simple construction. A terminal is provided with a connecting portion between a held portion and a lead wire connected portion. A terminal fixing portion of the insulating casing is provided adjacent to a terminal holding portion with a connecting portion receiving recess in which the connecting portion of the terminal is received. An insulating resin is charged in the connecting portion receiving recess and hardened. The walls surrounding the connecting portion receiving recess have a pair of grooves each formed on a pair of walls facing to a first linear connecting portion and a second linear connecting portion of the terminal.
    Type: Grant
    Filed: March 26, 1997
    Date of Patent: July 27, 1999
    Assignee: Hokuriku Electric Industry Co., Ltd.
    Inventors: Ichiro Tsunezawa, Motoharu Higami
  • Patent number: 5926379
    Abstract: A unitary assembly of electronic cards has a base printed card carrying electronic microcomponents having outputs distributed at a first pitch and at least one core printed card having a size smaller than that of the base printed card, carrying microcomponents. Some at least of the microcomponents have outputs distributed at a pitch smaller than the first pitch. Several electrically conductive solder beads, distributed according to a two-dimensional array, mechanically and electrically connect the core printed card and the base printed card.
    Type: Grant
    Filed: December 6, 1996
    Date of Patent: July 20, 1999
    Assignee: Sagem Sa
    Inventors: Yves Cadet, Andre Tutka
  • Patent number: 5907903
    Abstract: The present invention provides multi-layer multi-chip circuit board comprising at least two ATAB carriers having chips thereon, stacked upon each other in a pyramid configuration and attached to a substrate, thus reducing the required area on the substrate for mounting components to form a circuit board.
    Type: Grant
    Filed: January 8, 1998
    Date of Patent: June 1, 1999
    Assignee: International Business Machines Corporation
    Inventors: Joseph George Ameen, Joseph Funari
  • Patent number: 5880935
    Abstract: A device, in particular for use in an electronic controller, includes a card rack and a subassembly. The device is manufactured by soldering over a large area the unpopulated back side of the subassembly to this card rack. The soldering can be performed using a reflow soldering process and can be automated, and thus suitable for mass production. The electrical connections of the subassembly are led spatially and electrically separately from the mechanical attachment of the subassembly to the card rack. The subassembly can be an additional component mounted on the card rack with a new additional function, so that the controller can be flexibly adapted to a given requirement profile in a simple manner by combining, in a flexible manner, a plurality of subassemblies with different layouts and modes of operation on the card rack.
    Type: Grant
    Filed: February 14, 1997
    Date of Patent: March 9, 1999
    Assignee: Robert Bosch GmbH
    Inventors: Thomas Wiesa, Ralph Schimitzek, Dieter Karr
  • Patent number: 5877560
    Abstract: A monolithic flip chip microwave integrated circuit module formed using titanium coated copper circuitry and a processing method. A dam is formed on a substrate by forming a thin protective layer such as titanium or other metal on a copper layer formed on a surface of the substrate to which a monolithic microwave integrated circuit is to be attached. The protective layer is oxidized upon exposure to air. Vias or openings are then formed in the oxidized protective layer. Solder is disposed in the openings in the oxidized protective layer, and is confined to the openings while solder is reflowed to attach the integrated circuit to the substrate. The oxidized protective layer serves a dual function that provides both a solder dam and a protective coating for the underlying copper circuitry. Copper surfaces not covered by the oxidized protective layer may be environmentally protected by depositing a thin layer containing electroless plated nickel and electroless plated gold.
    Type: Grant
    Filed: February 21, 1997
    Date of Patent: March 2, 1999
    Assignee: Raytheon Company
    Inventors: Cheng P. Wen, Kuo-Hsin Li, Wah S. Wong
  • Patent number: 5838070
    Abstract: An electronic circuit apparatus has first and second pad electrodes arranged on a substrate to be separated by a first interval, first and second chip electrodes to be separated by a second interval smaller than the first interval, a first solder for fixedly attaching the first chip electrode to the first pad electrode and a second solder for fixedly attaching the second chip electrode to the second pad electrode. Because the first interval is longer than the second interval, any constricted portion does not exist in each of the first and second solders. Therefore, because any stress is not concentrated on any portion of each of the first and second solders, the occurrence of a crack in each of the first and second solders can be prevented.
    Type: Grant
    Filed: December 20, 1996
    Date of Patent: November 17, 1998
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Toshimichi Naruse, Noriaki Sakamoto
  • Patent number: 5814401
    Abstract: A selectively filled thermally curable adhesive film (10) contains a fluxing agent for reflow soldering an electronic device to a substrate. The adhesive film has a central, region (12) and a boundary region (14) surrounding the central region. The central region consists of an adhesive that is filled with an inert filler to reduce the co-efficient of thermal expansion of the adhesive. The boundary region consists of an unfilled adhesive and a fluxing agent. The film may be used to adhesively bond a flip chip semiconductor die (20) to a substrate (21). When solder bumps (22) on the die are reflowed, the fluxing agent acts to remove any oxides present on the solderable surfaces of the substrate or the die.
    Type: Grant
    Filed: February 4, 1997
    Date of Patent: September 29, 1998
    Assignee: Motorola, Inc.
    Inventors: Daniel R. Gamota, Robert W. Pennisi, Cynthia M. Melton
  • Patent number: 5805431
    Abstract: A surface mount package particularly suitable for transformers and other components having numerous windings of fragile, difficult to handle wire has a housing which includes openings along the lower edge, the housing being plated with an electrically conductive material on portions of the lower edge and in areas surrounding the opening. A component is held within the housing, and the leads of the component are disposed in the openings at a point above the lower edge of the housing, and the leads are electrically connected to the plating surrounding the openings and the plating at the flat portions of the lower edge. The plating on the flat portions of the lower edge can be at any suitable location, i.e., remote from or adjacent to the openings. Additional components can be stacked on the exterior of the housing, as connected to the plating surrounding the openings.
    Type: Grant
    Filed: January 17, 1996
    Date of Patent: September 8, 1998
    Assignee: Synergy Microwave Corporation
    Inventors: Shankar R. Joshi, Meta Rohde