Abstract: A semiconductor package includes a wiring portion including an insulating layer, conductive patterns disposed on the insulating layer, and conductive vias penetrating through the insulating layer and connected to the conductive patterns, a semiconductor chip disposed on the wiring portion, an encapsulant disposed on the wiring portion and encapsulating at least a portion of the semiconductor chip, and a metal layer disposed on the semiconductor chip and the encapsulant and having a thickness of 10 ?m to 70 ?m.

Abstract: The embodiment of the present disclosure discloses a method of packaging a chip and a chip package structure.

Abstract: A method for manufacturing a wiring board having conductive posts includes preparing a wiring board including electronic circuit and a solder resist layer covering the electronic circuit and having first openings and second openings surrounding the first openings such that the first openings are exposing pad portions of the electronic circuit and that the second openings are exposing post connecting portions of the electronic circuit surrounding the pad portions, applying surface treatment to the pad portions, forming a plating resist layer on the wiring board after the surface treatment of the pad portions such that the plating resist layer has resist openings exposing the post connecting portions, applying electrolytic plating on the post connecting portions such that conductive posts rising from the post connecting portions are formed in the resist openings, and removing the plating resist layer from the wiring board after forming the conductive posts in the resist openings.

Abstract: A multilayer structure for an electronic device, includes a flexible substrate film (202, 502) for accommodating electronics, a number of electronic components (308, 508) provided on a first surface area (401A, 501A) of the film, the film also including a second surface area adjacent (401B, 501B) to the first surface area, and a number of conductive traces (412, 512) printed on the substrate film for electrically connecting electronic components together, wherein the number of electronic components and the related first surface area of the substrate accommodating the components have been overmolded with first thermoplastic material (306, 506), the adjacent second surface area and at least part of the first area being overmolded with second thermoplastic material so that at least part of the electronic components and the first thermoplastic material thereon are substantially embedded between the substrate film and second thermoplastic material. A corresponding method of manufacture is presented.

Abstract: An epoxy resin compound having an epoxy resin, a curing agent, and inorganic filler as main components is provided. The epoxy resin includes an epoxy resin of Chemical Formula. Accordingly, the thermal conductivity of the epoxy resin compound can be increased because the epoxy resin has a mesogen structure that facilitates crystallizability. In addition, a high radiant heat board can be provided by using the above-mentioned epoxy resin as an insulating material for a printed circuit board.

Abstract: A substrate for a stacked module includes a stacked insulator in which a plurality of insulator layers mainly composed of a thermoplastic resin are stacked, a conductor pattern arranged along the plurality of insulator layers in the stacked insulator, an embedded component connected to the conductor pattern, a pad provided on a surface of the stacked insulator and configured to be ultrasonically bonded to a bump of a mounted component to be mounted on the surface of the stacked insulator, and an auxiliary conductor pattern between the pad and the embedded component and extending in a range that covers the pad and the embedded component as viewed in a stacking direction of the plurality of insulator layers.

Abstract: A printed circuit board and a method of manufacturing a printed circuit board are provided. The printed circuit board includes an insulating layer, a circuit layer embedded in the insulating layer, a solder resist layer disposed on one surface of the insulating layer, the solder resist layer having a cavity of a through-hole shape to expose a part of the circuit layer from the insulating layer, and a metal post embedded in the solder resist layer and exposed to outside via an opening of the solder resist layer, and the metal post includes a first post metal layer, a post barrier layer, and a second post metal layer disposed in that order.

Abstract: A wiring substrate includes first through holes extending through an insulation layer, first via wirings formed in the first through holes, a conductive pattern connected to the first via wirings, recesses formed in the first via wirings, and a protective insulation layer covering the conductive pattern and the first via wirings. The first via wirings, the conductive pattern, the recesses, and the protective insulation layer form an identification mark identifiable as a particular shape including a character or a symbol. Each recess is defined by an upper surface of the corresponding first via wiring and includes a curved side wall and a bottom wall that is located at a lower position than an upper surface of the conductive pattern. The protective insulation layer is thicker over the first via wirings than over the conductive pattern.

Abstract: An electronic component includes a laminated capacitor and a substrate-type terminal on which the laminated capacitor is mounted, with an viscoelastic resin located in a space between the laminated capacitor and the substrate-type terminal. The substrate-type terminal includes a substrate body, component connecting electrodes to mount the laminated capacitor are located on a component mounting surface of the substrate body, and external connecting electrodes to be connected to a circuit board are located on a substrate mounting surface of the substrate body.

Abstract: Disclosed herein are a semiconductor package and a method of manufacturing the same. The semiconductor package includes: a substrate including a mounting electrode formed on both sides and a wiring; a plurality of first electronic devices mounted on the substrate; a second electronic devices mounted on the substrate; and a via through which the wiring of the substrate and the second electronic devices are connected.

Abstract: A patch panel structure includes a circuit board, a plurality of first RJ45 sockets, and a plurality of second RJ45 sockets. The circuit board has a first end and a second end opposite to each other. A plurality of first conducting points are formed at the first end. A plurality of second conducting points are formed at the second end. Each of the first RJ45 sockets forms a first interface and is electrically connected to each of the first conducting points. Each of the second RJ45 sockets forms a second interface, is electrically connected to each of the second conducting points, and is disposed in a parallel and symmetrical manner with respect to each of the first RJ45 sockets. Each of the first interfaces of the first RJ45 sockets is disposed in a back-to-back and spaced-apart manner with respect to each of the second RJ45 sockets.

Abstract: A wired circuit board includes a metal supporting layer, a first insulating layer, a conductive pattern, and a second insulating layer. The first and second insulating layers include first and second openings which expose both surfaces of the conductive pattern. The conductive pattern has the surface on the other side thereof in a thickness direction which is exposed through the first opening and configured as a first terminal portion, and the surface on one side thereof in the thickness direction which is exposed through the second opening and configured as a second terminal portion. The metal supporting layer includes a third opening which exposes the first terminal portion and a covering portion of the first insulating layer which covers the conductive pattern continued to the first terminal portion, and a reinforcing portion located on a surface on the other side of the covering portion in the thickness direction.

Abstract: A device (100), comprising: a housing (110) having an inner surface (160) and an outer surface (170); an electronic unit (130, 140, 180); whereby the housing (110) surrounds the electronic unit (180) at least in part; whereby at least a part of the inner surface (160) of the housing (110) comprises an electrically insulating coating (120) that contains at least 30 wt.-% of a polymer and has a coating surface (150) facing the inner surface (160); whereby the inner surface (160) and the coating surface (150) are interconnected.

Abstract: An engine control unit including a substantially rectangular printed circuit board in which a microcontroller is mounted. The printed circuit board includes a connector portion in which connection terminals are provided to be arranged in one side edge portion along the longitudinal direction thereof. The connection terminals of the connector portion include connection terminals for input on one side in the longitudinal direction and connection terminals for output on the other side with respect to a setting position. A microcontroller is disposed at substantially the center portion of the printed circuit board in the longitudinal direction thereof. An electronic component as an input interface circuit is disposed on the one side in the longitudinal direction, and an electronic component as an output interface circuit is disposed on the other side.

Abstract: To prevent decrease of the bonding strength of an electronic component and a multilayer substrate, an electronic component-embedded module may include an electronic component having a plurality of pads and a multilayer substrate which includes a plurality of resin layers and a cavity for containing the electronic component. The multilayer substrate may include a first resin layer having a plurality of first pattern conductors and a space, and a second resin layer having a second pattern conductor and a plurality of third pattern conductors. The plurality of third pattern conductors may be in conduction with either of the first pattern conductors or the pads, with the second resin layer being placed over the first resin layer. The second pattern conductor may be arranged around a first pad with a gap, and the second resin layer is present between the second pattern conductor and at least one of the first pads.

Abstract: A method for manufacturing a printed wiring board includes forming a removable layer over first pads in central portion of an interlayer insulation layer to mount IC chip, forming on the interlayer and removable layers a resin insulation layer having openings exposing second pads in peripheral portion of the interlayer layer to connect second substrate, forming a seed layer on the resin layer, in the openings and on the second pads, forming on the seed layer a plating resist having resist openings exposing the openings of the resin layer with diameters greater than the openings, filling the resist openings with electrolytic plating such that metal posts are formed in the resist openings, removing the resist, removing the seed layer exposed on the resin layer, and removing the removable layer and the resin layer on the removable layer such that cavity exposing the first pads is formed in the resin layer.

Abstract: A method for manufacturing a printed wiring board includes forming a resin insulation layer on an interlayer resin insulation layer and conductive circuits such that the resin insulation layer has first openings exposing pad portions in central portion of the interlayer layer and second openings exposing pad portions in peripheral portion of the interlayer layer, forming a seed layer on the resin insulation layer, in the first and second openings and on the pad portions, forming on the seed layer a plating resist such that the resist has resist openings exposing the second openings and having diameters greater than the second openings, filling the resist openings with electrolytic plating material via the seed layer such that metal posts are formed in the resist openings, removing the resist from the resin insulation layer, and removing the seed layer exposed on the resin insulation layer by the removing of the resist.

Abstract: The present invention is directed to an RF device that includes a ceramic layer characterized by a ceramic layer dielectric constant and includes an RF circuit arrangement having a predetermined geometry and predetermined electrical characteristics. The ceramic layer dissipates thermal energy generated by the RF circuit via substantially the entire ceramic surface area. A first dielectric layer comprises a thermoplastic material and has a predetermined first thickness and a first dielectric constant. The predetermined electrical characteristics of the RF circuit arrangement are a function of the ceramic layer dielectric constant. A relative softness of the thermoplastic material is a function of the RF device operating temperature.

Abstract: There is provided a circuit board to which a solder ball composed of a lead (Pb)-free solder is to be connected, a semiconductor device including an electrode and a solder ball composed of a lead (Pb)-free solder disposed on the electrode, and a method of manufacturing the semiconductor device, in which mounting reliability can be improved by enhancing the bonding strength (adhesion strength) between the solder ball composed of a lead (Pb)-free solder and the electrode.

Abstract: The gas barrier property of a laminate constituted by a base material containing a resin or a rubber and an oxide glass is improved. A composite member containing an oxide glass 2 formed as a layer densely on a base material 1 containing a resin or a rubber, in which the oxide glass is bonded to the base material by irradiating the oxide glass with an electromagnetic wave and softening and fluidizing the oxide glass.

Abstract: A MCM system board uses a stiffener arrangement to enhance mechanical, thermo and electrical properties by incorporating an LGA compression connector in a computer system. The present designs of large scale computing systems (LSCS) in IBM use a MCM that is attached to a system board and held together by a stiffening frame. Due to the nature of the manufacturing of the system board, there can be significant gaps formed in the mounting area of the MCM between the board and the stiffener. A method is described that not only fills the void, it also, in addition promotes thermo conduction of excess heat away from the MCM and at the same time promotes enhanced electrical properties of the LGA connections of the MCM to the system board.

Abstract: An integral solar module power conditioning system includes one or more solar module support frames. Each frame includes a plurality of plug-and-play electrical connectors integrated therewith. A microinverter or microinverter connector is also integrated with each frame. Each frame is configured to receive a respective solar electric module and to carry electrical power through a plurality of solar electric modules and corresponding microinverters connected together via a plurality of solar module support frames connected together via the plurality of integrated plug-and-play electrical connectors.

Abstract: A plastic panel forming part of a motor vehicle is disclosed having a number of embedded conductors for electrically connecting together an electrical connector and an electrical unit. Parts of the electrical connector and the electrical unit are formed as integral parts of the plastic panel. The electrical connector includes terminals connected to the electrical conductors for co-operation with terminals formed as part of a plug used to connect the conductors to other electrical circuits of the motor vehicle. In one embodiment the electrical unit is in the form of a fuse box having electrical terminals held in position by the plastic panel and in pairs for cooperation with a respective fuse.

Abstract: A module includes a wiring board; a plurality of mounting electrodes for component mounting, the mounting electrodes being disposed on one principal surface of the wiring board; a plurality of components mounted on the one principal surface of the wiring board and solder-connected to the mounting electrodes; a solder resist being a photosensitive resin configured to cover the one principal surface of the wiring board, with a plating electrode layer of each mounting electrode exposed; and a sealing resin layer disposed on the one principal surface of the wiring board, the sealing resin layer being configured to cover the photosensitive resin and the components connected to the mounting electrodes. A recess substantially wedge-shaped in cross section is provided at a boundary between the plating electrode layer of each mounting electrode and the solder resist, and the recess is filled with resin of the sealing resin layer.

Abstract: The present disclosure relates to the field of fabricating microelectronic packages and the fabrication thereof, wherein a microelectronic device may be formed within a bumpless build-up layer coreless (BBUL-C) microelectronic package and wherein a warpage control structure may be disposed on a back surface of the microelectronic device. The warpage control structure may be a layered structure comprising at least one layer of high coefficient of thermal expansion material, including but not limited to a filled epoxy material, and at least one high elastic modulus material layer, such as a metal layer.

Abstract: An apparatus for electrical isolation of metallic hardware is provided and includes an item of hardware and an isolation sheet disposed in contact with the item of hardware. The isolation sheet includes first and second opposing sides at least one of which is anodized.

Abstract: There is provided an electronic circuit module that prevents a bonding force between ground wiring and a shield from decreasing and maintains successfully a desirable shield effect. The electronic circuit module includes a core layer also functioning as the ground wiring, each face OS of each first protrusion of the core layer facing to an end face of a shield is adjacent to faces OS of an outer cover made of an insulating synthetic resin facing to the end face of the shield, and the end face of the shield is bonded to both of the each face OS of each first protrusion facing to the end face of the shield and the faces OS of the outer cover facing to the end face of the shield.

Abstract: An interconnection component includes a first support portion has a plurality of first conductive vias extending therethrough substantially perpendicular to surfaces thereof such that each via has a first end adjacent a first surface and a second end adjacent a second surface. A second support portion has a plurality of second conductive vias extending therethrough substantially perpendicular to surfaces thereof such that each via has a first end adjacent the first surface and a second end adjacent the second surface. A redistribution layer is disposed between the second surfaces of the first and second support portions, electrically connecting at least some of the first vias with at least some of the second vias. The first and second support portions can have a coefficient of thermal expansion (“CTE”) of less than 12 parts per million per degree, Celsius (“ppm/° C.”).

Abstract: There is provided an electronic circuit module that prevents a bonding force between ground wiring and a shield from decreasing and maintains successfully a desirable shield effect. The electronic circuit module includes a core layer also functioning as the ground wiring, each face OS of each first protrusion of the core layer facing to an end face of a shield is adjacent to faces OS of an outer cover made of an insulating synthetic resin facing to the end face of the shield, and the end face of the shield is bonded to both of the each face OS of each first protrusion facing to the end face of the shield and the faces OS of the outer cover facing to the end face of the shield.

Abstract: A device mounting board includes a metallic substrate, an oxide film formed such that the surfaces of the metallic form are oxidized, an insulating resin layer disposed on the oxide film facing one main surface of the metallic layer, and a wiring layer disposed on the insulating resin layer. The film thickness of a certain partial region of the oxide film disposed below a first semiconductor device is greater than that of the other regions surrounding the partial region of the oxide film. Conversely, the film thickness of the insulating resin layer underneath a second semiconductor device is less than that of the insulating resin layer underneath the first semiconductor device.

Abstract: A power module substrate includes: a ceramics substrate composed of AlN, having a top face; a metal plate composed of pure aluminum and joined to the top face of the ceramics substrate with a brazing filler metal including silicon interposed therebetween; and a high concentration section formed at a joint interface at which the metal plate is joined to the ceramics substrate, having a silicon concentration that is more than five times the silicon concentration in the metal plate.

Abstract: This disclosure provides systems, methods and apparatus for glass via bars that can be used in compact three-dimensional packages, including embedded wafer level packages. The glass via bars can provide high density electrical interconnections in a package. In some implementations, the glass via bars can include integrated passive components. Methods of fabricating glass via bars are provided. In some implementations, the methods can include patterning and etching photo-patternable glass substrates. Packaging methods employing glass via bars are also provided.

Abstract: A surface-mount package structure for reducing the ingress of moisture and gases thereto is disclosed. The surface-mount structure includes a sub-module having a dielectric layer, semiconductor devices attached to the dielectric layer, a first level interconnect structure electrically coupled to the semiconductor devices, and a second level I/O connection electrically coupled to the first level interconnect and formed on the dielectric layer, with the second level I/O connection configured to connect the sub-module to an external circuit. The semiconductor devices of the sub-module are attached to a substrate structure, with a dielectric material positioned between the dielectric layer and the substrate structure to fill in gaps in the surface-mount structure.

Abstract: The Electronic Module has a body case 2, including a plurality of case members 3, 4 and that has an internal space (S) where a first opening P1 is formed on one side surface of the internal space and a second opening P2 that opens in a direction different from that of the first opening P1 is in an exposed state when a plurality of the case members are separated each other, a substrate 5 on which a sensor IC 51 is mounted and that is housed in the internal space of the body case, and a resin body 6 that covers the substrate 5 by being filled in the internal space of the body case and solidified or hardened, and is characterized by that a plurality of the case members and the substrate 5 are integrated by the use of the resin body 6 as an accouplement.

Abstract: According to one embodiment, there are provided a memory which is provided on a circuit board, a controller which is provided on the circuit board and controls the memory, and a signal line which is formed on the circuit board and configured to perform data transmission between the controller and the memory, in which a width of the signal line in the place where the signal line is led out from the memory is large compared with a place disposed under the memory.

Abstract: A method for producing an electronic module, in that at least one first microelectronic component is provided and is electrically connected to a second microelectronic component by a first flip-chip method step; at least one dielectric component is provided which has at least one printed circuit trace, and at least one printed circuit trace of the dielectric component is electrically connected to the second microelectronic component; and the second microelectronic component is electrically connected by a second flip-chip method step to a printed circuit board by way of the printed circuit trace(s) of the dielectric component, in order to avoid vias through a microelectronic component; the invention also relates to a corresponding electronic module.

Abstract: Methods of manufacturing low profile magnetic components configured as a power management devices for an electrical system of an electronic device involve prefabricated coil windings assembled with a plurality of flexible dielectric sheet layers, and laminating the plurality of flexible dielectric sheets around the prefabricated coil windings to form a dielectric body having a low profile chip configuration attachable to the electronic device.

Abstract: A module (1) includes a first functional device (2) and a second functional device (3). The first functional device (2) includes a base electrode, an emitter electrode and a collector electrode. The second functional device (3) includes at least one electrode. The module (1) further includes a conductive frame (4). One of the base electrode, the emitter electrode, and the collector electrode of the first functional device (2) is directly connected to the frame (4). The electrode of the second functional device (3) is also directly connected to the frame (4). The frame (4) includes a portion serving as a terminal for external connection.

Abstract: The invention provides a semiconductor package structure, comprising: a substrate having a first surface and a second surface; a first conductive layer plated on the first surface; a semiconductor element attached to the first conductive layer on the first surface of the substrate for electrically connecting; a second conductive layer plated on the first surface and surrounded the semiconductor element and the first conductive layer, wherein the height of the second conductive layer is higher than the first conductive layer; and a lid attached to the top of the second conductive layer for sealing the semiconductor element.

Abstract: The present invention relates to an epoxy resin composition for electronic parts encapsulation, including the following components (A) to (E), (A) an epoxy resin having an ICI viscosity of from 0.008 to 0.1 Pa·s and an epoxy equivalent of from 100 to 200 g/eq; (B) a phenol resin having an ICI viscosity of from 0.008 to 0.1 Pa·s and a hydroxyl-group equivalent of from 100 to 200 g/eq; (C) a curing accelerator; (D) an inorganic filler; and (E) a silicone compound, in which the component (D) is contained in an amount of from 82 to 88 wt % of the whole of the epoxy resin composition, the component (E) is contained in an amount of from 5 to 15 wt % of the whole of organic components in the epoxy resin composition, and the epoxy resin composition has a gelation time of 15 to 25 seconds.

Abstract: An electro-optic apparatus has an electro-optic panel, driver semiconductor chips bonded onto the terminal portion of the electro-optic panel, and two protection films either or both of which are transparent, wherein the electro-optic panel is sealed by being sandwiched between the two protection films, and one protection film that covers the terminal portion has openings for exposing the driver semiconductor chips.

Abstract: A circuitized substrate which includes at least one circuit layer and at least one substantially solid dielectric layer comprised of a dielectric composition which includes a cured resin material and a predetermined percentage by weight of particulate fillers, but not including continuous or semi-continuous fibers as part thereof.

Abstract: A method and apparatus for reducing pressure effects on an encapsulated device. In one embodiment, the apparatus comprises a power module comprising an equipment box assembly containing (i) an equipment module housing, (ii) a potted electronic device disposed within the equipment module housing, and (iii) a resilient expansion absorption layer disposed between at least a portion of the potted electronic device and at least a portion of the equipment module housing.

Abstract: An electronic device module is disclosed comprising: A. at least one electronic device, and B. a polymeric material in intimate contact with at least one surface of the electronic device, the polymeric material comprising (1) An ethylenic polymer comprising at least 0.1 amyl branches per 1000 carbon atoms as determined by Nuclear Magnetic Resonance and both a highest peak melting temperature, Tm, in ° C., and a heat of fusion, Hf, in J/g, as determined by DSC Crystallinity, where the numerical values of Tm and Hf correspond to the relationship: Tm?(0.2143*Hf)+79.643, and wherein the ethylenic polymer has less than about 1 mole percent ctane comonomer, and less than about 0.5 mole percent ctane, pentene, or ctane comonomer. (2) optionally, free radical initiator or a photoinitiator in an amount of at least about 0.05 wt % based on the weight of the copolymer, (3) optionally, a co-agent in an amount of at least about 0.

Abstract: An electronic device module comprising: A. At least one electronic device, e.g., a solar cell, and B. A polymeric material in intimate contact with at least one surface of the electronic device, the polymeric material comprising (1) a polyolefin copolymer characterized as having has an average Mv and a valley temperature between the interpolymer and high crystalline fraction, Thc, such that the average Mv for a fraction above Thc from ATREF divided by average Mv of the whole polymer from ATREF (Mhc/Mp) is less than about 1.95 and wherein the copolymer has a CDBI of less than 60%, (2) optionally, a vinyl silane, (3) optionally, free radical initiator or a photoinitiator in an amount of at least about 0.05 wt % based on the weight of the copolymer, and (4) optionally, a co-agent in an amount of at least about 0.05 wt % based upon the weight of the copolymer.

Abstract: The invention concerns a method of fusing and electrically contacting a first insulating substrate (28A) having at least one first conductive layer (29A) thereon with at least one second insulating substrate (28B) having at least one second conductive layer (29B) thereon, the method comprising: stacking the first and second substrates (28A, 28B) such that an interface zone is formed between them, the interface zone comprising an electrical contacting zone where at least one first conductive layers (29A) faces and is at least partially aligned with at least one second conductive layer (29B), and a substrate fusing zone where the insulating substrates (28A, 28B) directly face each other; focusing to the interface zone of the substrates (28A, 28B) through one of the substrates (28A, 28B) a plurality of sequential focused laser pulses from a laser source, the pulse duration, pulse frequency and pulse power of the laser light being chosen to provide local melting the substrate (28A, 28B) materials and the conducti

Abstract: A multilayer printed wiring board (11) is composed of a plurality of printed wiring boards (21a and 21b) each having wiring on its both sides, and a relaxing connection layer (15) for interconnecting the printed wiring boards (21a and 21b). The relaxing connection layer (15) contains an inorganic filler, a thermosetting resin, and a reliever for relieving internal stress. The multilayer printed wiring board (11) is prevented from warpage by making the relaxing connection layer (15) disposed inside it absorb internal stress caused by heating and cooling in a solder reflow process or other processes.

Abstract: A touch panel includes first and second substrates, and first insulating layer disposed therebetween. The first substrate has, on its bottom surface, a first conductive layer having opposing first and second sides; a first electrode along the first side; and a second electrode along the second side. The second substrate has, on its top surface, a second conductive layer facing the first conductive layer with a predetermined space and having third and fourth sides orthogonal to the first and second sides: a third electrode along the third side; and a fourth electrode along the fourth side. The first insulating layer is frame-like and coats at least part of the first and second electrodes. The first and second electrodes and the first insulating layer together form a decoration part having a color tone to prevent the third and fourth electrodes from being visible when viewed from the first substrate side.

Abstract: This disclosure provides systems, methods and apparatus for glass packaging of integrated circuit (IC) and electromechanical systems (EMS) devices. In one aspect, a glass package may include a glass substrate, a cover glass, one or more devices encapsulated between the glass substrate and the cover glass, and bond pads configured to attach to a flexible connector and in electrical communication with an encapsulated device. In some implementations, a flexible connector may be used to electrically connect a device within the glass package to an electrical component, such as an integrated circuit (IC) device or PCB, outside the glass package.

Abstract: The present disclosure relates to the field of fabricating microelectronic packages and the fabrication thereof, wherein a microelectronic device may be formed within a bumpless build-up layer coreless (BBUL-C) microelectronic package and wherein a warpage control structure may be disposed on a back surface of the microelectronic device. The warpage control structure may be a layered structure comprising at least one layer of high coefficient of thermal expansion material, including but not limited to a filled epoxy material, and at least one high elastic modulus material layer, such as a metal layer.