With Specific Dielectric Material Or Layer Patents (Class 361/746)
  • Publication number: 20030026078
    Abstract: A wired circuit board having a terminal portion formed as a flying lead that can provide enhanced strength of the conductive pattern, both sides of which are exposed, by simple construction to effectively prevent disconnection of the conductive pattern. The wired circuit board having the terminal portion formed as the flying lead in which the both sides of the conductive pattern are exposed includes, in crossing areas where ends of a cover-side opening and ends of a base-side opening and the conductive pattern are crossed each other, (i) the widened portions formed in the conductive pattern or (ii) cover-side projections and base-side projections formed in the cover layer and the base layer, respectively.
    Type: Application
    Filed: July 16, 2002
    Publication date: February 6, 2003
    Inventors: Makoto Komatsubara, Shigenori Morita, Tadeo Ookawa, Toshio Shintani
  • Publication number: 20020196610
    Abstract: An electronic power module including at least one semi-conductor power component disposed on an electrically insulating substrate, wherein said semi-conductor power component includes a face in contact with said substrate, which face is metallized in part and is covered in part in a diamond layer, said metallized portion being in contact with a conductor track provided on the surface of the substrate, and said diamond-covered portion being in register with an opening formed in the substrate, said substrate including a face remote from the semi-conductor component which is cooled by a liquid coolant, said liquid flowing into said opening and over the surface of the diamond-covered portion.
    Type: Application
    Filed: June 19, 2002
    Publication date: December 26, 2002
    Applicant: ALSTOM
    Inventors: Chritophe Beuille, Fabrice Breit
  • Patent number: 6498309
    Abstract: The present invention provides a circuit board, which can reduce a conduction loss and generate no trouble in electric/electronic apparatuses in the case of being mounted to electric/electronic apparatuses adapting a high frequency current. A circuit board 1 is formed a manner that a copper foil layer 2 and a copper layer 3 are laminated on a base material 5 made of polytetrafluoroethylene so as to form a predetermined circuit, and further, a tin plating layer 4 is laminated on these copper layers.
    Type: Grant
    Filed: February 7, 2001
    Date of Patent: December 24, 2002
    Assignee: Maspro Denkoh Co., LTD
    Inventor: Takehito Kuno
  • Patent number: 6492599
    Abstract: In a multilayer wiring board comprising: an insulating board (for example, a glass board 1); and a wiring layer (for example, wiring patterns 2a, 5a and 8a) superimposed on the insulating board through an insulating film (for example, insulating films 3 and 6), a sum (total film thickness) d (&mgr;m) of the thickness of the insulating films 3 and 6 and the internal stress f (MPa) of the insulating film satisfy the following relational expression (1): d×<700(MPa·&mgr;m)  (1)
    Type: Grant
    Filed: September 12, 2000
    Date of Patent: December 10, 2002
    Assignee: Hoya Corporation
    Inventor: Osamu Sugihara
  • Patent number: 6486398
    Abstract: A sealing arrangement is provided for sealing an orifice between an interior and an exterior surface of an electronic module. An air-permeable, water-impermeable membrane is disposed in the orifice. A portion of the exterior surface is provided with at least one surface channel which extends between the orifice and a distant point. A protective cover is attached to the exterior surface and arranged to overlie the membrane disposed about the orifice but not to overlie the distant point, thereby providing an air path to the interior surface of the module, via the surface channel and the membrane.
    Type: Grant
    Filed: March 26, 2001
    Date of Patent: November 26, 2002
    Assignee: Motorola, Inc.
    Inventors: Andrew McCulloch, Roger Humphreys
  • Publication number: 20020167828
    Abstract: A DC bus for use in a power module has a positive DC conductor bus plate parallel with a negative DC conductor bus plate. One or more positive leads are connected to the positive bus and are connectable to a positive terminal of a power source. One or more negative leads are connected to the negative bus and are connectable to a negative terminal of a power source. The DC bus has one or more positive connections fastenable from the positive bus to the high side of a power module. The DC bus also has one or more negative connections fastenable from the negative bus to the low side of the power module. The positive bus and negative bus permit counter-flow of currents, thereby canceling magnetic fields and their associated inductances, and the positive and negative bus are connectable to the center portion of a power module.
    Type: Application
    Filed: March 27, 2002
    Publication date: November 14, 2002
    Applicant: Ballard Power Systems Corporation
    Inventors: Scott Parkhill, Sayeed Ahmed, Fred Flett
  • Patent number: 6479760
    Abstract: Provided is a printed wiring board for a chip size scale package, which overcomes the poor adhesion of solder balls to a base material which poor adhesion is caused by a recent decrease in the size of the solder balls, and in the chip size scale package, the distortion of the printed wiring board is decreased and the distortion of a semiconductor package formed by mounting a semiconductor chip on the printed wiring board by wire bonding or flip chip bonding is decreased.
    Type: Grant
    Filed: October 11, 2001
    Date of Patent: November 12, 2002
    Assignee: Mitsubishi Gas Chemical Company, Inc.
    Inventors: Hidenori Kimbara, Nobuyuki Ikeguchi, Katsuji Komatsu
  • Patent number: 6478909
    Abstract: A method for surface mounting electrical components to a substrate, such as a printed circuitboard, involves use of an anisotropically conductive adhesive or Z-Axis adhesive between facing conductive surface areas on the component and substrate. Pressure is applied to the conductive adhesive by a nonconducting adhesive that is first cured between oppositely facing nonconductive surface areas of the component and substrate. This fixes the thickness of each layer of the conductive adhesive at a dimension no greater than its design conductive thickness. In a first submethod, the nonconducting adhesive is a fast setting adhesive subjected to mechanical pressure only as it is assembled on the substrate prior to the subsequent curing of the conductive adhesive. In a second submethod, it is a high shrinkage adhesive that applies compressive force between the component and substrate as it cures and shrinks dimensionally while at a temperature below the subsequent curing temperature of the conductive adhesive.
    Type: Grant
    Filed: April 10, 2000
    Date of Patent: November 12, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Mark E. Tuttle
  • Patent number: 6473314
    Abstract: A low cost radio frequency interference filter assembly comprises a multiple layer structure including a middle trace layer disposed between an upper ground layer and lower ground layer. Non-conductive insulation layers are disposed between the middle trace layer and the upper and lower ground layers. The upper layer includes input contacts, signal contacts, and capacitors which are coupled to the signal contacts and an upper grounded substrate. The middle trace layer includes a grounded substrate and trace lines which are coupled to the signal contacts of the upper layer by signal vias. The lower layer includes a grounded substrate. Ground vias are formed through the insulation layers to couple the middle grounded substrate to the upper and lower grounded substrates. The filter assembly may be formed as an integral projection of a printed circuit board assembly.
    Type: Grant
    Filed: August 3, 2000
    Date of Patent: October 29, 2002
    Assignee: Powerwave Technologies, Inc.
    Inventors: James Keith Custer, Pauline Mei-Seung Tong
  • Publication number: 20020126459
    Abstract: A stackable microcircuit layer formed from a plastic encapsulated microcircuit (PEM) and method of making the same is disclosed. The method involves the steps of starting with a commercially available PEM (e.g. a plastic Thin Small Outline Package or TSOP) that contains a microcircuit or die within an encapsulant and modifying the PEM to expose conductive members that are electrically connected to the microcircuit's bond pads. In the case of a TSOP, the preferred modifying step is accomplished by top grinding the TSOP in order to remove the lead frame that was secured above the die and encapsulated along with it in the TSOP. Next, reroute metallization is applied in order to connect the conductive members that were exposed by the top grinding, to an edge of the modified PEM. Finally, if appropriate, the modified PEM is thinned through backside grinding and diced to a desired area, in order to provide a stackable microcircuit layer that may form a part of a dense electronic package.
    Type: Application
    Filed: May 10, 2002
    Publication date: September 12, 2002
    Inventors: Douglas M. Albert, Keith D. Gann
  • Patent number: 6449168
    Abstract: The present invention refers to circuit board (10), in particular a multilayer circuit board including at least a first carrying section (11) and a second section (12), conductor pattern (17a, 17b, 17c) and via holes (14, 14b, 14c), at least one of the sections (11; 12) comprises at least one cavity (13a, 13b) for receiving a least one electric component (15), preferably a naked circuit, the second section (11, 12) constitutes a protective cover essentially hermetical sealing of the component (15). The circuit board (10) comprises substrates of a non ceramic material and that said substrates are protected against moisture penetrating in the transverse direction of the substrates by means scaling arranged at outer edges of the substrates.
    Type: Grant
    Filed: October 26, 1999
    Date of Patent: September 10, 2002
    Assignee: Telefonaktiebolaget LM Ericcson (publ)
    Inventor: Mats Söderholm
  • Patent number: 6441313
    Abstract: An interconnecting apparatus employing a lossy power distribution network to reduce power plane resonances. In one embodiment, a printed circuit board includes a lossy power distribution network formed by a pair of parallel planar conductors separated by a dielectric layer. The pair of parallel planar conductors includes a first power supply plane suitable for use, for example, as a ground plane and a second power supply plane suitable for use, for example, as a power plane (e.g., VCC). The dielectric layer has a loss tangent value of at least 0.2, and preferably of at least 0.3. In one embodiment, the dielectric material between the power planes could have a frequency dependent loss tangent, such that a loss tangent value of 0.3 is achieved at and above the lowest resonance frequency of the planes.
    Type: Grant
    Filed: November 23, 1999
    Date of Patent: August 27, 2002
    Assignee: Sun Microsystems, Inc.
    Inventor: Istvan Novak
  • Patent number: 6399891
    Abstract: A multilayer board free from breakage at connecting parts due to thermal fatigue is provided. A multilayer board 1 of the present invention comprises alternating polyimide films 11-16 and copper films 21-26. The polyimide films 11-16 have a thermal expansion coefficient of 2-5 ppm/° C. so that the multilayer board 1 has a total thermal expansion coefficient of less than 10 ppm/° C. Because of the thermal expansion coefficient close to that of the semiconductor element to be mounted, no breakage occurs at connecting parts to the semiconductor element. The multilayer board 1 of the present invention may be used as both interposer and motherboard.
    Type: Grant
    Filed: June 5, 2000
    Date of Patent: June 4, 2002
    Assignee: Sony Chemicals Corporation
    Inventors: Hideyuki Kurita, Masayuki Nakamura
  • Patent number: 6380622
    Abstract: A pressed-contact type semiconductor device in which a main electrode surface of a semiconductor element is contacted with an electrode plate by a pressed-contact, which can reduce both an electric resistance and a thermal resistance between the main electrode surface of the semiconductor element and the electrode plate. The pressed-contact type semiconductor device (100) is provided with a semiconductor element (1) having electrode surfaces, a pair of electrode plates (2) contacted with the electrode surfaces by the pressed-contact, a pair of insulating plates (3) contacted with the outer side of the pair of the electrode plates by the pressed-contact, and a pair of radiating plates (4) contacted with the outer side of the pair of the insulating plates by the pressed-contact. A contact intermediary member (5), which is made up of particle member having at least thermal conductivity and electric conductivity, is intercalated between the semiconductor element and the electrode plate.
    Type: Grant
    Filed: November 8, 1999
    Date of Patent: April 30, 2002
    Assignee: Denso Corporation
    Inventors: Yasuyoshi Hirai, Kazuhito Nomura, Tomoatsu Makino, Takahiko Yoshida, Masahiro Shiozawa, Atsushi Hashikawa, Muneo Yorinaga
  • Patent number: 6377467
    Abstract: The present invention relates to a novel thermal-sensitive resistive apparatus, such as PTC and NTC, which allocates planar electrode films on the top and bottom surfaces of a prior art thermal-sensitive resistive apparatus, such as a PTC apparatus, to laminate with an outer electrode layer. A plurality of interconnection vias are electroplated with conductive material to connect to any plane. It is convenient to surface mount the apparatus of the present invention on a printed circuit board. The present invention can largely increase the dimensional stability of components and overcome the disadvantage that thermal diffusion of the prior are surface mounted resistive apparatus is affected easily by line width and environments.
    Type: Grant
    Filed: April 4, 2000
    Date of Patent: April 23, 2002
    Assignee: Polytronics Technology Corporation
    Inventors: Fu-Hua Chu, Yun-Ching Ma, David Shau-Chew Wang
  • Patent number: 6301122
    Abstract: The radio frequency module of the present invention includes an insulating substrate having a first metal film on a first principal surface thereof and a second metal film on a second principal surface thereof opposed to the first principal surface and a semiconductor device. The semiconductor device is thermally and electrically coupled to the second metal film, and a thickness of the second metal film is larger than that of the first metal film.
    Type: Grant
    Filed: June 11, 1997
    Date of Patent: October 9, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Osamu Ishikawa, Masahiro Maeda
  • Patent number: 6295206
    Abstract: A memory card is disclosed which has a card body (2) having a concavity (9) formed at the forward end thereof in the inserting direction and in which terminals (5) are disposed and projections (10) are formed between the terminals (5) to prevent the terminals (5) from being touched or accessed from outside. A receptacle for the memory card is also disclosed. The memory card has a simple structure designed to positively protect the terminals and easily let out dust or the like from inside, thereby permitting to assure a positive connection with the receptacle.
    Type: Grant
    Filed: January 18, 2000
    Date of Patent: September 25, 2001
    Assignee: Sony Corporation
    Inventors: Yoshio Kondo, Toshiharu Kobayashi, Takumi Okaue, Akira Sassa
  • Patent number: 6184576
    Abstract: A packaging and interconnection for connecting a contact structure to an outer peripheral component with a short signal pass length to achieve a high frequency operation. The packaging and interconnection is formed of a contact structure made of conductive material and formed on a contact substrate through a photolithography process, a contact trace formed on the contact substrate and electrically connected to the contact structure at one end, and the other end of the contact trace is extended toward an edge of the contact substrate, a connection target provided at an outer periphery of the contact structure to be electrically connected with the other end of the contact trace, an elastomer provided under the contact substrate for allowing flexibility in the interconnection and packaging of the contact structure, and a support structure provided between for supporting the contact structure, the contact substrate and the elastomer.
    Type: Grant
    Filed: September 21, 1998
    Date of Patent: February 6, 2001
    Assignee: Advantest Corp.
    Inventors: Mark R. Jones, Theodore A. Khoury
  • Patent number: 6147860
    Abstract: An external storage device includes an external storage device main includes a thin type external storage device module formed into a package sealed on one side from a storage element containing at least one non-volatile semiconductor memory device, and a flat type external connection terminal connected to an input/output terminal of the storage element and led and exposed to a backside of the module, and an external storage device unit that includes an external storage device main detachable section for engaging, insertedly attaching, and detaching the external storage device main, a resilient contact electrically connecting to the external connection terminal of the external storage device main, and at least a part of a circuit for driving and controlling the storage element.
    Type: Grant
    Filed: March 14, 1997
    Date of Patent: November 14, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi Iwasaki
  • Patent number: 6147870
    Abstract: A printed circuit assembly and method of making the same facilitates the attachment of high density modules onto a printed circuit board. In one embodiment, the high density modules are attached to the printed circuit board using an adhesive having a conductive material disposed within at least one via. In an alternate embodiment, an adhesive layer including a plurality of non-conductive "gauge particles" disposed within a non-conductive adhesive is used to attach the module to the printed circuit board. When the adhesive layer is disposed between a module and a printed circuit, individual gauge particles are interposed or sandwiched at various points between the layers such that the diameters of the particles control the layer separation throughout overlapping areas of thereof, thereby permitting careful control over layer separation.
    Type: Grant
    Filed: November 19, 1998
    Date of Patent: November 14, 2000
    Assignee: Honeywell International Inc.
    Inventor: Richard J. Pommer
  • Patent number: 6122170
    Abstract: A ceramic base plate of aluminum nitride ceramics, for example, as a power module board has a metal layer on a surface of the ceramic base plate at a fixing portion at which the ceramic base plate is fixed onto a heat radiating plate. Further, a metal film is provided entirely on the rear surface of the ceramic base plate. An IGBT chip or the like is fixed onto the ceramic base plate with a conductive layer interposed therebetween, to form a power module board. Therefore, it is possible to avoid the generation of cracks when the ceramic base plate is mechanically fixed onto the heat radiating plate without using solder, and heat radiation from the ceramic base plate to the heat radiating plate can be improved.
    Type: Grant
    Filed: June 29, 1999
    Date of Patent: September 19, 2000
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Yoshiyuki Hirose, Kazutaka Sasaki, Mitsuru Shimazu, Hirohiko Nakata
  • Patent number: 6114005
    Abstract: A laminate capable of mounting semiconductor elements thereon; comprising an insulating layer which is constituted by a resin portion of sea-island structure and a woven reinforcement. The resin portion of sea-island structure is, for example, such that a resin as islands are dispersed in a resin as a matrix. Thus, the insulating layer exhibits a coefficient of thermal expansion of 3.0.about.10 (ppm/K) in a planar direction thereof and a glass transition temperature of 150.about.300 (.degree.C.). Owing to these physical properties, thermal stresses which the laminate undergoes in packaging the semiconductor elements thereon can be reduced, so that the connections of the laminate with the semiconductor elements can be made highly reliable.
    Type: Grant
    Filed: May 20, 1997
    Date of Patent: September 5, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Akira Nagai, Masatsugu Ogata, Shuji Eguchi, Masahiko Ogino, Toshiaki Ishii, Masanori Segawa, Hiroyoshi Kokaku, Ryo Moteki, Ichiro Anjoh
  • Patent number: 6097612
    Abstract: The radio frequency module of the present invention includes an insulating substrate having a first metal film on a first principal surface thereof and a second metal film on a second principal surface thereof opposed to the first principal surface and a semiconductor device. The semiconductor device is thermally and electrically coupled to the second metal film, and a thickness of the second metal film is larger than that of the first metal film.
    Type: Grant
    Filed: June 11, 1997
    Date of Patent: August 1, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Osamu Ishikawa, Masahiro Maeda
  • Patent number: 6088233
    Abstract: A semiconductor device includes a board base having through-holes filled with a filling core, an additive layer provided on an upper surface of the board base as well as an upper surface of the filling core wherein the additive layer includes a wiring pattern having one or more paths, a semiconductor chip fixed on an upper surface of the additive layer, and nodes provided on a lower surface of the board base, wherein the one or more paths are laid out without a restriction posed by the through-holes, and are used for electrically connecting the semiconductor chip and the nodes.
    Type: Grant
    Filed: November 18, 1998
    Date of Patent: July 11, 2000
    Assignee: Fujitsu Limited
    Inventors: Makoto Iijima, Tetsushi Wakabayashi, Toshio Hamano, Masaharu Minamizawa, Masashi Takenaka, Taturou Yamashita, Masataka Mizukoshi
  • Patent number: 6013357
    Abstract: A conductor pattern is formed on at least one surface of an AlN- or Si.sub.3 N.sub.4 -based ceramic substrate which is such that the ratio between the principal metal component binding with N to form the ceramic mass and the B in the BN remaining on the surface layer is no more than 50.times.10.sup.-6 as either B/Al or B/Si, wherein B/Al represents the ratio of I.sub.B to I.sub.Al where I.sub.B is the X-ray diffraction intensity of boron present on the surface layer and I.sub.Al is the X-ray diffraction intensity of aluminum, and B/Si represents the ratio of I.sub.B to I.sub.Si where I.sub.B is as defined above and I.sub.Si is the X-ray diffraction intensity of silicon. The thus produced circuit board has both a peel strength of at least 30 kg/mm.sup.2 and a capability of withstanding at least 30 heat cycles and, hence, satisfies the performance requirements of the recent models of power module ceramic circuit boards.
    Type: Grant
    Filed: August 25, 1997
    Date of Patent: January 11, 2000
    Assignee: Dowa Mining Co., Ltd.
    Inventors: Masami Sakuraba, Masami Kimura, Junji Nakamura, Masaya Takahara
  • Patent number: 5995374
    Abstract: A substrate unit is constituted by a printed substrate on which electronic parts such as a relay block is mounted, and at least printed circuit conductors and terminals in the printed substrate and relay block are buried in a sealing resin material hardened in a bag-like body of a thin resin film set in an injection mold, and the hardened sealing resin material is then released from the injection mold together with the bag-like body.
    Type: Grant
    Filed: April 23, 1998
    Date of Patent: November 30, 1999
    Assignee: Yazaki Corporation
    Inventors: Masataka Suzuki, Hiroyuki Ashiya, Yayoi Maki, Atsushi Masuda
  • Patent number: 5993946
    Abstract: A lattice of a wiring or terminal pattern is varied at areas on a wiring board. The spacing of the wiring lattice is reduced only in a predetermined area for a device having many terminals. An alignment pattern is provided in the predetermined area. The spacing of the wiring lattice in the central portion of the wiring board may be the finest and may get gradually coarser toward the peripheral portion of the wiring lattice.
    Type: Grant
    Filed: May 16, 1996
    Date of Patent: November 30, 1999
    Assignee: NEC Corporation
    Inventor: Tatsuo Inoue
  • Patent number: 5973931
    Abstract: A printed wiring board and an electronic device using the same with which the formation of cracks in base portions of projecting external electrodes formed on lands on the printed wiring board is certainly prevented. With respect to a printed wiring board 11 having lands 16 formed in a wiring pattern where external electrodes 13 are to be formed and a pattern-protecting film 17 having openings 17a where the external electrodes 13 are to be formed, the opening diameter D1 of the openings 17a in the pattern-protecting film 17 is set greater by a predetermined dimension than the external diameter D2 of the lands 16 and a gap is thereby provided between each of the external electrodes 13 and the pattern-protecting film 17 so that the external electrodes 13 and the pattern-protecting film 17 do not make contact with each other and as a result there is no cracking of the external electrodes 13 caused by differential thermal expansion of the external electrodes 13 and the pattern-protecting film 17.
    Type: Grant
    Filed: November 30, 1998
    Date of Patent: October 26, 1999
    Assignee: Sony Corporation
    Inventor: Hiroyuki Fukasawa
  • Patent number: 5907903
    Abstract: The present invention provides multi-layer multi-chip circuit board comprising at least two ATAB carriers having chips thereon, stacked upon each other in a pyramid configuration and attached to a substrate, thus reducing the required area on the substrate for mounting components to form a circuit board.
    Type: Grant
    Filed: January 8, 1998
    Date of Patent: June 1, 1999
    Assignee: International Business Machines Corporation
    Inventors: Joseph George Ameen, Joseph Funari
  • Patent number: 5905622
    Abstract: A transient voltage surge suppressor (TVSS) receptacle having front and rear, matable casings including a plurality of through openings for receiving the blades of an electrical plug; a plurality of first components which are fixed with respect to said casings; a plurality of second components which are moveable relative to said first components; a plurality of first rigid members formed integrally with the front and rear casings and extending from inside surfaces of each casing to define recesses for receiving the components; and a separator within the periphery of the front and rear casings for insulating one or more of the plurality of first components from each other, said separator including a separator board in a plane substantially parallel with the front and rear walls and intermediate between the front and rear casings and a plurality of partitions extending outwardly from a first surface of the board into the recesses.
    Type: Grant
    Filed: March 23, 1998
    Date of Patent: May 18, 1999
    Assignee: Pass & Seymour, Inc.
    Inventors: David A. Finlay, Sr., Patrick J. Murphy
  • Patent number: 5874516
    Abstract: The present invention is directed to novel poly(arylene ethers), their synthesis and use in electronics applications as low dielectric insulating layers such as spin-on materials in integrated circuits. The polymers have repeating units of the structure: ##STR1## wherein m=0.2 to 1.0; and n=1.0-m; and Ar.sub.1, Ar.sub.2 and Ar.sub.
    Type: Grant
    Filed: July 13, 1995
    Date of Patent: February 23, 1999
    Assignee: Air Products and Chemicals, Inc.
    Inventors: William Franklin Burgoyne, Jr., Lloyd Mahlon Robeson, Raymond Nicholas Vrtis
  • Patent number: 5844782
    Abstract: A printed wiring board and an electronic device using the same with which the formation of cracks in base portions of projecting external electrodes formed on lands on the printed wiring,board is certainly prevented. With respect to a printed wiring board 11 having lands 16 formed in a wiring pattern where external electrodes 13 are to be formed and a pattern-protecting film 17 having openings 17a where the external electrodes 13 are to be formed, the opening diameter D1 of the openings 17a in the pattern-protecting film 17 is set greater by a predetermined dimension than the external diameter D2 of the lands 16 and a gap is thereby provided between each of the external electrodes 13 and the pattern-protecting film 17 so that the external electrodes 13 and the pattern-protecting film 17 do not make contact with each other and as a result there is no cracking of the external electrodes 13 caused by differential thermal expansion of the external electrodes 13 and the pattern-protecting film 17.
    Type: Grant
    Filed: March 29, 1996
    Date of Patent: December 1, 1998
    Assignee: Sony Corporation
    Inventor: Hiroyuki Fukasawa
  • Patent number: 5844297
    Abstract: This interconnect chip provides the function of an antifuse device. The interconnect chip is initially disconnected. Application of a high voltage applied across two terminals on the chip causes intrinsic polysilicon, which serves as an insulator between the connections to break down and form a reliable short circuit between the pads by redistribution of impurities from the layers above and below the intrinsic polysilicon.
    Type: Grant
    Filed: September 26, 1995
    Date of Patent: December 1, 1998
    Assignee: Symbios, Inc.
    Inventors: Harold S. Crafts, Maurice M. Moll
  • Patent number: 5818699
    Abstract: An approximately lead-free mounting pad is formed on a first surface of a substrate having wiring circuits, and an electronic element having an approximately lead-free electrode is face-down mounted on the first surface. An approximately lead-free bump is formed on the approximately lead-free electrode of an electronic element. Mounting pads and approximately lead-free bumps are electrically and mechanically connected to each other by approximately lead-free conductive resin. An approximately lead-free sealing pattern is formed at the area which encloses the electronic element mounted area, of the first surface of the substrate. A weld ring made of Kovar is brazed onto the sealing pattern with approximately lead-free solder. The opening edge of a sealing cap made of Kovar disposed opposite to the weld ring and the weld ring are bonded at the deposited zone by welding.
    Type: Grant
    Filed: July 3, 1996
    Date of Patent: October 6, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshitaka Fukuoka
  • Patent number: 5789121
    Abstract: The present invention provides a method of ablative photodecomposition and forming metal pattern which attains high resolution, is convenient, and employs non-halogenated solvents. The present invention is directed to a process for forming a metal pattern, preferably circuitization on an organic substrate, preferably on a circuit board or component thereof, which comprises coating the substrate with an ablatively-removable coating comprising a polymer resin preferably an acrylate polymer resin and preferably an ultraviolet absorber. A pattern is formed in the polymer coating corresponding to the desired metal pattern by irradiating at least a portion of the polymer coating with a sufficient amount of ultraviolet radiation to thereby ablatively remove the irradiated portion of the polymer coating. Next the patterned substrate is coated with a conductive metal paste to define the metal pattern, and the conductive metal paste is cured.
    Type: Grant
    Filed: June 20, 1997
    Date of Patent: August 4, 1998
    Assignee: International Business Machines Corporation
    Inventors: Douglas Adam Cywar, Charles Robert Davis, Thomas Patrick Duffy, Frank Daniel Egitto, Paul Joseph Hart, Gerald Walter Jones, Edward McLeskey
  • Patent number: 5780145
    Abstract: A molding resin composition containing, in a resin, a filler comprising a globular powder of which mean particle diameter is not smaller than 0.1 .mu.m and not greater than 1.5 .mu.m (x component), a globular powder of which mean particle diameter is not smaller than 2 .mu.m and not greater than 15 .mu.m (y component) and a globular powder of which mean particle diameter is not smaller than 20 .mu.m and not greater than 70 .mu.m (z component), wherein proportions of the x, y and z components based on the total volume of x, y and z components are not smaller than 10% by volume and not greater than 24% by volume, not smaller than 0.1% by volume and not greater than 36% by volume and not smaller than 57% by volume and not greater than 76% by volume, exhibits an excellent fluidity even when loaded with a high percentage of filler. Further, their cured products are lowered in the moisture absorption and thermal expansion coefficient of which increases result from the resin itself present in the cured product.
    Type: Grant
    Filed: June 30, 1997
    Date of Patent: July 14, 1998
    Assignee: Sumitomo Chemical Company, Limited
    Inventors: Yasuhiro Hirano, Masatsugu Akiba, Yutaka Shiomi, Noriaki Saito
  • Patent number: 5776662
    Abstract: To inhibit the migration of conductive layers in a multilayer chip carrier, e.g., a multilayer printed circuit board, an optically cured layer 13, which is an anti-migration layer, is formed in an insulating layer 12 located between a first conductive layer 8 and a second conductive layer 6. Such a structure is formed by thinning, e.g., grinding down, a first insulating layer, leaving about half the thickness of the first insulating layer. This first insulating layer is selectively optically irradiated with actinic radiation to form an optically cured layer. Via holes are etched into the non-irradiated portions of the first insulating layer. Thereafter, a second insulating layer is formed on the first insulating layer, and it too is selectively optically irradiated with actinic radiation. Via holes are etched into the non-irradiated portions of the second insulating layer, directly over the via holes in the first insulating layer, and the second insulating layer is also thinned.
    Type: Grant
    Filed: May 14, 1996
    Date of Patent: July 7, 1998
    Assignee: International Business Machines Corporation
    Inventors: Masaharu Shirai, Yutaka Tsukada
  • Patent number: 5745339
    Abstract: The invention relates to a packing element, which can be used for packing and arranging one or more electric components of an appliance, depending on the case together with the same or similar packing elements; the packing element (1,3,4) has at least one current-conducting or light-conducting conducting track (10,11,12,17,18,43,44). Moreover, the invention relates to a device such as a Personal Computer in which this packing element is used.
    Type: Grant
    Filed: April 7, 1997
    Date of Patent: April 28, 1998
    Inventors: Gundokar Braumann, Ralf H. F. Seitz
  • Patent number: 5740001
    Abstract: A patient monitoring/signal processing module with increased electrical isolation is disclosed. The combination of an inner isolation piece and an isolation film provide signal isolation and electrical over-voltage protection between a lower, isolated portion of the unit defined by a lower housing and the isolation piece and an upper, non-isolated portion of the unit, defined by an upper housing and the isolation piece, increasing the module's ability to survive an over-voltage condition without damage to itself or to the patient to whom it is coupled. The combination of the isolation film and the isolation piece results in a much thinner module than would otherwise have been necessary to achieve the same levels of signal and electrical isolation.
    Type: Grant
    Filed: June 24, 1996
    Date of Patent: April 14, 1998
    Assignee: Hewlett-Packard Company
    Inventors: Erwin Flachslaender, Matthias Muehle, Wolfgang Kehrer
  • Patent number: 5723205
    Abstract: A multilayer rigid flex printed circuit board, wherein the board laminate comprises a double-sided basestock composite, formed by laminating two conducting sheets (12 and 14) to an insulating layer, said insulator layer contacting a flexible core (20), a second insulator layer (24 and 26) affixed to each side of the basestock, said insulator having a cutout region proximate to the flexible core of the basestock composite, a flexible layer (28 and 30) affixed to said cutout regions with an adhesive, wherein said flexible layer contacts the conducting layers and abuts and overlaps a portion of the second insulator layer such that upon stacking of the board laminate a hollow region (32) is produced as between the stacked laminate sections.
    Type: Grant
    Filed: September 6, 1996
    Date of Patent: March 3, 1998
    Assignee: Teledyne Industries, Inc.
    Inventors: Lee J. Millette, A. Roland Caron, Joseph A. Thoman
  • Patent number: 5695872
    Abstract: A glued connection suitable for attaching high power electronic components to a mounting location, such as on a cooling element, has an electrically insulating base layer of unfilled adhesive applied onto at least one surface of the parts to be glued. An adhesive filled with an electrically insulating powder that has good thermal conductivity is applied onto at least one part surface. Grains of the powder puncture the base layer, and the thickness of the glued connection thus essentially corresponds to the size of the grains.
    Type: Grant
    Filed: January 12, 1995
    Date of Patent: December 9, 1997
    Assignee: Siemens Aktiengesellschaft
    Inventors: Karl-Heinz Ideler, Dieter Dlugosch, Winfried Arz
  • Patent number: 5677045
    Abstract: A laminate capable of mounting semiconductor elements thereon; comprising an insulating layer which is constituted by a resin portion of sea-island structure and a woven reinforcement. The resin portion of sea-island structure is, for example, such that a resin as islands are dispersed in a resin as a matrix. Thus, the insulating layer exhibits a coefficient of thermal expansion of 3.0.about.10 (ppm/K) in a planar direction thereof and a glass transition temperature of 150.about.300 (.degree.C.). Owing to these physical properties, thermal stresses which the laminate undergoes in packaging the semiconductor elements thereon can be reduced, so that the connections of the laminate with the semiconductor elements can be made highly reliable.
    Type: Grant
    Filed: April 28, 1995
    Date of Patent: October 14, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Akira Nagai, Masatsugu Ogata, Shuji Eguchi, Masahiko Ogino, Toshiaki Ishii, Masanori Segawa, Hiroyoshi Kokaku, Ryo Moteki, Ichiro Anjoh
  • Patent number: 5654701
    Abstract: A data entry module having a keypad responsive to manual activation for generating electrical signals. A shaped mass of material is provided having a processor embedded therein for processing the generated signals. The processor is connected to the keypad so that the generated signals pass from the keypad to the processor. A housing is detachably riveted to the keypad to enclose, and secure to the keypad, the mass of material so that the connection between the keypad and the processor is maintained.
    Type: Grant
    Filed: May 9, 1996
    Date of Patent: August 5, 1997
    Assignee: Dresser Industries, Inc.
    Inventors: Reynold L. Liao, Mohamad Afshar
  • Patent number: 5650592
    Abstract: There is provided a component for use in electronic packaging. The component is a composite having a graphite matrix which is infiltrated with a metal or a metal alloy and the external surfaces of the composite then coated with a metallic layer to provide environmental and mechanical protection. The packaging components are lightweight, have a coefficient of thermal expansion close to that of a silicon based integrated circuit device and further, have a high coefficient of thermal conductivity.
    Type: Grant
    Filed: April 5, 1993
    Date of Patent: July 22, 1997
    Assignee: Olin Corporation
    Inventors: Harvey Cheskis, Deepak Mahulikar
  • Patent number: 5571608
    Abstract: An embedded core laminate including a conductive reference plane interposed between two insulation layers, and further interposed between two conductive layers. The assembly is laminated using standard temperature and pressure laminating procedures. Holes for interconnect vias are preferably drilled into the reference plane before laminating. The resulting embedded core laminate has three conductive layers with relatively uniform separation, insuring improved impedance control on each PCB (printed circuit board). Since uniform separation is maintained from one PCB to another, multiple PCBs connected together using embedded core laminates according to the present invention allows minimum cross-talk and characteristic impedance variations from one PCB to the next.
    Type: Grant
    Filed: September 5, 1995
    Date of Patent: November 5, 1996
    Assignee: Dell USA, L.P.
    Inventor: N. Deepak Swamy
  • Patent number: 5562971
    Abstract: A multilayer printed wiring board comprising a plurality of interlaminar insulating layers, a plurality of insulating circuit boards having circuits formed on the insulating substrates, and via holes for making electrical connection between two or more layers of circuits, wherein the difference between the glass transition point of an interlaminar insulating layer and that of the adjoining insulating substrate is not greater than 60.degree. C., is proof against exfoliation due to heat history of the board and has high reliability of insulation and through-hole connection.
    Type: Grant
    Filed: April 7, 1995
    Date of Patent: October 8, 1996
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Yoshiyuki Tsuru, Shigeharu Arike, Takashi Sugiyama, Shinjirou Miyashita, Takayuki Suzuki
  • Patent number: 5500628
    Abstract: A double-sided oscillator package (200) is provided. The package (200) has an open-top receptacle (212) adapted to receive an electronic component and an open-bottom receptacle (214) adapted to receive at least a piezoelectric element and a cover, forming a hermetic environment. The electronic component (226) and piezoelectric element (234), can be suitably connected to the package (200). The package (200) is designed to be mass-producable, and is compact, easily surface mounted and provides a narrow profile.
    Type: Grant
    Filed: January 24, 1995
    Date of Patent: March 19, 1996
    Assignee: Motorola, Inc.
    Inventor: Thomas Knecht
  • Patent number: 5497027
    Abstract: A three dimensional logic cube comprises a base plate having two vertically mounted backplanes attached thereto. A plurality of horizontally stacked substrates are coupled by connectors to the backplanes, with enough clearance between adjacent substrates to ensure heat dissipating air or fluid flow between the substrates. Typically, the substrates are multi-chip modules having a plurality of logic and interconnect chips attached at die mounting locations. Preferably, the logic and interconnect chips are attached to the substrate using flip TAB frames. The substrate includes a pattern interconnect for connecting together all of the chips. The logic chip is based on a standard 10K-50K gate array design with 100 micron pad spacing. The interconnect chip uses an interconnect pattern to connect the logic chips. The interconnect chip uses a lead placement identical to the logic chip, so that a single TAB frame can be used for both chips.
    Type: Grant
    Filed: November 30, 1993
    Date of Patent: March 5, 1996
    Assignees: AT&T Global Information Solutions Company, Hyundai Electronics America, Symbios Logic Inc.
    Inventor: Harold S. Crafts
  • Patent number: 5440172
    Abstract: An apparatus comprises a thermal energy generating device and a thermal energy dissipating device having a reduced thermal resistance of the interface between the two. The reduction is achieved by interposing a xylylene polymer layer between the two contact surfaces and applying a surface pressure sufficient to deform the xylylene polymer layer into the surface irregularities of the two surfaces. A reduction in the thermal resistance comparable to that which may be achieved by the use of a silicone grease or an indium foil may be realized if the layer is kept below eight times the air gap mean thickness caused by the surface irregularities. Layer thicknesses beyond this will serve to insulate or increase the thermal resistance between the two surfaces.
    Type: Grant
    Filed: June 28, 1993
    Date of Patent: August 8, 1995
    Assignee: Sundstrand Corporation
    Inventor: Thomas A. Sutrina
  • Patent number: 5239448
    Abstract: A method of reducing the area of MCMs that are integral to a flexible carrier is provided. A locally complex area, i.e. multilayer MCM carrier is constructed on a flex carrier, along with other components to form a subsystem. The flex carrier provides the interface between the MCM and the system that is utilizing the function. Also, the flex carrier will receive non-complex portions of the function, e.g. low I/O devices, not required to be mounted on the complex area (MCM) of the subsystem. The locally complex functional area will contain the high performance DCA mounted components, such as custom ASICs, processors, high frequency analog parts and other high I/O chips. The MCM on flex is constructed by obtaining an appropriate flexible carrier, such as a dielectric material having electrically conductive signal lines circuitized on both sides.
    Type: Grant
    Filed: October 28, 1991
    Date of Patent: August 24, 1993
    Assignee: International Business Machines Corporation
    Inventors: Charles T. Perkins, Gustav Schrottke