With Specific Dielectric Material Or Layer Patents (Class 361/746)
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Patent number: 8338935Abstract: A thermally enhanced electronic package comprises a chip, a substrate, an adhesive, and an encapsulation. The adhesive or the encapsulation is mixed with carbon nanocapsules. The substrate includes an insulation layer and a wiring layer formed on the substrate. The adhesive covers the chip and the substrate. The chip is electrically connected to the wiring layer. The encapsulation covers the chip and the substrate.Type: GrantFiled: May 26, 2011Date of Patent: December 25, 2012Assignee: Chipmos Technologies Inc.Inventors: An Hong Liu, David Wei Wang
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Publication number: 20120293965Abstract: A manufacturing method for a component built-in module, including: forming, in a sheet member including resin, a via hole filled up with a conductive paste, a cavity in which an electronic component is to be built, and an adjustment space; and performing a heat press allowing the sheet member to abut against a substrate on which the electronic component has been mounted, wherein the adjustment space is formed so that a flow vector of the resin in a neighborhood of the via hole during the heat press, which is directed toward the electronic component, is cancelled by a flow vector of the resin in a neighborhood of the via hole during the heat press, which is directed toward the adjustment space.Type: ApplicationFiled: May 16, 2012Publication date: November 22, 2012Applicant: Panasonic CorporationInventors: Shozo OCHI, Yoshitake Hayashi, Kazuo Ohtani, Yosuke Maeba
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Patent number: 8309210Abstract: A laminate for a printed wiring board (PWB) in which the laminate has a resin system containing a binder. The binder is made of ultra-fine binding particles that reinforce the resin system thereby reducing adhesive and cohesive failure of the laminate. The particles in addition to reducing occurrences such as pad cratering, eyebrowing, and tail-cracking, have the benefits of increasing thermal heat transfer and reducing resin shrinkage. The particles are preferably the same material as a reinforcing material contained in the laminate which can be a woven glass.Type: GrantFiled: September 13, 2010Date of Patent: November 13, 2012Assignee: Rockell Collins, Inc.Inventor: Roy M. Keen
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Patent number: 8304660Abstract: A fully reflective and highly thermoconductive electronic module includes a metal bottom layer, a transparent ceramic layer and a patterned metal wiring layer. The metal bottom layer has a lower reflective surface. The transparent ceramic layer has an upper surface and a lower surface. The lower surface of the transparent ceramic layer is bonded to the lower reflective surface of the metal bottom layer. The metal wiring layer is bonded to the upper surface of the transparent ceramic layer. The lower reflective surface reflects a first light ray, transmitting through the transparent ceramic layer, to the upper surface of the transparent ceramic layer. A method of manufacturing the fully reflective and highly thermoconductive electronic module is also disclosed.Type: GrantFiled: April 29, 2010Date of Patent: November 6, 2012Assignee: National Taiwan UniversityInventors: Wei-Hsing Tuan, Shao-Kuan Lee
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Patent number: 8259454Abstract: An electronic component includes a base insulative layer having a first surface and a second surface; at least one electronic device having a first surface and a second surface, wherein the electronic device is secured to the base insulative layer; at least one I/O contact located on the first surface of the electronic device; and a frame panel defining an aperture, wherein the electronic device is disposed within the aperture, and the frame panel is a multi-functional structure having a first region comprising a first material, wherein a surface of the first region secures to the base insulative layer; and a second region comprising a second material, wherein the first material and the second material differ from each other and have differing adhesability to the base insulative layer.Type: GrantFiled: April 14, 2008Date of Patent: September 4, 2012Assignee: General Electric CompanyInventors: Raymond Albert Fillion, Donald Stephen Bitting, Daniel Lee Abraham
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Publication number: 20120218721Abstract: A method of manufacturing a component built-in module includes a step of preparing a sheet metal; a step of providing a conductive thick-film pad over one main surface of the sheet metal by applying and curing a conductive paste; a step of providing a joining material over the conductive thick-film pad; a step of mounting a chip component onto the conductive thick-film pad with the joining material interposed therebetween; a step of providing a resin layer over the one main surface so as to cover the chip component; and a step of forming a surface electrode by patterning the sheet metal.Type: ApplicationFiled: May 9, 2012Publication date: August 30, 2012Applicant: MURATA MANUFACTURING CO., LTD.Inventor: Shigeo NISHIMURA
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Patent number: 8223472Abstract: A capacitor having at least one electrode pair being separated by a dielectric component, with the dielectric component being made of a polymer such as a norbornylene-containing polymer with a dielectric constant greater than 3 and a dissipation factor less than 0.1 where the capacitor has an operating temperature greater than 100° C. and less than 170° C.Type: GrantFiled: November 14, 2008Date of Patent: July 17, 2012Assignee: Sandia CorporationInventors: Shawn M. Dirk, David R. Wheeler
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Publication number: 20120176751Abstract: An electronic component module includes a substrate including a first electrode pattern and a first resist pattern on a first main surface thereof, a first electronic component mounted on the first main surface via the first electrode pattern, and a component-embedding resin layer provided on the first main surface so as to embed the first electronic component therein, and including, in an inside portion or a lateral portion thereof, an interlayer connection conductor connecting the first electrode pattern and an external connection electrode pattern disposed on a surface of the component-embedding resin layer to each other. The first electrode pattern and the first resist pattern are arranged so that the first resist pattern is disposed on top of a circumferential portion of the first electrode pattern.Type: ApplicationFiled: March 9, 2012Publication date: July 12, 2012Applicant: MURATA MANUFACTURING CO., LTD.Inventors: Norio SAKAI, Mayuko NISHIHARA
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Publication number: 20120120613Abstract: An electronic module 10 includes: a circuit board 12 having a first surface and a second surface opposite the first surface; and a plurality of electronic components 14 mounted thereon. The electronic components 14 are sealed at the first surface of the circuit board 12, with a mold body 16 composed of a resin composition. A shield layer 28 is formed on the surface of the mold body 16. The glass transition temperature of a resin included in the mold body 16 is higher than the glass transition temperatures of resins included in the circuit board 12 and the shield layer 28, respectively. The modulus of elasticity of the mold body at 25° C. is 10 to 18 GPa, and the thickness of the circuit board is 0.3 to 1.0 mm.Type: ApplicationFiled: July 15, 2010Publication date: May 17, 2012Applicant: PANASONIC CORPORATIONInventors: Ryo Kuwabara, Atsushi Yamaguchi, Masahiro Ono, Hidenori Miyakawa
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Patent number: 8178191Abstract: A multilayer wiring board includes a core insulating layer with a first conductive wiring, a first insulating layer with a softening temperature lower than the core insulating layer, and a second insulating layer formed on the core insulating layer through the first insulating layer, the second insulating layer with a second conductive wiring electrically connected to the first conductive wiring and a softening temperature higher than the first insulating layer. The first insulating layer is mainly formed of a liquid crystal polymer. The core insulating layer and the second insulating layer are mainly formed of a polyimide resin or a bismaleimide triazine resin. The first conductive wiring and the second conductive wiring are electrically connected through a conductive via formed penetrating through the first insulating layer and the second insulating layer in a thickness direction.Type: GrantFiled: June 13, 2008Date of Patent: May 15, 2012Assignee: Hitachi Cable, Ltd.Inventors: Shigeo Nishino, Hiroyuki Takasaka, Nagayoshi Matsuo, Hiroyuki Okabe
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Patent number: 8178192Abstract: The present invention provides a ceramic green sheet with a thin flat plate shape obtained by molding and solidifying a ceramic slurry, which contains a ceramic powder, dispersion medium, and gelling agent, into a thin flat plate. The ceramic green sheet partially includes a body that is obtained by molding and solidifying a conductor paste, which becomes a conductor later, and the body is exposed on a part of each of the both surfaces of the sheet. Plural ceramic green sheets described above are produced. The plural ceramic green sheets are successively stacked and press-bonded in the thickness direction in such a manner that the bodies included in the respective sheets are connected to each other for all combinations of the adjacent two sheets. As a result, a ceramic green sheet laminate is formed, which includes one body that is obtained by connecting the bodies included in the respective sheets.Type: GrantFiled: February 25, 2009Date of Patent: May 15, 2012Assignee: NGK Insulators, Ltd.Inventors: Kunihiko Yoshioka, Koji Kimura, Satoshi Ishibashi
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Publication number: 20120106095Abstract: An electronics module has a flexible substrate having conductors, an array of functional components on the substrate, the functional components arranged to contact at least one conductor, and perforations in the flexible substrate, the perforations arranged to increase stretchability of the flexible substrate, the conductor arranged around the perforation and the functional components arranged to one of reside between the perforations or partially cover the perforations. A method of manufacturing a flexible electronics module involves mounting at least two functional components onto a flexible substrate, forming electrical interconnects configured to provide connection between the two functional components, and perforating the flexible substrate with cuts configured to increase stretchability of the substrate.Type: ApplicationFiled: October 29, 2010Publication date: May 3, 2012Applicant: PALO ALTO RESEARCH CENTER INCORPORATEDInventor: Jurgen H. Daniel
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Publication number: 20120075812Abstract: In various embodiments, a chip module may include a substrate; electronic components, the electronic components being arranged on a first side of the substrate; and an insulating layer, which is applied to the first side of the substrate and to the electronic components, contact openings being arranged in the insulating layer which permit electrical contacting of the electronic components; and an electrically conducting layer being arranged on the insulating layer and in the contact openings, which connects the electronic components electrically to one another.Type: ApplicationFiled: September 23, 2011Publication date: March 29, 2012Applicant: INFINEON TECHNOLOGIES AGInventor: Wolfram Hable
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Patent number: 8145258Abstract: A radio communication apparatus includes housings that are connected via a hinge unit in an openable/closeable manner, and circuit boards in the housings. The circuit boards are connected via circuit connecting lines functioning as an inductor. One end of the hinge unit is connected to an end portion of the housing and the other end thereof is connected to a portion located farther inside than an end portion of the housing. When the housings are unfolded, a region extending from the portion to the end portion of the housing overlaps a region near the end portion of the housing in a projection domain. A high dielectric member is provided in this overlapped region, and a capacitor is constituted by the high dielectric member and ground areas.Type: GrantFiled: September 9, 2009Date of Patent: March 27, 2012Assignee: Murata Manufacturing Co., Ltd.Inventors: Jin Sato, Kengo Onaka
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Patent number: 8119922Abstract: Two panel-sized fully populated printed wiring board assemblies formed together, with an anisotropic epoxy that provides electrical connection for RF signals and DC supplies without the need for wirebonds, mechanical interconnects or solder balls.Type: GrantFiled: September 30, 2008Date of Patent: February 21, 2012Assignee: The Boeing CompanyInventor: Robert T. Worl
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Publication number: 20120026696Abstract: An ungrounded type multilayer packaging with a reduced energy of electrostatic discharge for packaging used in a combustible environment. The packaging comprises a non-conductive multilayer packaging material containing at least one polymeric thermoplastic electrostatic dissipating layer, to give an electrostatic discharge energy attenuation of more than 40 dB.Type: ApplicationFiled: May 5, 2009Publication date: February 2, 2012Applicant: IONPHASE OYInventors: Jukka Hillberg, Jouni Hillberg, Jyri Nieminen
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Publication number: 20110273851Abstract: A circuit board includes a substrate having a first surface and a second surface on an opposite side of the first surface. A hole is provided in the substrate so as to penetrate from the first surface to the second surface. A recess portion is formed in the second surface and has a bottom larger than a cross-section area of the hole. The hole is exposed on the bottom of the recess portion.Type: ApplicationFiled: November 6, 2009Publication date: November 10, 2011Applicant: PANASONIC CORPORATIONInventor: Seiji Yamaguchi
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Patent number: 7998560Abstract: A multilayer ceramic substrate includes an inner layer portion and surface portions that sandwich the inner layer portion in the stacking direction and have an increased transverse strength because of the surface layer portion having a thermal expansion coefficient less than that of the inner layer portion. At least one of the surface portions covers peripheries of main-surface conductive films arranged on a main surface of an inner portion so as to leave central portions of the main-surface conductive films exposed, so that the main-surface conductive films function as via conductors, thereby eliminating the need to provide a via conductor in the surface portions.Type: GrantFiled: November 7, 2008Date of Patent: August 16, 2011Assignee: Murata Manufacturing Co., Ltd.Inventor: Yasutaka Sugimoto
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Publication number: 20110194260Abstract: A semiconductor package module including a self-assembled organic molecule layer and a method of manufacturing the semiconductor package module is provided. The semiconductor package module may include a module printed circuit board (PCB) having a plurality of metal line patterns and a plurality of mounting pads formed thereon. The semiconductor package may further include an insulation thin film self-assembled on at least one metal line pattern selected from among the plurality of metal line patterns. In order to manufacture the semiconductor package module, the insulation thin film is formed in a manner that the plurality of metal line patterns are formed on the module PCB wherein a plurality of via holes are formed, and then an organic compound is self-assembled on a surface of at least one metal line pattern selected from the plurality of metal line patterns.Type: ApplicationFiled: January 31, 2011Publication date: August 11, 2011Applicant: Samsung Electronics Co., Ltd.Inventors: Jin-san Jung, Joo-han Lee, Jung-chan Cho, Hyun-seok Choi
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Patent number: 7948758Abstract: The invention relates to a circuit board unit and a method for production thereof. The circuit board unit comprises a circuit board topmost laminate with conductive tracks on the upper side for mounting surface-mountable devices. The circuit board topmost laminate features a thickness dimensioned such that the anticipated heat dissipated by the surface-mountable devices is transported from the upper side to the underside of the circuit board laminate to good effect. The circuit board unit further comprises an electrically insulating laminate arranged under the circuit board topmost laminate, inserts made of a material with good heat conductivity and electrical insulation embedded in the electrically insulating laminate at sites below surface-mountable devices with high heat dissipation, and a cooling plate arranged below the electrically insulating laminate and the inserts.Type: GrantFiled: October 25, 2007Date of Patent: May 24, 2011Assignees: Agie Charmilles SA, Charmilles Technologies SAInventors: Ernst Bühler, Rino D'Amario, Reto Knaak
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Publication number: 20110110050Abstract: A structure with electronic component mounted therein includes a wiring board on which an electronic component is mounted at least on its first face, resin provided at least between the electronic component and the wiring board, and a plurality of holes formed in the wiring board at region corresponding to a mounting position of the electronic component. The holes are filled with the resin. This suppresses warpage of the structure with electronic component mounted therein, and also improves reliability by reducing a stress applied to a bonding section between the wiring board and the electronic component.Type: ApplicationFiled: October 21, 2008Publication date: May 12, 2011Inventors: Shigeaki Sakatani, Koso Matsuno, Atsushi Yamaguchi, Hidenori Miyakawa, Mikiya Ueda
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Patent number: 7906732Abstract: Provided is a process for producing a glass plate with a conductive printed wire, which does not require a screen plate for each model, facilitates adjustments for desired heat generation performance or antenna performance, has an excellent adhesion to a glass plate surface, and minimizes surface roughness. The process for producing a glass plate with a conductive printed wire is characterized in that a laminate comprising a layer obtained by electro printing a first conductive toner having a number standard average particle size (D50) of 10 ?m<D50?50 ?m and a layer obtained by electro printing a second conductive toner having a particle size (D50) of 5 ?m?D50?10 ?m is formed on a surface of a glass plate and the glass plate is heated to fire the toners to thereby form a conductive printed wire having a predetermined pattern on the surface of the glass plate.Type: GrantFiled: November 28, 2008Date of Patent: March 15, 2011Assignee: Asahi Glass Company, LimitedInventors: Naoki Okahata, Satoshi Kashiwabara, Kazuo Sunahara, Tomoaki Okada, Katsuhiko Takeda
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Patent number: 7894200Abstract: The present invention provides a printed wiring board with a built-in semiconductor element in which an insufficient or excessive amount of filled sealing material does not affect excellent adhesion of the printed wiring board to an overlying wiring board. The printed wiring board with a built-in semiconductor element comprises a built-in semiconductor element, in which at least the lower surface, the upper surface, or the side surface of the semiconductor element is covered with an insulating film, and an insulating layer is provided in the side and upper portions of the semiconductor element.Type: GrantFiled: November 28, 2006Date of Patent: February 22, 2011Assignees: CMK Corporation, Renesas Eastern Japan Semiconductor, Inc.Inventors: Yutaka Yoshino, Takahiro Shirai, Shinji Kadono, Mineo Kawamoto, Minoru Enomoto, Masakatsu Goto, Makoto Araki, Naoki Toda
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Patent number: 7868451Abstract: A resin sealing semiconductor device (2) having a structure in which a portion to be sealed of components including a plurality of chip mounting board, a semiconductor chip mounted to a front surface of each chip mounting board, and a plurality of leads provided correspondingly to each chip mounting board is embedded in resin molded portions (41 and 42) molded into a generally plate shape, and outer lead portions of the plurality of leads (16 and 17) are led out in line from a side surface at one end in a width direction of the resin molded portions, and back surfaces as exposed surfaces (11u1 to 11w1 and 12u1 to 12w1) of each chip mounting board are placed on one surfaces of the resin molded portions (41 and 42), wherein a plurality of positioning protrusions (50) are provided on one surfaces of the resin molded portions (41 and 42), and a protrusion height of the positioning protrusions is set so that a gap to be filled with insulating resin is formed between each part of the exposed surface of each chip moType: GrantFiled: May 30, 2006Date of Patent: January 11, 2011Assignee: Kokusan Denki Co. Ltd.Inventors: Shuichi Muramatsu, Hidetoshi Suzuki, Tomoyuki Sato, Kazuo Hara
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Publication number: 20100232119Abstract: A method for producing an electronic module, in that at least one first microelectronic component is provided and is electrically connected to a second microelectronic component by a first flip-chip method step; at least one dielectric component is provided which has at least one printed circuit trace, and at least one printed circuit trace of the dielectric component is electrically connected to the second microelectronic component; and the second microelectronic component is electrically connected by a second flip-chip method step to a printed circuit board by way of the printed circuit trace(s) of the dielectric component, in order to avoid vias through a microelectronic component; the invention also relates to a corresponding electronic module.Type: ApplicationFiled: February 19, 2010Publication date: September 16, 2010Inventors: Manuela Schmidt, Axel Franke, Sven Zinober
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Publication number: 20100220448Abstract: A component-containing module includes a core substrate which includes a lower surface including recessed portions and a raised portion, and an upper surface facing the lower surface and which includes a plurality of in-plane conductors, an integrated circuit element arranged at a location which is above the upper surface and which corresponds to the raised portion, a first passive element and a second passive element disposed in the recessed portions of the lower surface, a composite resin layer which underlies the lower surface and which has a flat or substantially flat surface, and an external terminal electrode which is disposed on the flat or substantially flat surface of the composite resin layer and which is electrically connected to the in-plane conductors of the core substrate. The component-containing module enables electronic components, such as integrated circuit elements and passive elements, to be densely arranged and to be reduced in profile and size.Type: ApplicationFiled: May 18, 2010Publication date: September 2, 2010Applicant: MURATA MANUFACTURING CO., LTD.Inventor: Masato NOMURA
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Publication number: 20100202115Abstract: The document describes a circuit board and an electronic module, comprising a conductor-pattern layer, an insulating-material layer supporting the conductor-pattern layer, and at least one component inside the insulating-material layer. The component has a plurality of contact areas and the circuit board or electronic module comprises contact elements between the conductor-pattern layer and contact areas for electrically connecting the conductor-pattern layer and the at least one component such that at least two of the contact elements are in direct contact with a common contact area.Type: ApplicationFiled: February 9, 2010Publication date: August 12, 2010Applicant: Imbera Electronics OyInventors: Risto TUOMINEN, Petteri Palm
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Patent number: 7772689Abstract: It is configured to comprise a semiconductor chip 110, a resin member 106 for forming a cavity 109 in which this semiconductor chip 110 is installed, and wiring 105 constructed of pattern wiring 105b formed so as to be exposed to an upper surface 106b of this resin member 106 and also connected to the semiconductor chip 110 and a post part 105a in which one end is connected to the pattern wiring 105b and also the other end is formed so as to be exposed to a lower surface 106a of the resin member 106.Type: GrantFiled: September 6, 2006Date of Patent: August 10, 2010Assignee: Shinko Electric Industries Co., Ltd.Inventors: Tsuyoshi Kobayashi, Tetsuya Koyama, Takaharu Yamano
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Patent number: 7595997Abstract: In a multilayer ceramic electronic component, a pedestal portion is provided on a region of a first main surface of a multilayer ceramic body and includes a non-metallic inorganic powder and a resin so that the pedestal portion is fixed to the first main surface with at least the resin, the multilayer ceramic body being formed by stacking a ceramic base material layer and a shrinkage-inhibiting layer having a predetermined conductor pattern. Also, a via hole conductor is disposed in the pedestal portion so that one of the end surfaces is exposed in a surface of the pedestal portion, and a surface mounting-type electronic component such as a semiconductor element is connected, through a conductive binder, to the one of the end surfaces of the via hole conductor exposed in the surface of the pedestal portion. A resin is provided between the surface mounting-type electronic component and the pedestal portion, the resin having the same composition as in the resin of the pedestal portion.Type: GrantFiled: July 1, 2008Date of Patent: September 29, 2009Assignee: Murata Manufacturing Co., Ltd.Inventors: Masato Nomiya, Norio Sakai, Mitsuyoshi Nishide
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Patent number: 7582964Abstract: A semiconductor package for power transistors and the like has a heat sink flange with at least one die mounted thereon, a non-ceramic based window frame mounted thereon adjacent the die, and a plurality of leads mounted on the window frame and electrically coupled to the die by wire bonds. The non-ceramic based window frame is thermally matched to copper or other highly conductive material typically used for the flange, to facilitate assembly of the semiconductor package at high temperatures. The non-ceramic based window frame is flexible and is thermally matched to the highly conductive flange so as to expand and contract at a rate similar to the flange to prevent failure during assembly of the semiconductor package. The non-ceramic based material of the window frame includes a matrix of principally organic material, such as polytetrafluorethylene, filled with fibers which may be glass fibers or ceramic fibers.Type: GrantFiled: November 19, 2007Date of Patent: September 1, 2009Assignee: Kyocera America, Inc.Inventors: Jeffrey Venegas, Paul Garland, Joshua Lobsinger, Linda Luu
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Publication number: 20090201651Abstract: A resin sealing semiconductor device (2) having a structure in which a portion to be sealed of components including a plurality of chip mounting board, a semiconductor chip mounted to a front surface of each chip mounting board, and a plurality of leads provided correspondingly to each chip mounting board is embedded in resin molded portions (41 and 42) molded into a generally plate shape, and outer lead portions of the plurality of leads (16 and 17) are led out in line from a side surface at one end in a width direction of the resin molded portions, and back surfaces as exposed surfaces (11u1 to 11w1 and 12u1 to 12w1) of each chip mounting board are placed on one surfaces of the resin molded portions (41 and 42), wherein a plurality of positioning protrusions (50) are provided on one surfaces of the resin molded portions (41 and 42), and a protrusion height of the positioning protrusions is set so that a gap to be filled with insulating resin is formed between each part of the exposed surface of each chip moType: ApplicationFiled: May 30, 2006Publication date: August 13, 2009Inventors: Shuichi Muramatsu, Hidetoshi Suzuki, Tomoyuki Sato, Kazuo Hara
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Publication number: 20090185354Abstract: A heat radiating structure for an electronic module and an electronic device having the same structure thereon. The heat radiating structure is formed at the bottom of the electronic module to release the generated heat from the electronic module, and includes an impact absorber, which absorbs impact transferred from the outside. A heat radiating sheet is formed with a plurality of the multi-layered heat conductive sheets and is in contact with the bottom of the electronic module by covering the outside of the impact absorber.Type: ApplicationFiled: November 24, 2008Publication date: July 23, 2009Inventors: Jung-Kee LEE, Mun-Kue Park, Du-Chang Heo
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Patent number: 7532481Abstract: A base plate for a power module includes: a metal plate, a ceramic base plate joined to the metal plate, and a release agent which includes boron provided in a joint surface between the metal plate and the ceramic base plate. A remaining amount of the release agent is less than 5, as an amount of boron measured by fluorescence X-ray analysis, where the amount of boron is defined as a value obtained by an expression: (a peak height of B-K?/a peak height of X-K?) x 100000 and a crystal grain straining region in the joint surface is equal to or less than 40%, or an amount of crystal grain straining in the joint surface is equal to or less than 0.03%.Type: GrantFiled: April 4, 2005Date of Patent: May 12, 2009Assignee: Mitsubishi Materials CorporationInventors: Toshiyuki Nagase, Yoshiyuki Nagatomo, Kazuaki Kubo, Takeshi Negishi
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Patent number: 7301755Abstract: Power converters such as power modules configured as inverters employ modularized approaches. In some aspects, semiconductor devices are thermally coupled directly to thermally conductive substrates without intervening dielectric or insulative structures. Additionally, or alternatively, semiconductor devices are thermally coupled to thermally conductive substrates with relatively large surface areas before heat transferred from the semiconductor devices encounters a dielectric or electrically insulating structure with correspondingly high thermal impedance.Type: GrantFiled: December 13, 2004Date of Patent: November 27, 2007Assignee: Siemens VDO Automotive CorporationInventors: Pablo Rodriguez, Douglas K. Maly, Ajay V. Patwardhan, Kanghua Chen, Sayeed Ahmed, Gerardo Jimenez, Fred Flett
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Patent number: 7298046Abstract: A semiconductor package for power transistors and the like has a heat sink flange with at least one die mounted thereon, a non-ceramic based window frame mounted thereon adjacent the die, and a plurality of leads mounted on the window frame and electrically coupled to the die by wire bonds. The non-ceramic based window frame is thermally matched to copper or other highly conductive material typically used for the flange, to facilitate assembly of the semiconductor package at high temperatures. The non-ceramic based window frame is flexible and is thermally matched to the highly conductive flange so as to expand and contract at a rate similar to the flange to prevent failure during assembly of the semiconductor package. The non-ceramic based material of the window frame includes a matrix of principally organic material, such as polytetrafluoroethylene, filled with fibers which may be glass fibers or ceramic fibers.Type: GrantFiled: January 10, 2003Date of Patent: November 20, 2007Assignee: Kyocera America, Inc.Inventors: Jeffrey Venegas, Paul Garland, Joshua Lobsinger, Linda Luu
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Patent number: 7230187Abstract: A multi-layer printed wire board (PWB) structure optimized for improved drop reliability, reliable electrical connections under thermal load, and minimal thickness is provided, along with a mobile terminal, including the PWB. The PWB includes alternating conductive layers and insulative layers. The outermost three layers form an interconnect structure constructed of two conductive layers surrounding an insulative-coated conductive layer. The thicknesses of the various layers are optimized to have an increased resistance to mechanical shock resulting from, for instance, a drop onto a hard surface. In addition, the optimized PWB structure has a minimized thickness and an improved resistance to connection failures resulting from cyclical thermal loads.Type: GrantFiled: December 22, 2003Date of Patent: June 12, 2007Assignee: Nokia CorporationInventors: Liangfeng Xu, Tommi Reinikainen, Arni Kujala, Wei Ren, Ian Niemi, Ilkka Kartio
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Patent number: 7026547Abstract: A semiconductor device (10) includes a semiconductor component integrated in a semiconductor substrate and a conductive pad (110) arranged on top of the semiconductor device (10). The conductive pad is electrically connected with the semiconductor component. The pad is arranged for connecting the semiconductor device (10) externally. A dielectric material (310) is positioned between the conductive pad (110) and a buried conductive layer (20) of the semiconductor device. The dielectric material (310) comprises a stress blocking structure.Type: GrantFiled: January 21, 2005Date of Patent: April 11, 2006Assignee: Infineon Technologies AGInventors: Klaus Goller, Stefan Eckert, Anja Oesinghaus
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Patent number: 6958527Abstract: A wiring board includes a substrate, and an interconnect pattern which is formed on the substrate and includes a land. A penetration hole, which exposes the substrate, is formed in the land. The penetration hole is formed in a region along a periphery of the land.Type: GrantFiled: September 4, 2003Date of Patent: October 25, 2005Assignee: Seiko Epson CorporationInventor: Terunao Hanaoka
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Patent number: 6924973Abstract: The light emitting diode assembly for an illuminated sign is disclosed having an enhanced waterproofs function and an enhanced durability. The light emitting diode assembly includes a case being open upwards, in which a connecting recess is formed on upper portions of both sides of the case. A printed circuit board is installed in the case and being mounted on upper sides of a plurality of light emitting diodes. The hollow cap is coupled in the connecting recess of the case, in which a plurality of wires passes through the cap. A synthetic resin material for covering the printed circuit board, the cap and the light emitting diode, is filled in the case. In this structure, the light emitting diode assembly can prevent the printed circuit board, transformer and the light emitting diode from being damaged by using an epoxy resin.Type: GrantFiled: August 27, 2003Date of Patent: August 2, 2005Assignee: ATTO Display Co., Ltd.Inventor: Sun-Tai Kim
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Patent number: 6822873Abstract: An electronic device such as a semiconductor pressure sensor is provided which has a buffer disposed within a resinous casing. Terminals extend through the casing and connect electrically with an electronic element mounted on the casing through wires. The buffer is made of a material having a coefficient of thermal expansion smaller than that of the body of the casing, thereby decreasing undesirable movement of the terminals leading to fatigue of the wires which arises from a change in temperature of the casing. This minimizes a drop in mechanical strength of the wires caused by thermal cycling to which the casing is subjected.Type: GrantFiled: February 27, 2003Date of Patent: November 23, 2004Assignee: Denso CorporationInventor: Kazuhiko Koga
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Patent number: 6805940Abstract: A method for making an electrically conductive pattern, including: (a) depositing on a substrate a metal powder composition consisting essentially of at least one metal powder, wherein the substrate is selected from the group consisting of paper and materials that are at least about 10% compressible; and (b) densifying the composition to form a conductive pattern on the substrate.Type: GrantFiled: September 10, 2001Date of Patent: October 19, 2004Assignee: 3M Innovative Properties CompanyInventors: David C. Koskenmaki, David W. Kuhns
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Patent number: 6803114Abstract: The invention involves a card, including a card body including at least three laminated plastic layers directly superimposed on each other, a second layer being a layer in polyethylene terephthalate glycol placed between a first layer and a third layer, the first layer and third layer being of a chemical nature different from that of said second layer, and an electronic module being incorporated in a cavity of the card body, the module including an integrated circuit, where the thickness of the second layer is of the same order of magnitude as that of the first and third layers, and wherein the cavity extends into the second layer from the first layer.Type: GrantFiled: May 13, 2002Date of Patent: October 12, 2004Assignee: Schlumberger SystemesInventors: Denis Vere, Eric Daniel
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Patent number: 6784765Abstract: A mulitlayer ceramic device improves device functionality, reduces overall device size and profile, makes manufacturing easier, and improves reliability. A first ceramic layer 1 has a first multilayer circuit pattern 2 electrically connected through via holes 3. A second ceramic layer 2 also has a second multilayer circuit pattern 2 electrically connected through via holes 3. A thermosetting resin sheet 17 is disposed between the first and second ceramic layers. The thermosetting resin sheet has through holes filled with a conductive paste for electrically connecting one of multiple circuit pattern layers in the first ceramic layer with one of multiple circuit pattern layers in the second ceramic layer.Type: GrantFiled: February 24, 2003Date of Patent: August 31, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Toru Yamada, Kazuhide Uriu, Tsutomu Matsumura, Toshio Ishizaki
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Patent number: 6717794Abstract: A composite multilayered ceramic board includes a multilayered ceramic board made of dielectric ceramics, a multilayered ceramic board made of magnetic ceramics and an adhesive layer made of thermosetting resin such as polyimide and the like. In this composite multilayered ceramic board, the dielectric multilayered ceramic board and the magnetic multilayered ceramic board are joined through the adhesive layer.Type: GrantFiled: December 28, 2001Date of Patent: April 6, 2004Assignee: Sanyo Electric Co., Ltd.Inventors: Hideki Yoshikawa, Seiichirou Takahashi
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Publication number: 20040035519Abstract: A microelectronic element is with a connection component having a polymeric body, and a bonding material is provided between contacts on the microelectronic element and conductive features of the connection component. The microelectronic element is heated so as to activate the bonding material, and then cooled, leaving said contacts on said microelectronic element bonded to said conductive features on the connection component. The connection component is maintained at an average temperature below the glass transition temperature of the polymer in the connection component during the heating and cooling steps.Type: ApplicationFiled: August 26, 2003Publication date: February 26, 2004Applicant: Tessera, Inc.Inventors: Masud Beroz, Belgacem Haba, Klaus-Jurgen Wolter
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Patent number: 6690580Abstract: This disclosure describes use of dielectric islands embedded in metallized regions of a semiconductor device. The islands are formed in a cavity of a dielectric layer, as upright pillars attached at their base to an underlying dielectric. The islands break up the metal-dielectric interface and thus resist delamination of metal at this interface. The top of each island pillar is recessed from the cavity entrance by a selected vertical distance. This distance may be varied within certain ranges, to place the island tops in optimal positions below the top surface plane of the dielectric. Metallization introduced into the cavity containing the islands, submerges the island tops to at least a minimum distance to provide a needed minimum thickness of continuous metal. The continuous metal surface serves favorably as a last metal layer for attaching solder or for bump-bonding package to the IC; and also serves as an intermediate test or probe pad in an interior layer.Type: GrantFiled: March 7, 2002Date of Patent: February 10, 2004Assignees: AMD, Inc., Motorola, Inc.Inventors: Cindy K. Goldberg, John Iacoponi
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Patent number: 6650539Abstract: A modular backup power housing consists of at least one module and a base. Additional modules may be stacked to accommodate a larger bank of power cells. Each module has a cuboid frame, multiple top rails and multiple bottom tracks. The top rails and the bottom tracks are attached to top and bottom surfaces of the cuboid frame respectively and mate with the top rails and bottom tracks of adjacent modules or the base. By virtue of the interlocking top rails and bottom tracks, the total height of the modular backup power housing is less than a conventional housing, and the strength and stability of the modular backup power housing is improved.Type: GrantFiled: June 19, 2002Date of Patent: November 18, 2003Assignee: Handsome Electronics Ltd.Inventors: Hsin-An Lin, Kuo-Hsien Tsai
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Patent number: 6613987Abstract: Herein is disclosed an insulating resin composition for a multilayer printed-wiring board, comprising two or more kinds of resins which are different in etching rate by plasma treatment and which are not compatible with each other, so that the surface of the resulting insulating layer can be made uneven by the plasma treatment, whereby the bonding strength of the conductor layer to the said resulting insulating layer can be ensured, and heat resistance and electrically insulating properties required can be satisfied.Type: GrantFiled: March 31, 2000Date of Patent: September 2, 2003Assignee: Ajinomoto Co., Inc.Inventors: Yasuaki Seki, Takashi Ito, Shuji Mochizuki, Kiyonori Furuta, Toshihiko Hatajima
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Patent number: 6570469Abstract: A multilayer ceramic device improves device functionality, reduces overall device size and profile, makes manufacturing easier, and improves reliability. A first ceramic layer has a first multilayer circuit pattern electrically connected through via holes. Also, a second ceramic layer has a second multilayer circuit pattern electrically connected through via holes. A thermosetting resin sheet is disposed between the first and second ceramic layers. The thermosetting resin sheet has through holes filled with a conductive paste for electrically connecting one of multiple circuit pattern layers in the first ceramic layer with one of multiple circuit pattern layers in the second ceramic layer.Type: GrantFiled: June 27, 2001Date of Patent: May 27, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Toru Yamada, Kazuhide Uriu, Tsutomu Matsumura, Toshio Ishizaki
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Publication number: 20030039101Abstract: The present invention relates to a module component for which degradation of electrical properties caused by absorption of moisture in the air can be prevented. An intermediate layer comprises a first layer, a second layer and a core layer. The core layer comprises a material having a higher strength than the first layer and the second layer, has a network structure that extends out in planar fashion, has an outer periphery thereof positioned further to the inside than the outer peripheries of the first layer and the second layer, and is sealed between the first layer and the second layer. An upper layer is laminated on the upper surface of the intermediate layer. A lower layer is laminated on the lower surface of the intermediate layer. Mounted components are mounted on any one of the upper layer and the lower layer.Type: ApplicationFiled: August 14, 2002Publication date: February 27, 2003Applicant: TDK CorporationInventors: Minoru Takaya, Toshikazu Endo