With Particular Conductive Material Or Coating Patents (Class 361/751)
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Patent number: 6060169Abstract: A material and a method for forming a tamper-indicating identification coating are provided. The components of the coating are selected such that the coating exhibits a characteristic absorption spectrum with distinct features in individual regions during Fourier-transform infra-red (FTIR) spectroscopy. The coating components are selected to provide a distinct spectrum while, at the same time, providing a sufficiently complex spectrum such that the coating is difficult to duplicate. Also, a blowing agent in the coating decomposes to change the FTIR spectrum due to the heat associated with resoldering of an out-of-warranty electronic part marked with the identification coating to an in-warranty circuit card. In addition, the coating may contain a fluorophore to reveal the presence of a tamper-indicating identification coating, allowing a manufacturer to check the card by exposure with ultra-violet (UV) light. Further, the coating composition may be changed periodically and tracked to provide a date marker.Type: GrantFiled: November 24, 1997Date of Patent: May 9, 2000Assignee: International Business Machines CorporationInventors: Joseph Paul Kuczynski, David Otto Lewis
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Patent number: 6058021Abstract: A semiconductor element/substrate mounting structure is formed by a first step of covering a resin film over the substrate together with a conductive portion; a second step of pressing and heating so that bumps penetrate through the resin film to come into contact with the conductive portion; and a third step of pressing and heating so that the bumps and the conductive portion become alloyed between the semiconductor element and the substrate.Type: GrantFiled: June 20, 1997Date of Patent: May 2, 2000Assignee: Sharp Kabushiki KaishaInventor: Seiichi Yamamoto
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Patent number: 6054762Abstract: A paste of active metallic brazing material is applied to the entire surface of each side of aluminum nitride or alumina ceramic substrate 1; circuit forming copper plate 3 having a thickness of 0.3 mm is placed in contact with one surface of the substrate and a heat dissipating copper plate 4 having a thickness of 0.25 mm placed in contact with the other surface; the individual members are compressed together and heated at 850.degree. C.Type: GrantFiled: August 25, 1997Date of Patent: April 25, 2000Assignee: Dowa Mining Co., Ltd.Inventors: Masami Sakuraba, Masami Kimura, Junji Nakamura, Masaya Takahara
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Patent number: 6038133Abstract: A circuit component built-in module of the present invention includes an insulating substrate formed of a mixture comprising 70 wt % to 95 wt % of an inorganic filler and a thermosetting resin, a plurality of wiring patterns formed on at least a principal plane of the insulating substrate, a circuit component arranged in an internal portion of the insulating substrate and electrically connected to the wiring patterns, and an inner via formed in the insulating substrate for electrically connecting the plurality of wiring patterns. Thus, a highly reliable circuit component built-in module having high-density circuit components can be obtained.Type: GrantFiled: November 20, 1998Date of Patent: March 14, 2000Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Seiichi Nakatani, Kouichi Hirano
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Patent number: 6033764Abstract: A bumped substrate assembly comprising an alumina substrate a layer of copper on the alumina substrate, and a heterogeneous juncture band between the alumina the copper layer. Copper bumps integrally connected to the copper layer extend therefrom; the copper in the copper layer and the copper bumps is substantially identical. The heterogeneous juncture band has a copper-wetted surface area that is at least about twice the apparent surface area of the copper overlying the first juncture band and consisting essentially of alumina grains unitary with the copper layer and being constituted by finger-like copper protuberances unitary with the copper layer and occupying the space between the alumina grains.Type: GrantFiled: October 14, 1997Date of Patent: March 7, 2000Assignee: Zecal Corp.Inventors: Leon M. Balents, Terry L. Streeter, Kenneth W. Christopher, James S. Morrison, Kalman F. Zsamboky
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Patent number: 6030706Abstract: A intermetal level dielectrics with copolymers of parylene and cyclic siloxances (432, 482) between metal lines plus oxides (450, 490), and vapor deposition method for the copolymerization. Fluorination of the copolymers lowers dielectric constant and increases working temperature.Type: GrantFiled: November 6, 1997Date of Patent: February 29, 2000Assignee: Texas Instruments IncorporatedInventors: Mona Eissa, Justin Gaynor
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Patent number: 6007668Abstract: A TAB (tape automated bonding) tape of high precision is formed without the deformations of its conductor pattern and the like and which is hermetically sealed with resin. The method for producing a TAB tape includes punching required holes, such as a device hole 14 and the like, in a metal plate 10 coated with an insulating adhesive layer 12 over the area where a conductor pattern is to be formed; and forming a required conductor pattern 24 by bonding a conductor metal foil onto the adhesive layer and by etching the conductor metal foil. Thus, the material cost of this TAB tape can be reduced and the production of this tape is facilitated.Type: GrantFiled: November 24, 1997Date of Patent: December 28, 1999Assignee: Shinko Electric Industries Co., Ltd.Inventors: Kotaro Kodani, Kazuo Koyanagi, Kiyokazu Sato
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Patent number: 6005289Abstract: The minimum spacing between wires disposed on a printed circuit board of a printed circuit board ball grid array package is reduced. Wiring layers are narrower than in the prior art because they are not plated and because only one metal layer is plated on the wiring layers. The narrower wiring layers can be formed easily with small spaces between wires.Type: GrantFiled: October 24, 1996Date of Patent: December 21, 1999Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering CorporationInventors: Masaki Watanabe, Akiyoshi Sawai, Yoshikazu Narutaki, Tomoaki Hashimoto, Masatoshi Yasunaga, Jun Shibata, Hiroshi Seki, Kazuhiko Kurafuchi, Katsunori Asai
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Patent number: 6002590Abstract: A circuit board has traces attached to a flexible trace surface such that the traces can be displaced in a direction of thermal expansion of a component attached to the traces without causing the failure of the solder joint between the component and the trace. In one embodiment, the printed circuit board substrate is etched away in areas not covered by the traces such that flexible protuberances are formed from the substrate underneath the traces. In one method for constructing such a circuit board, a conductive layer is deposited on the printed circuit board substrate. The conductive layer is then etched to form conductive traces. The printed circuit board substrate is then selectively etched using the traces as a mask for etching the printed circuit board substrate. In a second printed circuit board embodiment, a flexible layer of a material is deposited onto the printed circuit board substrate. The traces are then formed on top of the flexible layer.Type: GrantFiled: March 24, 1998Date of Patent: December 14, 1999Assignee: Micron Technology, Inc.Inventors: Warren M. Farnworth, Kevin G. Duesman
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Patent number: 5995370Abstract: An effective heat-sinking arrangement is realized for circuit elements used in a portable type information terminal having a small restricted space therein. Wherein, a first substrate has a cavity formed in its insulating layer extending to an earthing layer and filled with a silver paste to form a seat for mounting a CPU that can thus thermally contact with the earthing layer, and a second substrate has a cavity formed in an insulating layer in which cavity a heat-conducting cushion bonded to the top of the CPU is fitted for creating the heat-conductive route between the CPU and the earthing layer of the second substrate.Type: GrantFiled: August 6, 1998Date of Patent: November 30, 1999Assignee: Sharp Kabushiki KaishaInventor: Toshihiro Nakamori
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Patent number: 5991155Abstract: In a heat sink, a portable electronic apparatus using this heat sink, and a method for forming this heat sink, an abutting member is arranged on an inside surface of a casing and the casing and the abutting member are covered with a heat spreader sheet. The heat spreader sheet is made to abut against an exothermic device by means of an abutting member. The heat generated in the exothermic device is transmitted to the inside wall surface of the casing via the heat spreader sheet, with a portion being transmitted via the abutting member. When an anisotropic thermal conductivity material is used for the abutting member, it is possible to realize characteristics such as a low peak casing temperature under the exothermic device.Type: GrantFiled: December 10, 1997Date of Patent: November 23, 1999Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Takashi Kobayashi, Takashi Nonaka
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Patent number: 5973927Abstract: A mounting structure for an integrated circuit device comprises a first substrate, a second substrate and an insulator. The first substrate contains conductive wiring electrically connected to the integrated circuit device. The first substrate is mounted on the second substrate which have a ground pattern. The insulator is provided between the conductive wiring and the ground pattern.Type: GrantFiled: June 30, 1997Date of Patent: October 26, 1999Assignee: NEC CorporationInventor: Shinji Tanaka
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Patent number: 5956234Abstract: A method and structure for a surface mountable rigid-flex printed circuit board is disclosed. A rigid-flex circuit board is mounted onto a printed circuit board using standard surface mount technology such as ball grid array, pin grid array or solder screen print.The use of rigid-flex board allows tested, burned in components to be used while still allowing a small multiple chip module footprint.Type: GrantFiled: January 20, 1998Date of Patent: September 21, 1999Assignee: Integrated Device Technology, Inc.Inventor: Gerhard M. Mueller
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Patent number: 5923232Abstract: An improved electrical circuit particularly adapted to operate in an extremely thin atmosphere such as above fifty thousand feet. The circuitry of the invention is preferably formed on a circuit board and has an exposed conductive element such as a harmonic filter. This exposed conductive element is encased by a thin dielectric which is preferably formed using a solder mask having dielectric properties which prevent the conductive element from creating a corona during electrical operation in the contemplated thin atmosphere. In the preferred embodiment, the solder mask has a thickness of less than 0.002 inches and exhibits a dielectric strength of at least 1000 V/0.001 inch. The solder mask, for the preferred embodiment, is positioned to cover the conductive element and extends onto the circuit board only minimally.Type: GrantFiled: July 11, 1997Date of Patent: July 13, 1999Assignee: Honeywell Inc.Inventors: Thomas M. Europa, Mark D. Smith
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Patent number: 5920461Abstract: The present invention relates to a method and apparatus for manufacturing a surface mount power supply device having effective thermal management. The surface mount power supply device comprises a printed circuit board mounted to a thermal plastic lead frame attach by means of vertically-extending aluminum pins embedded in the lead frame attach. A cylindrical member is centered within the lead frame attach by means of inwardly protruding arms transversely connected to the lead frame attach to allow for a pick-and-place operation.Type: GrantFiled: May 12, 1997Date of Patent: July 6, 1999Assignee: Lambda Electronics, Inc.Inventor: Peter T. Brune
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Patent number: 5917709Abstract: A multiple circuit board assembly comprising: a first circuit board having a first predetermined set of conductive traces on a surface; a second circuit board having a second predetermined set of conductive traces on a surface; an interconnect mechanism having a third set of traces that mate the first and second set of traces when sandwiched between the first circuit board and the second circuit board in a predetermined manner; and fastened to the first and second circuit boards together with the interconnect mechanism sandwiched between such that there is electrical contact between the first and second predetermined set of conductive traces. The interconnect mechanism can be either single sided flex connector cable, double sided flex connector cable, or Cinch connectors. The fastening mechanism can be snaps fittings or screw setups without or without resilient washers.Type: GrantFiled: June 16, 1997Date of Patent: June 29, 1999Assignee: Eastman Kodak CompanyInventors: Dean A. Johnson, William R. Laubengayer, Stephen G. Richardson
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Patent number: 5903440Abstract: A method of forming a circuit board with electronic assemblies lying in different planes, includes providing a single circuit board with entire electronic assemblies pressed thereon. A channel is then formed in the circuit board of a predetermined depth to divide the circuit board into two separate, but integral portions. The circuit board is then bent at a point between the first and second portions of the circuit board such that the second portion of the circuit board can be bent between 0 and 180 degrees with respect to the first portion of the circuit board.Type: GrantFiled: January 30, 1998Date of Patent: May 11, 1999Assignee: Delco Electronics CorporaitonInventors: Michael Wayne Blazier, Frank Martin Stephan
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Patent number: 5901050Abstract: In a wired base plate for an electronic part, an infinite number of metallic posts made of copper are provided to a lid joining section of a plural wire layer portion, which section includes a lid joining surface area to which a lid is joined. The metallic posts supports a pressure applied thereto from a lid at the time of mounting of the wired base plate on a circuit board and prevent the plural wire layer portion having a plurality of conductor wire layers and a plurality of resinous insulation layers, from being deformed by compression. A package for an electronic part having such a wired base plate is also provided.Type: GrantFiled: August 21, 1997Date of Patent: May 4, 1999Assignee: NGK Spark Plug Co., Ltd.Inventor: Ryuji Imai
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Patent number: 5897724Abstract: A multilayer substrate is constituted by laminating a plurality of sheet substrates, the respective sheet substrates are constituted by forming conductive layers of a refractory metal such as W on ceramic green sheets composed mainly of an alumina ceramic, and the ceramic green sheets are laminated and sintered to constitute the multilayer substrate. Porous conductive material layers are formed on the surface of the multilayer substrate so as to be selectively connected to the conductive layers, and copper-plated layers are formed on the porous conductive material layers. Thick film conductor layers are formed on the copper-plated layers to constitute terminal conductors, and, a thick film resistor layer for example is connected to the terminal conductors.Type: GrantFiled: February 27, 1997Date of Patent: April 27, 1999Assignee: Nippondenso Co., Ltd.Inventor: Takashi Nagasaka
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Patent number: 5888627Abstract: It is an object of the present invention to provide a highly reliable printed circuit board subject to little bowing or twisting of the substrate, wherein the substrate and metal wiring are securely bonded together, and stable electrical and mechanical connection is achieved between the metal wiring and electroconductive resin paste filled into the through holes, and to provide a method of manufacture for same. The present invention relates to a printed circuit board having a multilayer wiring structure comprising a plurality of sheet substrates consisting of resin component layers containing an inorganic filler formed onto both sides of an organic nonwoven fabric material, and two or more circuit patterns, wherein through holes are formed in the sheet substrates in the thickness direction thereof and an electroconductive resin component is filled into the through holes, forming electrical connection between each of the electrode layers, and to a method of manufacture for same.Type: GrantFiled: May 29, 1997Date of Patent: March 30, 1999Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Seiichi Nakatani
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Patent number: 5886877Abstract: A circuit board, which is formed with bump patterns subject to a narrow variation in height on the surface of the circuit board, and which permits high-density packaging of a semiconductor component thereon. In this circuit board, conductor circuits formed by electroplating are embedded in an insulating base that is formed of a resist layer and an insulating substrate, and bumps are exposed in the surface of the insulating base. The bumps and the conductor circuits are connected electrically with one another by means of pillar-shaped conductors that are formed by electroplating. Each bump is a multilayer structure in two or more layers formed by successively depositing different electrically conductive materials by electroplating.Type: GrantFiled: October 9, 1996Date of Patent: March 23, 1999Assignees: Meiko Electronics Co., Ltd., Machine Active Contact Co., Ltd.Inventors: Noboru Shingai, Tatsuo Wada, Katsuro Aoshima
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Patent number: 5874152Abstract: The invention relates to a method of making a composite laminate comprising the steps of providing unidirectionally oriented parallel fibres (UD filaments) (3) with a resin matrix to form a composite UD layer and laminating a plurality of UD layers to form a UD crossply laminate (18). In the method of the invention, the UD filaments are impregnated with a melt of a resin which in the uncured form solidifies below a certain temperature (Tm). Thereupon the UD filaments-containing resin is cooled to a temperature below Tm to produce the composite UD layer. The produced composite UD layer is irreversibly cured before or after lamination. Notably latent curing resins are suitable. The impregnation is preferably conducted by coating a process belt (8) with solid resin (6), laying the UD filaments onto the resin, and heating the resin so as to form the resin melt. The heating of the resin is preferably conducted by means of IR irradiation (11).Type: GrantFiled: July 25, 1996Date of Patent: February 23, 1999Assignee: AMP-AKzo Linlam VoFInventor: Erik Middelman
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Patent number: 5856913Abstract: A semiconductor power module has semiconductor components mounted on a substrate. The semiconductor components are in electrical contact with the substrate. Internal circuit wiring is achieved by using one or more flexible circuit boards. The flexible circuit board(s) contact the semiconductor components and also provide external connection elements. Hermetical encapsulation is achieved by lamination, and height equalization of the different circuit regions is achieved by using geometrically preformed prepregs in conjunction with the flexible circuit board and the substrate.Type: GrantFiled: April 21, 1997Date of Patent: January 5, 1999Assignee: Semikron Elektronik GmbHInventor: Heinrich Heilbronner
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Patent number: 5847935Abstract: A package for an electronic component includes a metal base plate and a body of an insulating material, such as glass or ceramic, on and bonded to a surface of the base plate. The body is formed of a plurality of layers of the insulating material stacked and bonded to each other and has at least one opening extending therethrough to the base plate. Strips of a conductive material, such as a metal, are on the surface of various layers of the body. An electronic component is mounted in the opening in the body and has terminals which are electrically connected to the conductive strips on the body, preferably by wires. Vias of a conductive material may extend through some of the layers of the body to connect the conductive strips to terminals on the surface of the body. A cover plate of an insulating material may extend over the body and the opening therein to enclose the electronic component in the body.Type: GrantFiled: December 16, 1996Date of Patent: December 8, 1998Assignee: Sarnoff CorporationInventors: Barry Jay Thaler, Ashok Narayan Prabhu, Ananda Hosakere Kumar, Bernard Dov Geller
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Patent number: 5847936Abstract: A method and structure for routing electrically conductive interconnect paths through a printed circuit board. The printed circuit board includes a plurality of insulating layers and conductive layers, including at least one electrically conductive voltage supply layer for receiving a first supply voltage. A plurality of voltage supply pad patterns are located at the upper surface of the printed circuit board. Each voltage supply pad pattern includes two or more electrically conductive pads which are coupled by one or more electrically conductive traces. Electrically conductive via plugs extend through the printed circuit board to connect the voltage supply layer to the voltage supply pad patterns. Each via plug is connected to one corresponding voltage supply pad pattern, thereby allowing each via plug to provide the first supply voltage to a plurality of pads at the upper surface of the printed circuit board.Type: GrantFiled: June 20, 1997Date of Patent: December 8, 1998Assignee: Sun Microsystems, Inc.Inventors: Douglas W. Forehand, Ray Lamoreaux
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Patent number: 5840402Abstract: A metallized laminate material for the manufacture of high performance, high density printed wiring boards and the like includes an ordered distribution of via holes electrically interconnecting opposing conductive layers on a dielectric polymeric film substrate. Furthermore, opposing photoresist layers substantially cover the conductive layers and vias. The conductive material in the conductive layers and the vias is bonded adhesivelessly to the substrate to provide a high degree of delamination resistance. The production of metallized laminate material is preferably carried out in a roll-to-roll process suitable for high volume, low cost production. In use, an end user may manufacture customized printed wiring boards in small volume runs from the laminate material with a reduced amount of equipment, expertise and cost.Type: GrantFiled: June 24, 1994Date of Patent: November 24, 1998Assignee: Sheldahl, Inc.Inventors: Sidney J. Roberts, Eugene T. Selbitschka, Glenn W. Gengel, Brent N. Sweitzer
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Patent number: 5837367Abstract: The invention relates to a memory card and its method of manufacture. The memory card has a flexible composite substrate formed from a top film, a base film, and an adhesive layer deposited between and bonding together the base film and the top film. Preferably, the thickness of such composite substrate is between 8 and 12 mils. A layer of metal is adhered to the exposed surface of the top film. A circuit layer is provided to form at least one site on the memory card which is readable by an external reading device. A protective layer is provided to overlie and protect the circuit layer of the memory card.Type: GrantFiled: May 1, 1996Date of Patent: November 17, 1998Assignee: Interprint Formularios Ltda.Inventors: Fernando Ortiz, Jr., James T. Faris
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Patent number: 5828555Abstract: A multilayer printed-circuit board includes at least one inner-layer signal line, first and second ground layers between which the inner-layer signal line is sandwiched via a frame member made of an insulating material in a thickness direction of the multilayer printed-circuit board, and metallic wall members which are provided on inner walls of slits formed in the frame member and extending along the inner-layer signal line. The first and second ground layers and the metallic wall members shielding the inner-layer signal line.Type: GrantFiled: May 20, 1997Date of Patent: October 27, 1998Assignee: Fujitsu LimitedInventor: Takumi Itoh
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Patent number: 5822191Abstract: There is provided a highly reliable panel assembly structure capable of performing fine-pitch high-density assembling at a high yield and a low cost. A flexible wiring board has a film-like substrate with flexibility, and an IC chip is mounted in an area. In the area is provided a through hole that has plane dimensions smaller than plane dimensions of the chip and penetrates the substrate. Portions that belong respectively to an output side wiring line and an input side wiring line provided on a substrate surface and are connected respectively to an output side electrode and an input side electrode of the chip via second connection materials and are supported by the substrate surface. An output terminal of the flexible wiring board is connected to an electrode terminal formed at a peripheral portion of a panel via a first connection material, while an input terminal of the flexible wiring board is connected to an electrode terminal of a circuit board via a third connection material.Type: GrantFiled: May 27, 1997Date of Patent: October 13, 1998Assignee: Sharp Kabushiki KaishaInventors: Yasunobu Tagusa, Shigeo Nakabu
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Patent number: 5818697Abstract: An electronic package is provided that includes a flexible polyimide film carrier having electronic circuitry on both of its major surfaces and a plurality of solder interconnection pads on a first major surface; solder mask layers located on both major surfaces, provided that areas between subsequently to be applied individual circuit chips on the first major surface exist that are free from the solder mask; and a plurality of modules attached to the film carrier by the solder balls or bumps. Also provided is a method for fabricating the electronic package that includes reflow of the solder balls or bumps to achieve attachment of the modules.Type: GrantFiled: March 21, 1997Date of Patent: October 6, 1998Assignee: International Business Machines CorporationInventors: Gregg Joseph Armezzani, Robert Nicholas Ives, Mark Vincent Pierson, Terry Alan Tull
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Patent number: 5808872Abstract: A semiconductor package includes a semiconductor chip having a plurality of electrodes on a main surface thereof, and a package substrate having first and second parallel surfaces, wherein the package substrate is fixed to the semiconductor chip in such a positional relationship that the main surface of the semiconductor chip faces the first surface, and has substantially the same size as a size of the semiconductor chip as viewed on a projection plane vertical to the first surface, and wherein the package substrate has a passage extending between the first and the second surfaces for electrically connecting the electrodes of the semiconductor chip to predetermined portions of the circuit board. A method of mounting the above-mentioned semiconductor package to the circuit board comprises electrically connecting the electrodes of the semiconductor chip to predetermined portions of the circuit board by bonding wires or bumps, through the passage provided to the semiconductor package.Type: GrantFiled: November 13, 1995Date of Patent: September 15, 1998Assignee: Nippon Steel CorporationInventor: Atsushi Ozawa
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Patent number: 5764497Abstract: The circuit board connecting method and a connection structure. A first flexible board is adhered to a first surface of the circuit board at a first temperature, and then a second flexible board is adhered to a second flexible board at a second temperature lower than the first temperature.Type: GrantFiled: November 12, 1996Date of Patent: June 9, 1998Assignee: Minolta Co, Ltd.Inventor: Yoshiyuki Mizumo
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Patent number: 5761054Abstract: An integrated circuit package which has a flexible circuit that covers an integrated circuit. The flexible circuit contains a conductive line which prevents a probe from accessing the integrated circuit. The conductive line of the flexible circuit can be attached to the power lines, synchronization line, memory erase line, or any other line that will disable, erase or otherwise prevent access to the integrated circuit if the flexible circuit conductive line is broken. The integrated circuit can be mounted to a printed circuit board. The printed circuit board, integrated circuit and flexible circuit can all be enclosed within the package.Type: GrantFiled: August 25, 1997Date of Patent: June 2, 1998Assignee: Intel CorporationInventor: Harry A. Kuhn
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Patent number: 5744863Abstract: An aluminum or copper heat sink is attached to a ceramic cap or exposed semiconductor chip using flexible-epoxy to provide improved thermal performance. The aluminum may be coated by anodizing or chromate conversion or the copper may be coated with nickel. Such structures are especilly useful for CQFP, CBGA, CCGA, CPGA, TBGA, PBGA, DCAM, MCM-L, single layer ceramic, and other chip carrier packages as well as for flip chip attachment to flexible or rigid organic circuit boards. These adhesive materials withstand thermal cycle tests of 0.degree. to 100.degree. C. for 1,500 cycles, -25.degree. to 125.degree. C. for 400 cycles, and -40.degree. to 140.degree. C. for 300 cycles; and withstand continuous exposure at 130.degree. C. for 1000 hours without loss of strength. Flexible-epoxies have a modulus of elasticity below 100,000 psi and a glass transition temperature below 25.degree. C., are much stronger than typical silicone adhesives, and do not contaminate the module or circuit board with silicone.Type: GrantFiled: June 7, 1995Date of Patent: April 28, 1998Assignee: International Business Machines CorporationInventors: Thomas Moran Culnane, Michael Anthony Gaynes, Ping Kwong Seto, Hussain Shaukatullah
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Patent number: 5745334Abstract: A multi-layer printed circuit board comprises a first metallic layer, a first Ta or Hf layer on one face of the first metallic layer, a first layer of Ta.sub.2 O.sub.5 or HfO on a face of the Ta or Hf layer opposite the first metallic layer, a second metallic layer on the Ta.sub.2 O.sub.5 or HfO layer opposite the Ta or Hf layer, a first dielectric layer on the first metallic layer opposite the Ta of Hf layer, and a second dielectric layer on the second metallic layer opposite the Ta.sub.2 O.sub.5 or HfO layer. A multi-layer printed circuit board is formed by adding the following layers to form the second capacitor. A third metallic layer on said second dielectric layer, a second Ta or Hf layer on a face of the third metallic layer, a second Ta.sub.2 O.sub.5 or HfO layer on a face of the second Ta or Hf layer opposite the third metallic layer, a fourth metallic layer on the second Ta.sub.2 O.sub.Type: GrantFiled: March 25, 1996Date of Patent: April 28, 1998Assignee: International Business Machines CorporationInventors: Joseph Gerard Hoffarth, John Matthew Lauffer, Issa Said Mahmoud, deceased
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Patent number: 5738928Abstract: A TAB (tape automated bonding) tape of high precision is formed without the deformations of its conductor pattern and the like and which is hermetically sealed with resin. The method for producing a TAB tape includes punching required holes, such as a device hole 14 and the like, in a metal plate 10 coated with an insulating adhesive layer 12 over the area where a conductor pattern is to be formed; and forming a required conductor pattern 24 by bonding a conductor metal foil onto the adhesive layer and by etching the conductor metal foil. Thus, the material cost of this TAB tape can be reduced and the production of this tape is facilitated.Type: GrantFiled: November 14, 1995Date of Patent: April 14, 1998Assignee: Shinko Electric Industries Co., Ltd.Inventors: Kotaro Kodani, Kazuo Koyanagi, Kiyokazu Sato
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Patent number: 5738931Abstract: A electronic device is disclosed having an underlying conductor formed in a predetermined pattern on a surface of an underlying insulator and made of at least one member selected from the group consisting of Ti, Ta, Mo, Cr, Nb and W and their alloy, a main conductor made of Cu formed in a predetermined pattern on the underlying conductor, a first coating conductor made of at least one member selected from the group consisting of Ti, Ta, Mo, Nb and Ni and their alloy, and a second coating conductor made of at least one member selected from the group consisting of Au and Al and their alloy that are formed in this order so as to coat a surface of the main conductor made of Cu facing the surrounding insulator.Type: GrantFiled: September 13, 1995Date of Patent: April 14, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Toshiro Sato, Tetsuhiko Mizoguchi
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Patent number: 5688584Abstract: A multilayer circuit board having three or more conductive layers, with at least two conductive layers electrically and mechanically connected by an interconnecting adhesive layer, is disclosed. The interconnecting adhesive layer comprises a conductive adhesive material having a plurality of deformable, heat fusible metallic particles dispersed substantially throughout a non-conductive adhesive. The fabricated multilayer circuit boards have interconnections which are reliable, heat resistant, and capable of withstanding thermal cycling and typical circuit board finishing and assembly processes.Type: GrantFiled: September 27, 1995Date of Patent: November 18, 1997Assignee: Sheldahl, Inc.Inventors: Keith L. Casson, Carol Myers, Kenneth B. Gilleo, Deanna Suilmann, Edward Mahagnoul, Marion Tibesar
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Patent number: 5650665Abstract: A hybrid IC device has an insulation substrate 1. Circuit patterns 2 made of a thick copper film are formed on the substrate 1. The circuit patterns 2 include terminal patterns 8. Through-holes 7 electrically connect the terminal patterns 8 to terminal patterns 81 formed on the bottom surface of the substrate 1. Active elements such as transistors and ICs and passive elements such as resistors and capacitors are mounted on the top surface of the substrate 1 and are electrically connected to the circuit patterns 2. A conductive pattern 6 made of a thick copper film or a thick silver-platinum film is formed on the bottom surface of the substrate 1. The conductive pattern 6 is used for grounding and heat radiation. The conductive pattern 6 is electrically connected to the active and passive elements via through-holes. The through-holes are usually formed Just under the active and passive elements.Type: GrantFiled: October 23, 1996Date of Patent: July 22, 1997Assignee: Kabushiki Kaisha ToshibaInventors: Tomohiko Yamamoto, Shoichi Tanimata
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Patent number: 5627344Abstract: A multilayer ceramic circuit substrate having therein internal conductor patterns comprising W and/or Mo as a main component and surface conductor patterns comprising Cu as a main component formed onto a surface layer of the multilayer ceramic circuit substrate, wherein an intermediate metal layer comprising 40 to 90 wt. % of W and/or Mo and 10 to 60 wt. % of at least one element selected from the group consisting of Ir, Pt, Ti, and Cr is formed in through-holes of the surface layer and on parts of the surface layer in the vicinity of the through holes on the surface layer, whereby the internal conductor patterns and the surface conductor patterns are electrically connected through the intermediate metal layer. The alumina multilayer ceramic circuit substrate provides an excellent bonding strength and electrical conductivity between the internal conductors and the surface conductors and enables high precision wiring and miniaturization of an electronic circuit part.Type: GrantFiled: December 22, 1994Date of Patent: May 6, 1997Assignees: Sumitomo Metal Ceramics Inc., Nippondenso Co., Ltd.Inventors: Nozomi Tanifuji, Akihiko Naito, Koji Sawada, Tohru Nomura, Yoshiyuki Miyase, Takashi Nagasaka
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Patent number: 5615088Abstract: A multi-layer, flexible printed circuit device having a relatively rigid electronic component mounting portion and a relatively pliable connection wiring portion. The electronic component mounting portion comprises multiple layers of bases including at least one rigid base, and circuit pattern layers. The pliable connection wiring portion is formed by extending pliable bases and circuit pattern layers at one end. The rigidity of the electronic component mounting portion may be maintained by means of the rigid base or bases comprising a thick panel made of the same material as the pliable bases. Alternatively, the copper films of the circuit pattern layers may be made relatively thick or a base material with high rigidity may be used.Type: GrantFiled: August 21, 1995Date of Patent: March 25, 1997Assignee: Minolta Co., Ltd.Inventor: Yoshiyuki Mizumo
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Patent number: 5604673Abstract: Electronic power conversion circuitry, for frequencies not exceeding 30 MHz, is manufactured using the benefits of low temperature co-fired ceramic substrates to provide interconnection between the discrete components of the power conversion circuit, and integrate various non-semiconductor devices into the body of the low temperature co-fired ceramic structure, such as resistors, capacitors, inductors and transformers. Use of a low temperature co-fired ceramic structure as a substrate on and within which power conversion circuitry is formed allows selection of various conductive and resistive inks to precisely form interconnection circuitry and selected non-semiconductor components which improves the stability and reduces the cost of power conversion circuits.Type: GrantFiled: June 7, 1995Date of Patent: February 18, 1997Assignee: Hughes ElectronicsInventors: Robert D. Washburn, Robert F. McClanahan, Andrew A. Shapiro
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Patent number: 5585162Abstract: A flexible circuit construction allows solder balls to be mass reflow attached to the ground plane of a double-sided flexible circuit by providing a first via which is separate from the remainder of the ground plane, but which is electrically connected to the ground plane through a second via at a distance from the first via by a circuit trace on the side of the flexible circuit opposite the ground plane.Type: GrantFiled: June 16, 1995Date of Patent: December 17, 1996Assignee: Minnesota Mining and Manufacturing CompanyInventor: Randolph D. Schueller
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Patent number: 5586010Abstract: The ball grid array package (10) uses a flexible base (30) having a substantially flat center plate (34) disposed at a first level coupled to a substantially flat base plate (32) disposed at a second level. The center plate (34) is coupled to the base plate (32) by a plurality of flexible narrow straps (36-38) arranged substantially surrounding the center plate (34). The flexible base (30) accommodates the thermal expansion in the pedestal (18) caused by the powered up integrated circuit (16) so that the rest of the package does not expand and induce stress in the solder joint between the ball grid array (12) and the printed circuit board (14).Type: GrantFiled: March 13, 1995Date of Patent: December 17, 1996Assignee: Texas Instruments IncorporatedInventors: Masood Murtuza, Abbas I. Attarwala
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Patent number: 5528000Abstract: A process for electroplating a nonconducting substrate comprising formation of a film of a conductive polymer on the surface of a nonconducting substrate and electrolytic deposition of metal thereover. The conductive film is formed by deposition of the conductive polymer onto said surface from an aqueous suspension of said polymer.Type: GrantFiled: February 28, 1995Date of Patent: June 18, 1996Assignee: Shipley Company, L.L.C.Inventors: George R. Allardyce, Kevin Bass, John E. Graves, James G. Shelnut
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Patent number: 5519578Abstract: A printed wiring board structure includes a printed wiring board and an electromagnetic shielding member. The printed wiring board has a part-mounted surface formed on one surface thereof, a ground surface formed on a reverse surface side to the part-mounted surface, and an exploded shape including at least a portion constituted by a flexible printed wiring board, and bottom and upper surface portions which are divided from each other by the flexible printed wiring board. The printed wiring board is folded at a portion constituted by the flexible printed wiring board to cause the part-mounted surface to face inside and to make the bottom surface portion parallel to the upper surface portion, thereby constituting a stereoscopic structure having two wiring layers. The electromagnetic shielding member is parallelly arranged between opposing part-mounted surfaces of the bottom and upper surface portions of the printed wiring board in which the stereoscopic structure is constituted.Type: GrantFiled: June 6, 1994Date of Patent: May 21, 1996Assignee: NEC CorporationInventor: Masahiro Fujii
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Patent number: 5493074Abstract: A flexible circuit board device for connecting to an electronic device comprised of a flexible circuit board made from flexible resistive film, an adhesive layer formed on the flexible resistive film, electrical conductive circuits formed on the adhesive layer and cured films filling the gaps between the conductive circuits. The electrical conductive circuits are formed of conductor metal foil and a plating film covering the surface of the conductor.Type: GrantFiled: June 23, 1994Date of Patent: February 20, 1996Assignee: Nippon Graphite Industries Ltd.Inventors: Katsuhiro Murata, Mitsumasa Shibata, Toru Hatakeyama, Tadaaki Isono
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Patent number: 5474834Abstract: A circuit sub-assembly as a mounting for an electronic component such as Josephson device, i.e., a superconducting element, comprises a ceramic insulating substrate, an oxygen-shielding barrier layer formed on the insulating substrate, and a circuit film of niobium, as a superconducting material formed on the barrier layer according to a desired pattern. The barrier layer prevents oxidation of the circuit layer by shielding it from oxygen present in the insulating substrate. Due to the barrier layer, the circuit film is scarcely subject to superconductivity-impairing oxidation. The circuit film is thus capable of high-speed electronic signal conduction.Type: GrantFiled: June 9, 1994Date of Patent: December 12, 1995Assignee: Kyocera CorporationInventors: Shigeo Tanahashi, Takanori Kubo, Kazuhiro Kawabata
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Patent number: 5468918Abstract: A conductor member for an electric circuit includes a conductive plastic mold in which carbon fibers or graphite fibers are dispersedly contained, and a metallic layer at least partially plated on the surface of said conductive plastic mold. The conductor member is provided on the surface of an insulating substrate to provide an electric circuit body. Thus, the conductor member for an electric circuit and the electric circuit body can be easily formed in a three-dimensional circuit because of its simple fabrication and excellent processing. Further, the film of metal plating can be made at a high speed and is hard to break because of the intimate contact of the plated metal.Type: GrantFiled: December 16, 1993Date of Patent: November 21, 1995Assignee: Yazaki CorporationInventors: Toshiaki Kanno, Makoto Katsumata, Hidenori Yamanashi, Hitoshi Ushijima
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Patent number: 5463190Abstract: A conductive adhesive (120) for electrically and mechanically bonding circuit terminals (105) includes a polymer (121) having a predetermined curing temperature range, a first conductive particulate material (125) suspendable in the polymer (121) for providing substantially uniform conductivity throughout the conductive adhesive (120), and a second conductive particulate material (130) suspendable in the polymer (121) for metallurgically bonding together particles of the first particulate material (125). The first conductive particulate material (125) provides substantially uniform conductivity throughout the conductive adhesive (120) and includes metallic particles having a melting point above the curing temperature of the polymer. The second conductive particulate material (130) welds together particles of the first particulate material (125) and includes metallic particles having a melting point within the curing temperature range of the polymer (121).Type: GrantFiled: April 4, 1994Date of Patent: October 31, 1995Assignee: Motorola, Inc.Inventors: Robert T. Carson, Arnold W. Hogrefe, Frank J. Juskey, Jr.