Abstract: A printed circuit board includes an electronic component including a first land, a printed wiring board including a resist portion and a second land, and a connecting portion interconnecting the first land and the second land. An opening larger than the first land in plan view from the electronic component side is defined in the resist portion. In plan view from the electronic component side, the first land is disposed inside the opening, the second land including a body portion disposed inside the opening and a protruding portion protruding from the body portion, the body portion being disposed further on an inside than an outer edge of the first land, and at least part of the protruding portion protruding further to an outside than the first land.

Abstract: Embodiments may relate to a semiconductor package that includes a package substrate coupled with a die. The package may further include a waveguide coupled with the first package substrate. The waveguide may include two or more layers of a dielectric material with a waveguide channel positioned between two layers of the two or more layers of the dielectric material. The waveguide channel may convey an electromagnetic signal with a frequency greater than 30 gigahertz (GHz). Other embodiments may be described or claimed.

Abstract: A stacked, multi-layer transmission line is provided. The stacked transmission line includes at least a pair of conductive traces, each conductive trace having a plurality of conductive stubs electrically coupled thereto. The stubs are disposed in one or more separate spatial layers from the conductive traces.

Abstract: An electrical component having partial bodies, a base on which the partial bodies are arranged, and at least one connection contact for electrically connecting the partial bodies to a carrier. A method for producing an electrical component having one or more partial bodies is also disclosed.

Abstract: A resin substrate includes a resin base material including a first main surface, electrode pads provided on the first main surface, circuit conductor patterns, a resist film, and a coverlay film. The resist film includes, on the outer circumference, a plurality of protruding portions each of which has a tapered shape with a vertex. A portion of the circuit conductor patterns are covered with the resist film, and the coverlay film covers a portion of the resist film including the protruding portions and exposed portions of the circuit conductor patterns. The protruding portions are located at positions sandwiching the exposed portions of the circuit conductor patterns.

Abstract: By changing the characteristic impedance of the transmission line depending on the location, the transmission line functions as a band-pass filter.

Abstract: An object of the present invention is to decrease the resistance of a power supply line, to suppress a voltage drop in the power supply line, and to prevent defective display. A connection terminal portion includes a plurality of connection terminals. The plurality of connection terminals is provided with a plurality of connection pads which is part of the connection terminal. The plurality of connection pads includes a first connection pad and a second connection pad having a line width different from that of the first connection pad. Pitches between the plurality of connection pads are equal to each other.

Abstract: A computer-implemented method for extracting a capacitance for a target wire of an integrated circuit includes receiving a design of the integrated circuit having a plurality of wiring layers and selecting a target wire to perform the capacitance extraction. The method further includes determining a first adjacent wiring layer and a second adjacent wiring layer and removing a first subset and a second subset of a plurality of non-adjacent wiring layers from the plurality of wiring layers. The method includes approximating a first plate to be used in the extraction based on the first subset of the plurality of non-adjacent wiring layers and approximating a second plate to be used in the extraction based on the second subset of the plurality of non-adjacent wiring layers and performing the extraction of the target wire based on the first and second adjacent wiring layers and the first and second plates.

Abstract: Disclosed is an organic light emitting display device that may include first and second pads on a pad area of a substrate, wherein the first pad includes a first bonding region and a first link region, and the second pad includes a second bonding region, a contact region, and a second link region. A first bonding electrode in the first bonding region is electrically connected to one or more signal lines in the active area of the device through contact holes in the first bonding region. A second bonding electrode is electrically connected to one or more signal lines of the device through contact holes in the contact region. The contact region is closer to the active area than the first bonding region.

Abstract: A printed wiring board includes an insulating layer, a first conductor layer embedded into first surface of the insulating layer and including multiple wirings such that the wirings include connecting portions positioned to connect an electronic component, respectively, a second conductor layer projecting from second surface of the insulating layer on the opposite side, a solder resist layer formed on the first surface of the insulating layer such that the solder resist layer is covering the first conductor layer and has an opening structure exposing the connecting portions of the wirings, and multiple metal posts formed on the connecting portions respectively such that each of the metal posts has a width which is larger than a width of a respective one of the wirings having the connecting portions. The wirings are formed such that the connecting portions are positioned side by side on every other adjacent one of the wirings.

Abstract: A frame 100 containing aperture(s) 102, 103, 104 is positioned on and joined to a permanent substrate 206a or temporary substrate 206b. Electrical component(s) 202, 203, 204 are placed into respective aperture(s) 102, 103, 104 with the leads 504, 1002 of the component(s) 202, 203, 204 positioned on and attached to the permanent substrate 206a or the temporary substrate 206b. Then an encapsulant 402, electrically insulating, but preferably thermally conductive, envelops the component(s) 102, 103, 104. At this point, temporary substrate 206b may be removed exposing component leads 1002. Or, if component(s) 102, 103, 104 are mounted on permanent substrate 206a, vias 502 extend from the surface of substrate 206a to leads 504. With leads 504, 1002 exposed, the completed subassembly 500, 1000 may be incorporated into various forms of reverse-interconnection process (RIP) assemblies as detailed in related applications.

Abstract: A system for managing electric devices, including a first panel having at least one hole and having a first conductive surface, a second panel integral and substantially parallel to the first panel and having a second conductive surface. The first panel is overlapped to the second panel. The system is configured in such a way that the second conductive surface has at least one portion not covered by the first panel and accessible through the, or each, hole. The first conductive surface and the second conductive surface are connected to an electric circuit in such a way that the first conductive surface has a first predetermined polarity, and the second conductive surface has a second predetermined polarity, opposite to the first predetermined polarity.

Abstract: According to various embodiments, a method for forming a direct data connector for a sealed device may be provided. The method may include: providing a substrate with a hole; and filling the hole with a filling material using a plating process.

Abstract: A semiconductor device design method includes generating a layout of a semiconductor device based on schematic data. The layout includes location data for at least one electrical component. The method includes receiving first voltage data associated with at least one electrical component. The method includes receiving second voltage data based on simulation results for the semiconductor device. The method includes incorporating, based on the location data of the at least one electrical component, the first voltage data or the second voltage data in the layout to generate a modified layout. The first voltage data or the second voltage data being incorporated in at least one marker layer of the modified layout. The method includes performing a voltage-dependent design rule check (VDRC) on the modified layout. The VDRC analyzes spacing rules associated with the at least one electrical component based on the first voltage data or the second voltage data.

Abstract: The present invention relates to photovoltaic modules and methods of manufacturing photovoltaic modules.

Abstract: A printed circuit board, and method of manufacture, for high speed signals. The printed circuit board has small diameter vias of uniform inside diameter when plated. The uniformity of the inside diameter, at least over the region in which a press fit segment is inserted, is sufficient to make a reliable electrical and mechanical connection to the press fit segment with reduced risk of damage to the press fit segment.

Abstract: A motherboard with an electrostatic discharge protection (ESD) function including a first electrode, a second electrode, an isolation region and an energy storage unit is disclosed. The first electrode receives a grounding level. The second electrode includes at least one solder pad to fix an input/output port thereon. The isolation region is disposed between the first and the second electrodes. The energy storage unit is coupled between the first and the second electrodes and disposed across the isolation region.

Abstract: An apparatus comprising a first substrate having a first surface, a second substrate having a second surface facing the first surface and an array of metallic raised features being in contact with the first surface to the second surface, a portion of the raised features having a mechanical bend or buckle plastic deformation produced therein via a compressive force. One or more of the metallic raised features has one or more surface singularities therein prior to the mechanical bend or the buckle plastic deformation produced by the compressive force.

Abstract: A substrate including a fluid reservoir and a connected fluid channel, the fluid reservoir positioned away from a component region of the substrate, the fluid channel configured to extend from the fluid reservoir to guide an electrically conductive fluid from the fluid reservoir at a reservoir end of the fluid channel through the fluid channel to a component end of the fluid channel, the component end extending to the component region of the substrate to enable the formation of an electrical connection to a connector of an electronic component appropriately positioned in the component region, formation of the electrical connection allowing the electronic component to be interconnected to other electronic components using one or more of the fluid reservoir and fluid channel.

Abstract: A surface mount electrical interconnect adapted to provide an interface between solder balls on a BGA device and a PCB. The electrical interconnect includes a socket substrate with a first surface, a second surface, and a plurality of openings sized and configured to receive the solder balls on the BGA device. A plurality of electrically conductive contact tabs are bonded to the first surface of the socket substrate so that contact tips on the contact tabs extend into the openings. The contact tips electrically couple with the BGA device when the solder balls are positioned in the openings. Vias are located in the openings that electrically couple the contact tabs to contact pads located proximate the second surface of the socket substrate. Solder balls are bonded to the contact pad that are adapted to electrically and mechanically couple the electrical interconnect to the PCB.

Abstract: An electronic device of the present invention includes an insulating base substrate in which a plurality of through electrodes are formed, an electronic element which is electrically connected to the through electrodes and is mounted on one surface of the base substrate, a lid which accommodates the electronic element and is bonded to the one surface of the base substrate, and an external electrode which covers a region from an end face of the through electrode, which is exposed by the other surface of the base substrate, to the other surface in the vicinity of the end face. The external electrode includes a conductive film which covers a region ranging from the end face to the other surface in the vicinity of the end face, and a paste film which covers a surface of the conductive film and is formed of a conductive paste. The paste film is formed by a printing method and is formed of tin or a tin alloy.

Abstract: A surface-mountable electronic device free of leads has a plurality of solderable connection surfaces at its lower side, with at least one of the connection surfaces having a rectangular portion. The outline of this rectangular portion corresponds to a connection surface of the JEDEC Standard MO-236 or of any other standard according to which the respective connection surface should not extend directly up to a side edge of the lower device side. The at least one connection surface furthermore has an extension section which extends, starting from the rectangular portion, in the direction of a side edge of the lower side of the device.

Abstract: Inductive coupling arising between adjacent vias in interconnect technologies (commonly associated with printed circuit boards or package) can be combatted through the addition of metal plates to vias. The plates generate capacitive coupling that can compensate for the inductive crosstalk normally generated between vias in printed circuit boards or packages. When the added plates of two neighboring vias overlap with each other, a capacitive coupling is generated. By balancing the inductive coupling with capacitive coupling, an effective reduction of far end crosstalk may be obtained.

Abstract: Disclosed herein is a printed circuit board, including a base substrate; and a circuit pattern formed on the base substrate and including a first metal layer having an inclined surface on both upper sides thereof and a second metal layer formed on the inclined part.

Abstract: An embodiment of a solder wettable flange includes a flange body formed from a conductive material. The flange body has a bottom surface, a top surface, sidewalls extending between the top surface and the bottom surface, and one or more depressions extending into the flange body from the bottom surface. Each depression is defined by a depression surface that may or may not be solder wettable. During solder attachment of the flange to a substrate, the depressions may function as reservoirs for excess solder. Embodiments also include devices and systems that include such solder wettable flanges, and methods for forming the solder wettable flanges, devices, and systems.

Abstract: The present invention concerns a printed circuit board, PCB. The PCB comprises a number of signal layers comprising routing channels and at least one ground layer being adjacent to at least one signal layer. A number of via holes connects different signal layers of the PCB. In the signal layers the via holes are connected to pads and in the ground layers they are be surrounded by anti-pads. The pads are shaped such that at least a part of a via hole connected to the pad is on the outside of, or in close proximity to, the edge of the pad, irrespective of where on the pad the centre of the via hole is positioned.

Abstract: The invention relates to a method for fabricating a bond by providing a body including a metallic surface provided with an inorganic, dielectric protective layer. The protective layer covers at least one surface zone of the metallic surface in which the metallic surface is to be electrically conductive bonded to a contact conductor. To fabricate the bond, a portion of a provided contact conductor above the surface zone is pressed on to the protective layer and the body so that the protective layer is destroyed above the surface zone in achieving an electrically conductive bond between the metallic surface and the contact conductor.

Abstract: Embodiments of the present invention provide a multi layered printed circuit board, PCB, with via holes connecting different signal layers of the PCB. The via holes are connected to pads in the signal layers and are surrounded by anti-pads in the ground layers. In accordance with further embodiments of the invention the pads have a shape wherein a first path, stretching from the center of the pad and substantially in a direction in which adjacent routing channels extend, to a first point located on the edge of the pad, is longer than a second path, stretching from the center of the pad and substantially in a direction towards the adjacent routing channels to a second point located on the edge of the pad.

Abstract: A package assembly comprises an electronic device; a package body; at least a first plurality of leads having a first geometrical shape and a second plurality of leads having a second geometrical shape, protruding from the package body; each of the first plurality of leads being located in corners of the package body; or the first and the second plurality of leads arranged in at least a first row and a second row located in parallel to the first row; each of the rows comprising at least two leads; the first row being transformable into the second row by mirroring the first row along a symmetry plane of the package body; each of the first plurality of leads having the first geometrical shape different from the second geometrical shape.

Abstract: An electronic device may contain components such as flexible printed circuits and rigid printed circuits. Electrical contact pads on a flexible printed circuit may be coupled electrical contact pads on a rigid printed circuit using a coupling member. The coupling member may be configured to electrically couple contact pads on a top surface of the flexible circuit to contact pads on a top surface of the rigid circuit. The coupling member may be configured to bear against a top surface of the flexible circuit so that pads on a bottom surface of the flexible circuit rest against pads on a top surface of the rigid circuit. The coupling member may bear against the top surface of the flexible circuit. The coupling member may include protrusions that extend into openings in the rigid printed circuit. The protrusions may be engaged with engagement members in the openings.

Abstract: An electronic-component mounted body of the present invention includes an electronic component mounted on a circuit board. The electronic component includes multiple component-side electrode terminals, and the circuit board includes multiple circuit-board side electrode terminals for the component-side electrode terminals. The electronic-component mounted body further includes: multiple protruded electrodes formed respectively on the component-side electrode terminals of the electronic component to electrically connect the electronic component and the circuit board; and a dummy electrode formed on the electronic component and electrically connected to the component-side electrode terminal in a predetermined position out of the component-side electrode terminals. The protruded electrode on the component-side electrode terminal in the predetermined position is higher than the protruded electrode on the component-side electrode terminal in a different position from the predetermined position.

Abstract: Embodiments of the present disclosure describe apparatuses, methods, and systems of thermal via structures with surface features. In some embodiments the surface features may have dimensions greater than approximately one micron. The thermal via structures may be incorporated into a substrate of an integrated circuit device. Other embodiments may be described and/or claimed.

Abstract: A package structure includes a base body having a first encapsulant and a wiring layer embedded in and exposed from the first encapsulant. The wiring layer has a plurality of conductive traces and a plurality of first electrical contact pads. The first encapsulant has openings for exposing the first electrical contact pads, a chip electrically connected to the wiring layer, and a second encapsulant formed on the base body for covering the chip and the wiring layer, thereby providing an even surface for preventing the encapsulant from cracking when the chip is mounted.

Abstract: Microelectronic packages with leadframes, including leadframes configured for stacked die packages, and associated systems and methods are disclosed. A system in accordance with one embodiment includes a support member having first package bond sites electrically coupled to leadframe bond sites. A microelectronic die can be carried by the support member and electrically coupled to the first packaged bond sites. A leadframe can be attached to the leadframe bond sites so as to extend adjacent to the microelectronic die, with the die positioned between the leadframe and the support member. The leadframe can include second package bond sites facing away from the first package bond sites. An encapsulant can at least partially surround the leadframe and the microelectronic die, with the first and second package bond sites accessible from outside the encapsulant.

Abstract: Provided are a tape carrier package and a method of manufacturing the same, the method, including: forming through holes by performing a drill process using a laser to an insulating film of a flexible copper clad laminate (FCCL) film consisting of the insulating film and a copper layer; forming a circuit pattern layer by performing an etching process to the copper layer of the FCCL film; and selectively forming a plating layer on the circuit pattern layer. The method of manufacturing the tape carrier package according to the present invention is advantageous because a punching process, and processes for laminating and drying the copper layer which are necessary for the conventional method of manufacturing the tape carrier package can be omitted, a production cost of the tape carrier package is reduced, and the time required for the drying process is saved.

Abstract: A device includes a substrate, a first antenna connection, and a first retention mechanism. The substrate has a top surface and a bottom surface. The first antenna connection is mounted directly to the top surface of the substrate, and is configured to connect with a first antenna. The first retention mechanism is connected at a first location of the bottom surface of the substrate to provide support for the substrate at the first antenna connection when the first antenna connection is connected to the first antenna. The first location of the first retention mechanism is selected to be directly below the first antenna connection.

Abstract: An electrode bonding structure sealed with a sealing resin, in which a flexible substrate is bonded to a first substrate via an adhesive, wherein: a region along a bottom face edge of an flexible substrate end part is bonded, via the adhesive, to an inner side region of a region along a top face edge of an first substrate end part; a gap is formed between an inner side region of the region along the bottom face edge of the flexible substrate end part and the region along the top face edge of the first substrate end part; the sealing resin is formed so as to enter, while covering a top face of the flexible substrate end part, at least a portion of the gap; and a height of the gap gets smaller towards the adhesive from the top face edge of the first substrate end part.

Abstract: A circuit board includes a substrate, a first ground electrode group, and a first pair of signal electrodes. The first ground electrode group includes a plurality of first ground electrodes, where each of the plurality of the first ground electrodes is disposed at a corresponding one of vertexes of a first rectangular area in a surface of the substrate. the first pair of signal electrodes is disposed in the first rectangular area and is arranged in a first direction parallel to a side of the first rectangular area.

Abstract: Devices and methods for constructing low-profile, minimal-thickness electronic devices using existing production techniques are disclosed in this application. An electronic component and interposer form a sub-assembly. The sub-assembly is placed in an aperture in a circuit board with the interposer providing interconnections between the electronic component and the circuit board. Such placement conceals the thickness of the integrated circuit within the thickness of the circuit board, reducing overall thickness.

Abstract: Disclosed herein is a printed circuit board having an insulating layer crack preventing port. The printed circuit board includes: an insulating layer part having at least one pair of insulating layers stacked therein; circuit patterns formed on the insulating layers, respectively; and crack preventing ports formed at positions at which they are not affected by the respective circuit patterns of the insulating layer part and supporting the insulating layer part from external impact.

Abstract: Approaches for formation of a circuit via which electrically connects a first thin film metallization layer a second thin film metallization layer are described. Via formation involves the use of an anodization barrier and/or supplemental pad disposed in a via connection region prior to anodization of the first metallization layer. The material used to form the barrier is substantially impermeable to the anodization solution during anodization, and disrupts the formation of oxide between the electrically conducting layer and the barrier. The supplemental pad is non-anodizable, and is covered by the barrier to substantially prevent current flow through the pad during anodization. Following anodization, the barrier is removed. If the supplemental pad is sufficiently conductive, it can be left on the first metallization layer after removal of the barrier.

Abstract: A semiconductor device for mounting on a wiring board includes: a container for containing a semiconductor chip; and a plurality of leads, each of the plurality of leads includes a mount connection portion at one end for the semiconductor device to be connected to the wiring board, wherein the plurality of leads includes first leads and second leads, a signal transmission rate of the first leads is higher than that of the second leads, and the mount connection portion of each of the first leads is smaller than that of each of the second leads.

Abstract: A method for electrically interconnecting two substrates, each having a corresponding set of preformed electrical contacts, the substrates comprising an electronic circuit, and the resulting module, is provided. A liquid curable adhesive is provided over the set of contacts of a first substrate, and the set of electrical contacts of the second substrate is aligned with the set of electrical contacts of the first substrate. The sets of electrical contacts of the first and second substrate are compressed to displace the liquid curable adhesive from the inter-contact region, and provide electrical communication between the respective sets of electrical contacts. The liquid curable adhesive is then cured to form a solid matrix which maintains a relative compression between the respective sets of electrical contacts. One embodiment of the module comprises a high-speed superconducting circuit which operates at cryogenic temperatures.

Abstract: A printed circuit board and a method for the production thereof. The printed circuit board can include a shaped part made of an electrically conducting material and can be used to manage the currents and heat volumes that occur in the field of power electronics.

Abstract: A printed circuit board and a design method thereof are disclosed. The design method includes: wiring signal lines on an area basis at inner layers adjacent to outer surface layers; arranging the outer surface layers with no wiring or few wirings and interconnecting the outer surface layers through vias, so that the outer surface layers function as a primary ground; and setting parameters of a line width and a layer height to control a target impedance value. The printed circuit board includes outer surface layers and two inner layers therebetween. The inner layers adjacent to the outer surface layers are used for arranging signal lines on an area basis; and the outer surface layers are arranged with no wiring or few wirings and are interconnected as a primary ground through vias. The invention also discloses a mainboard of a terminal product using the printed circuit board.

Abstract: A wiring structure for improving a crown-like defect and a fabrication method thereof are provided. The method includes the following steps. A substrate, on which a seed layer and a patterned photoresist layer with an opening are formed, is provided. A copper layer, having a bottom covering the seed layer, is formed in the opening. A barrier layer covering at least one top portion of the copper layer is formed on the copper layer. An oxidation potential of the barrier layer is greater than that of the copper layer. The patterned photoresist layer is removed to perform an etching process, wherein the copper layer and a portion of the seed layer exposed are etched to form a wiring layer. An immersion process is performed to form an anti-oxidation layer comprehensively on exposed surfaces of the barrier layer and the wiring layer.

Abstract: An LTCC carrier composed of thermosetting polymer, woven glass fiber and ceramic has gold over nickel contact pads on top and bottom surfaces and conductive vias therethrough between aligned pairs of top and bottom pads. The vias prevent undesirable inductive paths from limiting high frequency operation of the circuitry. Solder deposits on the top pads attach the LTCC component, which is further secured to the carrier by epoxy, thus improving resistance to thermal stress and mechanical shock. A slot through the carrier body between top and bottom surfaces further reduces thermal stress and mechanical shock. Metallized castellations on opposite carrier sides provide additional surface area for reflow solder joints with the PCB, and a means for visually inspecting the solder joint quality. A gap in the metallization on the top layer of the carrier prevents solder spreading during multiple soldering cycles, which may result in poor solder joints.

Abstract: Methods for manufacturing a light source circuit board having one or more light emitting components that include providing at least one circuit component on a light source circuit board, wherein the at least one circuit component has an electrical circuit constant that specifies one or more performance parameters for the light source. The methods also include measuring the electrical circuit constant of the at least one circuit component. The methods also include identifying one or more performance parameters for the light source based on the measured electrical constant.

Abstract: Some invention embodiments relate to a method for forming a fuse which electrically connects two metal surfaces (2) that are arranged on a printed circuit board (4) next to each other and spaced apart from each other. It is provided according to the invention that the two metal surfaces (2) are each partially covered with a protective coating (5), wherein a partial region forming a contact region (2a) remains uncovered, liquid soft solder material (1) which bridges the gap between the two metal surfaces (2) is applied onto the two uncovered partial regions (2a), and the protective coating (5) in a surrounding area of the solder material (1) is removed after the soft solder material (1) has solidified, in order to form receiving regions (2b) which are wetted by the solder material (1) when the latter fuses, with the result that the solder material (1) flows off from a printed circuit board region (3) between the two metal surfaces (2) and the electrical contact formed by the solder material (1) is interrupted.

Abstract: A printed board includes a printed board body having a first side, a second side opposing the first side, and a through-hole; a printed conductor disposed on the first side of the printed board body; and a bus bar disposed on the second side of the printed board body, the bus bar including a terminal that extends through the through-hole. The terminal includes a plurality of branched terminal portions at a position corresponding to an interior of the through-hole, and at least one of the branched terminal portions is bent and attached to the printed conductor.