Connection Of Components To Board Patents (Class 361/760)
  • Patent number: 11444043
    Abstract: Disclosed are substrates having an electronic component, including a frame having a through hole, the electronic component disposed in the through hole, a first wiring portion formed on a surface of the frame and the electronic component, a first layer formed on the first wiring portion, and a second wiring portion formed on the first layer, and the second wiring portion including an antenna layer.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: September 13, 2022
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Hong In Kim, Thomas A Kim, Tae Sung Jeong
  • Patent number: 11437290
    Abstract: An electronic component built-in wiring board includes a substrate having a cavity, an electronic component accommodated in the cavity of the substrate and having pads on a surface of the component, a coating insulating layer formed on the substrate such that the insulating layer is covering the component and has via holes, via conductors formed in the via holes such that the via conductors are penetrating through the insulating layer, and a resin coating formed between the component and the insulating layer and having through holes such that the through holes are partially exposing the pads in the via holes and that the coating has adhesion to the component that is stronger than adhesion of the insulating layer to the component. The via conductors are formed in the via holes and the through holes such that the via conductors are connected to the pads on the surface of the component.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: September 6, 2022
    Assignee: IBIDEN CO., LTD.
    Inventors: Yusuke Tanaka, Tomohiro Futatsugi, Yuichi Nakamura, Yoshiki Matsui, Keinosuke Ino, Tomohiro Fuwa, Seiji Izawa
  • Patent number: 11425816
    Abstract: Systems, apparatuses, and methods related to a printed circuit board (PCB) with a plurality of layers are described. An edge connector may be formed on an end of the PCB substrate and may include contact pins on an outer layer of the plurality of layers. The edge connector may also include an intra-pair coupling block disposed on one or more interior layers such that at least a portion of the intra-pair coupling block is colinear with at least one contact pin on the outer layer. The electronic device may also include at least one integrated circuit on the PCB and electrically connected to the contact pins. The intra-pair coupling component may induce coupling of signals carried by the contact pins.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: August 23, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Daniel B. Stewart
  • Patent number: 11417975
    Abstract: A connector includes a flat-plate housing made of insulating resin and including a first positioning hole and a second positioning hole, a plurality of contacts held on the housing, and a first hold-down and a second hold-down made of metal and disposed to correspond to a first positioning hole and a second positioning hole, respectively. The housing includes a CPU board opposed surface to be opposed to a CPU board. The first hold-down includes a reinforcing plate part to cover the CPU board opposed surface around the corresponding first positioning hole. The second hold-down includes a reinforcing plate part to cover the CPU board opposed surface around the corresponding second positioning hole.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: August 16, 2022
    Assignee: Japan Aviation Electronics Industry, Ltd.
    Inventors: Junji Oosaka, Yuichi Takenaga, Akihiro Matsunaga
  • Patent number: 11410935
    Abstract: A semiconductor package includes a cavity substrate, a semiconductor die, and an encapsulant. The cavity substrate includes a redistribution structure and a cavity layer on an upper surface of the redistribution structure. The redistribution structure includes pads on the upper surface, a lower surface, and sidewalls adjacent the upper surface and the lower surface. The cavity layer includes an upper surface, a lower surface, sidewalls adjacent the upper surface and the lower surface, and a cavity that exposes pads of the redistribution structure. The semiconductor die is positioned in the cavity. The semiconductor die includes a first surface, a second surface, sidewalls adjacent the first surface and the second surface, and attachment structures that are operatively coupled to the exposed pads. The encapsulant encapsulates the semiconductor die in the cavity and covers sidewalls of the redistribution structure.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: August 9, 2022
    Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.
    Inventors: Young Do Kweon, JeongByung Chae, DongJoo Park, ByoungWoo Cho, SeHwan Hong
  • Patent number: 11393758
    Abstract: A semiconductor device and associated methods are disclosed. In one example, dies are interconnected through a bridge in a substrate. A reference voltage stack extends over at least a portion of the interconnect bridge, and a passive component is coupled to the reference voltage stack. In one example, the passive component helps to reduce interference in the power supply to components in the semiconductor device, such as the dies and the interconnect bridge.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: July 19, 2022
    Assignee: Intel Corporation
    Inventors: Bok Eng Cheah, Jackson Chung Peng Kong, Loke Yip Foo, Wai Ling Lee
  • Patent number: 11380368
    Abstract: The disclosed chip includes a storage module, pins, a control module, a first connection and a second connection. The storage module includes a first and a second storage array groups, which respectively include a plurality of first storage arrays and a plurality of second storage arrays. The pins are located on the side of the first storage array group away from the second storage array group. The control module is located between the first storage array group and the second storage array group. The first connection pin connects to the control module; and the second connection connects the control module to the first and the second storage array groups. The first connection line has a length less than the distance from the control module to the second storage array group at far side of the control module. The chip reduces the parasitic capacitance introduced by the first connection.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: July 5, 2022
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: KangLing Ji, Hongwen Li, Kai Tian
  • Patent number: 11362080
    Abstract: A semiconductor arrangement includes at least one switching device, electrically coupled between a first terminal and a second terminal, at least one diode, coupled in parallel to the at least one switching device between the first terminal and the second terminal, at least one bonding pad, and at least one electrically connecting element. Each of the at least one electrically connecting element is arranged to electrically couple one of the at least one switching device to one of the at least one diode. Each electrically connecting element includes a first end, a second end, and a middle section, and for at least one of the electrically connecting element, the first end is mechanically coupled to the respective switching device, the second end is mechanically coupled to the respective diode, and the middle section is mechanically coupled to at least one of the at least one bonding pad.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: June 14, 2022
    Inventors: Christian Robert Mueller, Christoph Urban
  • Patent number: 11355475
    Abstract: Methods of singulation and bonding, as well as structures formed thereby, are disclosed. A method includes singulating a first chip and after the singulating the first chip, bonding the first chip to a second chip. The first chip includes a first semiconductor substrate and a first interconnect structure on a front side of the first semiconductor substrate. The singulating the first chip includes etching through a back side of the first semiconductor substrate through the first interconnect structure.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: June 7, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Patent number: 11348861
    Abstract: A semiconductor package includes a semiconductor die having a semiconductor device, and first and second contact pads arranged on opposite surfaces of the die. The semiconductor die is embedded in a dielectric layer. The semiconductor package also includes one or more first package contact pads and one or more second package contact pads arranged on a first major surface of the semiconductor package. The first contact pad of the die is coupled to the one or more first package contact pads, and the second contact pad of the die is coupled to the one or more second package contact pads. In operation, the semiconductor device causes a current path between the first contact pad and the second contact pad. The package contact pads are arranged on the first major surface of the semiconductor package to provide multiple non-parallel current paths.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: May 31, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Sergey Yuferev, Robert Fehler, Petteri Palm
  • Patent number: 11335633
    Abstract: Provided is a circuit module including a power supply chip module, a load chip module, and a system board. A power supply output terminal group of the power supply chip module is arranged side by side in a row along a side of the power supply chip module board, the power supply input terminal group of a load chip module includes a specific terminal group arranged in a specific row that is a row along a side of the load chip module board, and a wiring width along an arrangement direction of the power supply output terminal group of a wiring pattern in which the power supply output terminal group is connected to the system board is equal to or more than a wiring width W31 along an arrangement direction of the specific terminal group of the wiring pattern in which the specific terminal group is connected to the system board.
    Type: Grant
    Filed: May 27, 2019
    Date of Patent: May 17, 2022
    Assignee: AISIN CORPORATION
    Inventors: Takashi Kusano, Takanobu Naruse
  • Patent number: 11335647
    Abstract: Apparatuses relating generally to a microelectronic package having protection from electromagnetic interference are disclosed. In an apparatus thereof, a platform has an upper surface and a lower surface opposite the upper surface and has a ground plane. A microelectronic device is coupled to the upper surface of the platform. Wire bond wires are coupled to the ground plane with a pitch. The wire bond wires extend away from the upper surface of the platform with upper ends of the wire bond wires extending above an upper surface of the microelectronic device. The wire bond wires are spaced apart from one another to provide a fence-like perimeter to provide an interference shielding cage. A conductive layer is coupled to at least a subset of the upper ends of the wire bond wires for electrical conductivity to provide a conductive shielding layer to cover the interference shielding cage.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: May 17, 2022
    Assignee: Invensas LLC
    Inventors: Shaowu Huang, Javier A. Delacruz
  • Patent number: 11336762
    Abstract: An electronic device comprises: a first plate configured to face one surface of the electronic device; a second plate configured to face in a direction opposite to the first plate; a side bezel structure connected to the first plate and the second plate and configured to surround the side of the electronic device; and a printed circuit board mounted in the electronic device and configured to be connected to the side bezel structure, wherein the printed circuit board comprises: a ground area; a first conductive pad, disposed in one area of the printed circuit board, and configured to couple the side bezel structure and the printed circuit board; and a second conductive pad electrically connected to the ground area and disposed between the first conductive pad and the ground area, wherein the first conductive pad and the second conductive pad may be disposed at an interval through which a current, having a voltage equal to or greater than a threshold voltage between the first conductive pad and a second electro
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: May 17, 2022
    Assignees: Samsung Electronics Co., Ltd., UNIST (Ulsan National Institute of Science and Technology)
    Inventors: Jongsung Lee, Cheolgu Jo, Byongsu Seol, Jingook Kim, Junsik Park
  • Patent number: 11335777
    Abstract: Disclosed herein are integrated circuit (IC) components with substrate cavities, as well as related techniques and assemblies. In some embodiments, an IC component may include a substrate, a device layer on the substrate, a plurality of interconnect layers on the device layer, and a cavity in the substrate.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: May 17, 2022
    Assignee: Intel Corporation
    Inventors: Kevin L. Lin, Paul B. Fischer, Han Wui Then, Sansaptak Dasgupta, Marko Radosavljevic, Ibrahim Ban
  • Patent number: 11307525
    Abstract: A printed circuit board comprises a first mounting surface, a second mounting surface, and a piezoelectric transformer. The piezoelectric transformer has a piezoelectric substance, external electrodes, and a frame substrate. The second mounting surface has a projection region. There is a first region from a first location, where an end portion further from the output electrode out of end portions of the input electrode is projected onto the second mounting surface in the projection region, to a second location, where an end portion closer to the output electrode out of the end portions of the input electrode is projected onto the second mounting surface, the first region being a mounting allowed region where an electronic component is mounted.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: April 19, 2022
    Assignee: Canon Kabushiki Kaisha
    Inventors: Taro Minobe, Norikazu Sugiyama, Ryo Matsumura
  • Patent number: 11309626
    Abstract: A wireless communication device is provided and includes a communication module, a dust and moisture resistant adhesive, and a nano-metallic layer. The communication module includes a circuit board, a communication chip and a plurality of passive components mounted on a carrying surface of the circuit board, and an insulating sheet that is disposed on the passive components and that has a thickness smaller than or equal to 150 ?m. The dust and moisture resistant adhesive covers any electrically conductive portions of the communication module on the carrying surface. The nano-metallic layer covers the dust and moisture resistant adhesive, the communication chip, the passive components, and the insulating sheet, and is electrically coupled to a grounding portion of the circuit board. The wireless communication device does not include any grounding metal housing mounted on the circuit board.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: April 19, 2022
    Assignee: AZUREWAVE TECHNOLOGIES, INC.
    Inventors: Chih-Hao Liao, Hsin-Yeh Huang, Shu-Han Wu
  • Patent number: 11309259
    Abstract: A high frequency module in which warpage does not easily occur is provided by adjusting linear expansion coefficient, glass transition temperature, and elastic modulus of a sealing resin layer. The high frequency module includes a wiring board, a first component mounted on a lower surface of the wiring board, a plurality of connection terminals, a first sealing resin layer that coats the first component and the connection terminal, a plurality of second components mounted on an upper surface of the wiring board, a second sealing resin layer coating the second components, and a shield film. The first sealing resin layer is formed thinner than the second sealing resin layer, and the first sealing resin layer has the linear expansion coefficient of the resin smaller than the linear expansion coefficient of the resin of the second sealing resin layer.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: April 19, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Tadashi Nomura, Takafumi Kusuyama
  • Patent number: 11300838
    Abstract: A transparent display device has a first substrate, a second substrate, and a display medium disposed between the first substrate and the second substrate. A pixel unit of the transparent display includes a transparent region and a display region. In the display region, a first reflective material is disposed between the first substrate and the display medium, and a second reflective material is disposed between the second substrate and the display medium.
    Type: Grant
    Filed: November 18, 2020
    Date of Patent: April 12, 2022
    Assignee: InnoLux Corporation
    Inventors: Masahiro Yoshiga, Satoru Takahashi, Toshiya Inada
  • Patent number: 11297715
    Abstract: A solderable circuit board module system includes at least a first solderable circuit board module and a second solderable circuit board module, wherein the first solderable circuit board module has a first module circuit board having a top side and an underside provided for placement on a motherboard, wherein on the underside of the first module circuit board, solder connection contacts are arranged in a first frame-shaped contact region around a central middle section, which is free of connection contacts. The second solderable circuit board module has additional solder connection contacts, which form an outer frame around the first frame-shaped contact region, as a second group.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: April 5, 2022
    Assignee: PHYTEC Messtechnik GmbH
    Inventor: Bodo Huber
  • Patent number: 11289412
    Abstract: A semiconductor package includes a multilayer substrate including a dielectric layer, a first conductive layer forming a first set of electrical contacts, a second conductive layer forming package electrical contacts and two capacitor electrical contacts, conductive vias extending through the dielectric layer between the first conductive layer with the second conductive layer, and a solder mask layer over the second conductive layer. The semiconductor package further includes a semiconductor die on the first side of the multilayer substrate electrically connected a capacitor on the second side of the multilayer substrate. A recessed portion of the capacitor is within a capacitor opening of the solder mask layer between the two capacitor electrical contacts and a board-side surface of the solder mask layer.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: March 29, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jaimal Mallory Williamson, Snehamay Sinha
  • Patent number: 11289438
    Abstract: According to an aspect of the inventive concept, there is provided a die-to-wafer bonding structure including a die having a first test pad, a first bonding pad formed on the first test pad, and a first insulating layer, the first bonding pad penetrates the first insulating layer. The structure may further include a wafer having a second test pad, a second bonding pad formed on the second test pad, and a second insulating layer, the second bonding pad penetrates the second insulating layer. The structure may further include a polymer layer surrounding all side surfaces of the first bonding pad and all side surfaces of the second bonding pad, the polymer layer being arranged between the die and the wafer. Additionally, the wafer and the die may be bonded together.
    Type: Grant
    Filed: August 5, 2020
    Date of Patent: March 29, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jiseok Hong, Unbyoung Kang, Myungsung Kang, Taehun Kim, Sangcheon Park, Hyuekjae Lee, Jihwan Hwang
  • Patent number: 11276657
    Abstract: A component includes a plurality of electrical connections on a process side opposed to a back side of the component. Each electrical connection includes an electrically conductive multi-layer connection post protruding from the process side. A printed structure includes a destination substrate and one or more components. The destination substrate has two or more electrical contacts and each connection post is in contact with, extends into, or extends through an electrical contact of the destination substrate to electrically connect the electrical contacts to the connection posts. The connection posts or electrical contacts are deformed. Two or more connection posts can be electrically connected to a common electrical contact.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: March 15, 2022
    Assignee: X Display Company Technology Limited
    Inventors: Carl Prevatte, Christopher Bower, Ronald S. Cok, Matthew Meitl
  • Patent number: 11275412
    Abstract: A detection system for non-standard connection interface through an adapter card. In the detection system, snaps of a first assembly are inserted through fastening slots of an adapter card, to make the first assembly and the adapter card fasten and engage with each other; the snaps of the first assembly are further inserted through engaging slots of a second assembly, to make the first assembly, the adapter card and the second assembly engage and fasten with each other; a motherboard is electrically connected to the adapter card, and the adapter card is electrically connected to a standard test adapter card, and the standard test adapter card is electrically connected to a standard BSI development test fixture, thereby achieving the technical effect of restraining protection for the adapter card and improvement of stability in detection for the non-standard connection interface.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: March 15, 2022
    Assignees: Inventec (Pudong) Technology Corporation, Inventec Corporation
    Inventor: Lin Zhang
  • Patent number: 11270991
    Abstract: Integrated circuits (ICs) employing front side (FS) back end-of-line (BEOL) (FS-BEOL) input/output (I/O) routing and back side (BS)) BEOL (BS-BEOL) power routing for current flow organization, and related IC packages and methods of fabricating are disclosed. The IC includes a FS-BEOL metallization structure disposed on a first side of a semiconductor layer and a BS-BEOL metallization structure disposed on a second side of the semiconductor layer. The FS-BEOL metallization structure is configured to route I/O signals to the semiconductor devices. The FS-BEOL metallization structure of the IC is also configured to receive power signals to be routed to the semiconductor devices.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: March 8, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Bharani Chava, Stanley Seungchul Song, Mohammed Yousuff Shariff
  • Patent number: 11268977
    Abstract: An inertial sensor includes: a sensor unit; a base substrate having the sensor unit arranged at one surface thereof and having a first lateral surface and a second lateral surface; a package accommodating the sensor unit and the base substrate and having an inner bottom surface, a first inner wall surface, and a second inner wall surface; a first adhesive bonding together an other surface of the base substrate and an inner bottom surface of the package; a second adhesive bonding together the first inner wall surface of the package and the first lateral surface; and a third adhesive bonding together the second inner wall surface of the package and the second lateral surface.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: March 8, 2022
    Inventor: Fumiya Ito
  • Patent number: 11270967
    Abstract: There is provided a method for manufacturing a semiconductor device comprising: forming a first organic insulating layer on a semiconductor region; forming a bump base film including an edge portion contacting with the first organic insulating layer; performing heat treatment of the bump base film; and forming a second organic insulating layer so as to cover the edge portion of the bump base film and the first organic insulating layer around the bump base film while contacting with the first organic insulating layer, the second organic insulating layer being provided with a first opening that exposes a surface of the bump base film.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: March 8, 2022
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Keita Matsuda
  • Patent number: 11264319
    Abstract: Provided is a storage system including a decoupling device having a plurality of unit capacitors. The storage system includes a storage device, a control device, and a decoupling device disposed on a circuit substrate. The storage device is configured to receive and store data from the control device. The control device is configured to generate an inner voltage. The decoupling device is connected to the control device and decouples the inner voltage. The decoupling device includes a plurality of unit capacitors constituting a plurality of decoupling capacitors. Each of the unit capacitors includes a plurality of capacitor elements, a first terminal, and a second terminal. Some of the unit capacitors are selectively connected with each other to constitute the decoupling capacitors having various capacitances.
    Type: Grant
    Filed: January 13, 2021
    Date of Patent: March 1, 2022
    Assignee: SK hynix Inc.
    Inventor: Bok Kyu Choi
  • Patent number: 11254558
    Abstract: A micro-electrical-mechanical system (MEMS) assembly includes a micro-electrical-mechanical system (MEMS) actuator configured to be coupled, on a lower surface, to a printed circuit board, an image sensor assembly coupled to an upper surface of the micro-electrical-mechanical system (MEMS) actuator, and a holder assembly coupled to and positioned with respect to the micro-electrical-mechanical system (MEMS) actuator.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: February 22, 2022
    Assignee: MEMS DRIVE (NANJING) CO., LTD.
    Inventors: Gerardo Morabito, Guiqin Wang
  • Patent number: 11223907
    Abstract: The present application relates to structures for supporting mechanical, electrical and/or electromechanical components, devices and/or systems and to methods of fabricating such structures. The application describes a primary die comprising an aperture extending through the die. The aperture is suitable for receiving a secondary die. A secondary die may be provided within the aperture of the primary die.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: January 11, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Rkia Achehboune, Roberto Brioschi
  • Patent number: 11219120
    Abstract: A component carrier includes a stack comprising at least one electrically insulating layer structure and/or at least one electrically conductive layer structure, a component embedded in the stack, and at least one stress relief opening formed in each of the at least one electrically conductive layer structure arranged in the stack on one side of the component so that a portion of the stack extending from an exterior main surface of the component carrier up to a main surface of the component on said side and including the at least one stress relief opening is free of electrically conductive material.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: January 4, 2022
    Assignee: AT&S (China) Co. Ltd.
    Inventors: Mikael Tuominen, Artan Baftiri, Nick Xin
  • Patent number: 11194935
    Abstract: Secure IoT devices and methods of use are disclosed herein. An example Internet-of-Things (IoT) device includes an interface for transmitting and receiving data on a network; and a chip comprising a reconfigurable hardware core configured to transmit the data using the interface. The reconfigurable hardware core is not vulnerable to malicious attacks can be used to replace a central processing unit (CPU) which is vulnerable to malicious attacks.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: December 7, 2021
    Inventors: Iurii V. Iuzifovich, Oleg Margulis, Iurii I. Iuzifovich
  • Patent number: 11179797
    Abstract: An article comprising additively manufactured metal portions is described. The article comprises a first additively manufactured metal portion, and a second additively manufactured metal portion coupled to the first additively manufactured metal portion at a welded joint. The article further comprises a resistive heating material disposed within an interior of the welded joint, the resistive heating material comprising a different material than the first additively manufactured metal portion and the second additively manufactured metal portion.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: November 23, 2021
    Assignee: THE BOEING COMPANY
    Inventors: Daniel J. Braley, Brandon Heath Wegge, Elaine MacDonald
  • Patent number: 11183461
    Abstract: A method of manufacturing a semiconductor structure includes following operations. A first die is provided. A first molding is formed to encapsulate the first die. A second die is disposed over the first molding. A mold chase is disposed over the second die and the first molding. The mold chase includes a protrusion protruded from the mold chase towards the first molding. A molding material is disposed between the mold chase and the first molding. A second molding is formed to surround the second die. The second die is at least partially covered by the second molding. The disposing of the mold chase includes surrounding the protrusion of the mold chase by the molding material.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: November 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chen-Hua Yu, Kai-Chiang Wu, Chun-Lin Lu
  • Patent number: 11178755
    Abstract: A flexible printed circuit board of the present invention includes an insulating base film and an electrode stacked on a first surface of the base film, in which the electrode includes a low-melting-point metal layer on a surface of the electrode, and a plate- or strip-like rigid member electrically insulated from the electrode is disposed in a region of a second surface of the base film opposite from the electrode.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: November 16, 2021
    Assignees: SUMITOMO ELECTRIC INDUSTRIES, LTD., SUMITOMO ELECTRIC PRINTED CIRCUITS, INC.
    Inventors: Katsunari Mikage, Masamichi Yamamoto, Junichi Okaue, Hiroshi Ueda
  • Patent number: 11175014
    Abstract: An optoelectronically functional multilayer structure as well as related methods of manufacturing an optoelectronically functional multilayer structure are described herein.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: November 16, 2021
    Assignee: TACTOTEK OY
    Inventors: Juha-Matti Hintikka, Miikka Kärnä, Heikki Tuovinen, Tuomas Nieminen, Johannes Soutukorva, Ville Wallenius, Tero Rajaniemi, Tomi Simula, Jari Lihavainen, Mikko Heikkinen, Jarmo Sääski, Hasse Sinivaara, Antti Keränen, Ilpo Hänninen
  • Patent number: 11178768
    Abstract: Three-dimensional (3-D) volumetric board architectural design provides technical solutions to technical problems facing miniaturization of circuit boards. The 3-D volumetric architecture includes using more of the unused volume in the vertical dimension (e.g., Z-dimension) to increase the utilization of the total circuit board volume. The 3-D volumetric architecture is realized by mounting components on a first PCB and on a second PCB, and inverting and suspending the second PCB above the first PCB. The use of 3-D volumetric board architectural design further enables formation of a shielded FEMIE, providing shielding and improved volumetric use with little or no reduction in system performance or increase in system Z-height.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: November 16, 2021
    Assignee: Intel Corporation
    Inventors: Khang Choong Yong, Stephen H. Hall, Tin Poay Chuah, Boon Ping Koh, Eng Huat Goh
  • Patent number: 11171110
    Abstract: A flip-chip integrated circuit die includes a front side including active circuitry formed therein and a plurality of bond pads in electrical communication with the active circuitry, at least two through-wafer vias extending at least partially though the die and having portions at a rear side of the die, and a bond wire external to the die and electrically coupling the portions of the at least two through-wafer vias at the rear side of the die.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: November 9, 2021
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Bharatjeet Singh Gill, Grant Darcy Poulin
  • Patent number: 11159166
    Abstract: A field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a look-up table (LUT), includes: multiple non-volatile memory cells therein configured to store multiple resulting values of the look-up table (LUT); and a programmable logic block therein having multiple static-random-access-memory (SRAM) cells configured to store the resulting values passed from the non-volatile memory cells, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values stored in the static-random-access-memory (SRAM) cells into its output.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: October 26, 2021
    Assignee: iCometrue Company Ltd.
    Inventors: Jin-Yuan Lee, Mou-Shiung Lin
  • Patent number: 11140774
    Abstract: A printed circuit board has first, second, and third printed circuit board sections extending along a longitudinal direction between two transverse edge outer sides of the printed circuit board. The printed circuit board has at each of its two longitudinal ends a respective transverse edge strip, which has regions of the first, second, and third printed circuit board sections and extends continuously transversely with respect to the longitudinal direction along a transverse edge outer side. A depression is formed in the third printed circuit board section on the first printed circuit board side between the two transverse edge strips. The first and/or second printed circuit board sections has a first metallic conductor track section that extends electrically conductively right into one or both of the two transverse edge strips.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: October 5, 2021
    Assignee: Vitesco Technologies GmbH
    Inventors: Christian Lammel, Guenther Ruppaner, Robert Bushnell, Detlev Bagung
  • Patent number: 11101221
    Abstract: Input/output pins for a chip-embedded substrate may be fabricated by applying a contact-distinct volume of solder to at least two contacts that are recessed within the chip-embedded substrate, temperature-cycling the chip-embedded substrate to induce solder reflow and define an input/output pin for each one of the at least two contacts, and machining the input/output pin for each one of the at least two contacts to extend exposed from the chip-embedded substrate to a common height within specification tolerance. Such a technique represents a paradigm shift in that the manufacturer of the chip-embedded substrate, as opposed to the immediate customer of the manufacturer, may assume the burden of quality control with respect to minimizing unintended solder void trapping under the input/output pins, thereby reinforcing existing customer loyalty and potentially attracting new customers.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: August 24, 2021
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Eung San Cho, Danny Clavette
  • Patent number: 11101186
    Abstract: A substrate structure includes a wiring structure and a supporter. The wiring structure includes a first dielectric structure, a first circuit layer, a second dielectric structure and a second circuit layer. The first circuit layer is disposed on the first dielectric structure. The second dielectric structure covers the first dielectric structure and the first circuit layer. A pad portion of the first circuit layer is exposed from the first dielectric structure, and the second circuit layer protrudes from the second dielectric structure. The supporter is disposed adjacent to the first dielectric structure of the wiring structure, and defines at least one through hole corresponding to the exposed pad portion of the first circuit layer.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: August 24, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng-Lin Ho, Chih-Cheng Lee
  • Patent number: 11088345
    Abstract: Provided is an organic light emitting diode display panel, including a substrate, a thin film transistor array layer and an organic light emitting diode layer, which are sequentially stacked and disposed on the substrate, and a thin film encapsulation layer covering the organic light emitting diode layer and an inorganic barrier layer disposed on an outer periphery of the thin film encapsulation layer, wherein at least two grooves in circle around a periphery of the organic light emitting diode layer are provided in the non-display area on the thin film transistor array layer, and the at least two grooves are correspondingly disposed to the thin film encapsulation layer, and the thin film encapsulation layer completely covers the organic light emitting diode layer, and fills the grooves corresponding to the thin film encapsulation layer. The OLED display panel possesses a dense and stable package structure.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: August 10, 2021
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Chen Zhao
  • Patent number: 11089675
    Abstract: A tamper sensor that includes a substrate and a conductive layer placed on the substrate. The tamper sensor also includes an insulation layer that is stacked on the conductive layer to form a layered tamper circuit. In addition, the substrate of the tamper sensor is the only substrate of the tamper sensor.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: August 10, 2021
    Assignee: TE CONNECTIVITY CORPORATION
    Inventors: Kenneth Jermstad, Michael Ritchie, Marcus Updyke, Anthony Ball
  • Patent number: 11079637
    Abstract: A display device includes: a display panel, a driving printed circuit board connected to the display panel, a control printed circuit board connected to the driving printed circuit board, at least one cable which connects the driving printed circuit board and the control printed circuit board, and a hinge connecting module disposed at both ends of at least one cable. Therefore, it is possible to implement an image having a high resolution by increasing the number of driving printed circuit boards attached to the display panel.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: August 3, 2021
    Assignee: LG Display Co., Ltd.
    Inventors: Hoontaek Lee, Jinwon Kim
  • Patent number: 11083121
    Abstract: A component mounting apparatus includes a nozzle that sucks a component supplied from a feeder, conveys the component to a predetermined position on a substrate, and mounts the component in the predetermined position. The component mounting apparatus controls an XY-robot to perform repeatedly the component mounting operation while performing a thermal correction from a start of the component mounting operation as a result of a power supply being turned on until an amount of positional deviation due to heat from the XY-robot reaches a steady state. After the steady state is achieved, the component mounting apparatus controls the XY-robot to perform repeatedly the component mounting operation while performing a steady state correction using a correction amount resulting immediately after the steady state is achieved without performing the thermal correction and controls the XY-robot to perform a dummy operation for maintaining the steady state during a standby period.
    Type: Grant
    Filed: January 25, 2016
    Date of Patent: August 3, 2021
    Assignee: FUJI CORPORATION
    Inventor: Takeshi Sakurayama
  • Patent number: 11071217
    Abstract: A device for fastening a plate, comprising a receiving structure with an abutment for receiving the plate and a fastener for fastening of the plate. The device should be produced at low cost, allow for average production tolerances and be susceptible to little wear. This is achieved in that a fastener for fastening comprise at least one snap arm, which can in each case swivel in an elastic manner about an axis perpendicular to a main surface of the plate and which presses the received plate against the abutment under pre-tension.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: July 20, 2021
    Assignee: Hella GmbH & Co. KGaA
    Inventor: Andreas Kupezki
  • Patent number: 11069633
    Abstract: The disclosure provides an electronic package, including a carrier, an electronic component disposed on the carrier, a buffer, and an antenna structure, wherein the antenna structure includes a metal frame disposed on the carrier and a wire disposed on the carrier and electrically connected to the metal frame, and the buffer covers the wire so as to reduce the emission wave speed of the wire and thus the wavelength is shorten, thereby satisfying the length requirement of the antenna within the limited space of the carrier and achieving an operating frequency radiated as required.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: July 20, 2021
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Ming-Fan Tsai, Chih-Hsien Chiu, Tsung-Hsien Tsai, Chao-Ya Yang, Chia-Yang Chen
  • Patent number: 11024702
    Abstract: A stacked electronic structure comprises: a substrate and a magnetic device, wherein electronic devices and conductive pillars are disposed on and electrically connected to the substrate, wherein a molding body encapsulates the electronic devices, and the magnetic device is disposed over and electrically connected to the conductive pillars, wherein at least one recess or groove can be formed on the bottom surface of the conductive pillar, such as copper pillar, to help the venting of the soldering material as well as to increase the soldering area.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: June 1, 2021
    Assignee: CYNTEC CO., LTD.
    Inventors: Bau-Ru Lu, Jianhong Zeng, Chun Hsien Lu
  • Patent number: 11013121
    Abstract: The present disclosure relates to a circuit bonding structure, a circuit bonding method, and a display device. The circuit bonding structure includes a carrying portion configured to carry a driving circuit and having two sides which are adjacent to each other and form a preset acute angle and a preset circuit board having a bonding region having two sides which are adjacent to each other and form a preset acute angle. The driving circuit is bonded to the bonding region by the carrying portion.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: May 18, 2021
    Assignees: BOE Technology Group Co., Ltd., BOE (Hebei) Mobile Display Technology Co., Ltd.
    Inventors: Zhifu Yang, Zhiyang Cui, Dahua Zhu, Lei Zhao
  • Patent number: 11004574
    Abstract: An anisotropic conductive film manufacturing method capable of reducing manufacturing costs. Also, an anisotropic conductive film capable of suppressing the occurrence of conduction defects. The anisotropic conductive film manufacturing method includes: a holding step of supplying conductive particles having a plurality of particle diameters on a member having a plurality of opening parts, and holding the conductive particles in the opening parts; and a transfer step of transferring the conductive particles held in the opening parts to an adhesive film. In the particle diameter distribution graph (X-axis: particle diameter (?m), Y-axis: number of particles) of the conductive particles held in the opening parts, the shape of the graph is such that the slope is substantially infinite in a range at or above a maximum peak particle diameter.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: May 11, 2021
    Assignee: DEXERIALS CORPORATION
    Inventor: Junichi Nishimura