Connection Of Components To Board Patents (Class 361/760)
  • Patent number: 11101221
    Abstract: Input/output pins for a chip-embedded substrate may be fabricated by applying a contact-distinct volume of solder to at least two contacts that are recessed within the chip-embedded substrate, temperature-cycling the chip-embedded substrate to induce solder reflow and define an input/output pin for each one of the at least two contacts, and machining the input/output pin for each one of the at least two contacts to extend exposed from the chip-embedded substrate to a common height within specification tolerance. Such a technique represents a paradigm shift in that the manufacturer of the chip-embedded substrate, as opposed to the immediate customer of the manufacturer, may assume the burden of quality control with respect to minimizing unintended solder void trapping under the input/output pins, thereby reinforcing existing customer loyalty and potentially attracting new customers.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: August 24, 2021
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Eung San Cho, Danny Clavette
  • Patent number: 11101186
    Abstract: A substrate structure includes a wiring structure and a supporter. The wiring structure includes a first dielectric structure, a first circuit layer, a second dielectric structure and a second circuit layer. The first circuit layer is disposed on the first dielectric structure. The second dielectric structure covers the first dielectric structure and the first circuit layer. A pad portion of the first circuit layer is exposed from the first dielectric structure, and the second circuit layer protrudes from the second dielectric structure. The supporter is disposed adjacent to the first dielectric structure of the wiring structure, and defines at least one through hole corresponding to the exposed pad portion of the first circuit layer.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: August 24, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng-Lin Ho, Chih-Cheng Lee
  • Patent number: 11089675
    Abstract: A tamper sensor that includes a substrate and a conductive layer placed on the substrate. The tamper sensor also includes an insulation layer that is stacked on the conductive layer to form a layered tamper circuit. In addition, the substrate of the tamper sensor is the only substrate of the tamper sensor.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: August 10, 2021
    Assignee: TE CONNECTIVITY CORPORATION
    Inventors: Kenneth Jermstad, Michael Ritchie, Marcus Updyke, Anthony Ball
  • Patent number: 11088345
    Abstract: Provided is an organic light emitting diode display panel, including a substrate, a thin film transistor array layer and an organic light emitting diode layer, which are sequentially stacked and disposed on the substrate, and a thin film encapsulation layer covering the organic light emitting diode layer and an inorganic barrier layer disposed on an outer periphery of the thin film encapsulation layer, wherein at least two grooves in circle around a periphery of the organic light emitting diode layer are provided in the non-display area on the thin film transistor array layer, and the at least two grooves are correspondingly disposed to the thin film encapsulation layer, and the thin film encapsulation layer completely covers the organic light emitting diode layer, and fills the grooves corresponding to the thin film encapsulation layer. The OLED display panel possesses a dense and stable package structure.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: August 10, 2021
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Chen Zhao
  • Patent number: 11079637
    Abstract: A display device includes: a display panel, a driving printed circuit board connected to the display panel, a control printed circuit board connected to the driving printed circuit board, at least one cable which connects the driving printed circuit board and the control printed circuit board, and a hinge connecting module disposed at both ends of at least one cable. Therefore, it is possible to implement an image having a high resolution by increasing the number of driving printed circuit boards attached to the display panel.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: August 3, 2021
    Assignee: LG Display Co., Ltd.
    Inventors: Hoontaek Lee, Jinwon Kim
  • Patent number: 11083121
    Abstract: A component mounting apparatus includes a nozzle that sucks a component supplied from a feeder, conveys the component to a predetermined position on a substrate, and mounts the component in the predetermined position. The component mounting apparatus controls an XY-robot to perform repeatedly the component mounting operation while performing a thermal correction from a start of the component mounting operation as a result of a power supply being turned on until an amount of positional deviation due to heat from the XY-robot reaches a steady state. After the steady state is achieved, the component mounting apparatus controls the XY-robot to perform repeatedly the component mounting operation while performing a steady state correction using a correction amount resulting immediately after the steady state is achieved without performing the thermal correction and controls the XY-robot to perform a dummy operation for maintaining the steady state during a standby period.
    Type: Grant
    Filed: January 25, 2016
    Date of Patent: August 3, 2021
    Assignee: FUJI CORPORATION
    Inventor: Takeshi Sakurayama
  • Patent number: 11069633
    Abstract: The disclosure provides an electronic package, including a carrier, an electronic component disposed on the carrier, a buffer, and an antenna structure, wherein the antenna structure includes a metal frame disposed on the carrier and a wire disposed on the carrier and electrically connected to the metal frame, and the buffer covers the wire so as to reduce the emission wave speed of the wire and thus the wavelength is shorten, thereby satisfying the length requirement of the antenna within the limited space of the carrier and achieving an operating frequency radiated as required.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: July 20, 2021
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Ming-Fan Tsai, Chih-Hsien Chiu, Tsung-Hsien Tsai, Chao-Ya Yang, Chia-Yang Chen
  • Patent number: 11071217
    Abstract: A device for fastening a plate, comprising a receiving structure with an abutment for receiving the plate and a fastener for fastening of the plate. The device should be produced at low cost, allow for average production tolerances and be susceptible to little wear. This is achieved in that a fastener for fastening comprise at least one snap arm, which can in each case swivel in an elastic manner about an axis perpendicular to a main surface of the plate and which presses the received plate against the abutment under pre-tension.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: July 20, 2021
    Assignee: Hella GmbH & Co. KGaA
    Inventor: Andreas Kupezki
  • Patent number: 11024702
    Abstract: A stacked electronic structure comprises: a substrate and a magnetic device, wherein electronic devices and conductive pillars are disposed on and electrically connected to the substrate, wherein a molding body encapsulates the electronic devices, and the magnetic device is disposed over and electrically connected to the conductive pillars, wherein at least one recess or groove can be formed on the bottom surface of the conductive pillar, such as copper pillar, to help the venting of the soldering material as well as to increase the soldering area.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: June 1, 2021
    Assignee: CYNTEC CO., LTD.
    Inventors: Bau-Ru Lu, Jianhong Zeng, Chun Hsien Lu
  • Patent number: 11013121
    Abstract: The present disclosure relates to a circuit bonding structure, a circuit bonding method, and a display device. The circuit bonding structure includes a carrying portion configured to carry a driving circuit and having two sides which are adjacent to each other and form a preset acute angle and a preset circuit board having a bonding region having two sides which are adjacent to each other and form a preset acute angle. The driving circuit is bonded to the bonding region by the carrying portion.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: May 18, 2021
    Assignees: BOE Technology Group Co., Ltd., BOE (Hebei) Mobile Display Technology Co., Ltd.
    Inventors: Zhifu Yang, Zhiyang Cui, Dahua Zhu, Lei Zhao
  • Patent number: 11004574
    Abstract: An anisotropic conductive film manufacturing method capable of reducing manufacturing costs. Also, an anisotropic conductive film capable of suppressing the occurrence of conduction defects. The anisotropic conductive film manufacturing method includes: a holding step of supplying conductive particles having a plurality of particle diameters on a member having a plurality of opening parts, and holding the conductive particles in the opening parts; and a transfer step of transferring the conductive particles held in the opening parts to an adhesive film. In the particle diameter distribution graph (X-axis: particle diameter (?m), Y-axis: number of particles) of the conductive particles held in the opening parts, the shape of the graph is such that the slope is substantially infinite in a range at or above a maximum peak particle diameter.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: May 11, 2021
    Assignee: DEXERIALS CORPORATION
    Inventor: Junichi Nishimura
  • Patent number: 10991787
    Abstract: Display device and method of manufacturing the display device are provided. According to an exemplary embodiment of the present disclosure, a display device includes a display panel having a display area and a pad area, which is spaced apart from the display area; a protective film disposed on one surface of the display panel; and a middle layer interposed between the protective film and the display panel, wherein the middle layer has a light-blocking area and a light-transmitting area, the light-blocking area overlaps with the display area, and the light-transmitting area overlaps with the pad area.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: April 27, 2021
    Inventor: Hirotsugu Kishimoto
  • Patent number: 10955882
    Abstract: A solid-state drive device includes a memory module in which at least one non-volatile memory device is mounted, a first heat storage unit and a second heat storage unit covering upper and lower parts of the memory module, respectively, to store heat emitted by the memory module, and having at least portions connected to each other, respectively, a cover having a space in which the memory module and the first and second heat storage units are received and arranged with a spacing distance from the first and second heat storage units, respectively, and an inner frame arranged between the cover and at least one of the first and second heat storage units, to provide the spacing distance.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: March 23, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yusuf Cinar, Jae Hong Park, Han Hong Lee, Jung Hoon Kim, Ki Taek Lee
  • Patent number: 10950537
    Abstract: A package structure including a capacitor mounted within a cavity in the package substrate is disclosed. The package structure may additionally include a die mounted to a die side surface of the package substrate, and the opposing land side surface of the package substrate may be mounted to a printed circuit board (PCB). The capacitor may be mounted within a cavity formed in the die side surface of the package substrate or the land side surface of the package substrate. Mounting a capacitor within a cavity may reduce the form factor of the package. The die may be mounted within a cavity formed in the die side surface of the package substrate. Solder balls connecting the package to the PCB may be mounted within one or more cavities formed in one or both of the package substrate and the PCB.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: March 16, 2021
    Assignee: Intel Corporation
    Inventors: Md Altaf Hossain, Scott Gilbert
  • Patent number: 10937742
    Abstract: A package includes a plurality of dies, a wall structure, an encapsulant, and a redistribution structure. The wall structure surrounds at least one of the dies. The encapsulant includes a first portion, a second portion, and a third portion. The first portion is encircled by the wall structure. The second portion encircles the wall structure. The third portion connects the first portion and the second portion. The redistribution structure is disposed on the encapsulant and is electrically connected to the dies and the wall structure.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: March 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Po-Hao Tsai
  • Patent number: 10923433
    Abstract: A fan-out semiconductor package includes a connection member including an insulating layer and a redistribution layer, a semiconductor chip disposed on the connection member, an encapsulant encapsulating the semiconductor chip, and an electromagnetic wave shielding layer disposed on the semiconductor chip and including a plurality of degassing holes. The electromagnetic wave shielding layer includes a first region and a second region in which densities of the degassing holes are different from each other, the first region having a density of the degassing holes higher than a density of the degassing holes in the second region.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: February 16, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Mi Ja Han, Dae Hyun Park, Seong Hwan Lee, Sang Jong Lee
  • Patent number: 10910357
    Abstract: The present disclosure provides a semiconductor package structure. The semiconductor package structure includes a first die, a second die and a hybrid bonding structure disposed between the first die and the second die. The first die includes a first front side and a first back side opposite to the first front side. The second die includes a second front side and a second back side opposite to the second front side. The hybrid bonding structure is disposed between the first back side of the first die and the second front side of the second die. The first die and the second die are bonded to each other by the hybrid bonding structure. The hybrid bonding structure includes an organic barrier layer and an inorganic barrier layer bonded to each other.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: February 2, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Shing-Yih Shih
  • Patent number: 10905017
    Abstract: The disclosure relates to methods and compositions for direct printing of circuit boards having an electromagnetically-shielded tracks and/or components. Specifically, the disclosure relates to the direct, uninterrupted and continuous 3D printing of insulation-jacketed tracks and/or components with metallic shielding sleeves or capsule.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: January 26, 2021
    Assignee: Nano Dimension Technologies Ltd.
    Inventors: Avi Shabtai, Michael Partosh
  • Patent number: 10905010
    Abstract: A connecting arrangement includes an electronic component and a printed circuit board, and a method includes establishing a solder connection between the component and circuit board. The component has a housing with a support area, and a contact element with a first contact area running parallel to the support area of the housing, a second contact area at a prespecified angle relative to the first contact area, and a rounded transition region formed between the first and second contact areas. The circuit board has a first surface with a soldering area including a constriction, a first section, and a second section connected to the first section via the constriction. The transition region is in a region of the constriction. The second contact area is connected to the second section via a solder connection. The support area is at an angle relative to the first surface corresponding to the prespecified angle.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: January 26, 2021
    Assignee: Robert Bosch GmbH
    Inventors: Helmut Seiband, Michael Schlitzkus, Sandra Heim, Stefan Lehenberger, Valentin Notemann
  • Patent number: 10903388
    Abstract: A main carrier wafer includes a first integrated network of electronic connections between front and back faces. A first electronic chip is mounted to the front face of the main carrier wafer and connected to the network of electronic connections of the main carrier wafer. A secondary carrier wafer includes a platform that extends over the first chip and a base the protrudes backwards with respect to the platform to a back end face facing the main wafer. A second integrated network of electronic connections is provided within the secondary carrier wafer. A second electronic chip is mounted on top of the platform and connected to the second integrated network. The second integrated network is further connected to the main carrier wafer at the back end face.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: January 26, 2021
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventor: Jean-Michel Riviere
  • Patent number: 10855333
    Abstract: An inductively coupled multi-channel digital isolator where the transmitter and receiver inductive loops of a given channel are coplanar. In the case where two adjacent channels flow data in opposite directions, the receiver inductive loops of a given channel include a large, generally conventional loop portion and a small loop portion that is located inside the transmitter inductive loops of the adjacent channels. The sizes of the small loop portion and the conventional loop portion are generally in the ratio of the magnetic flux in the conventional loop portion to the magnetic flux in the transmitter inductive loop. This size relationship results in the voltage of the small loop portion being very close but opposite in sign to the voltage in the conventional loop portion. As a result, there is minimal crosstalk from the transmitter inductive loop of one channel to the receiver inductive loop of the adjacent channel.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: December 1, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Kumar Anurag Shrivastava
  • Patent number: 10849227
    Abstract: A circuit card assembly (CCA) stack includes a first circuit card assembly (CCA) with circuit components mounted thereto, wherein the first CCA includes a power contact and a return contact for powering the first CCA. A plurality of additional CCAs in a stack with the first CCA, wherein each CCA in the plurality of additional CCAs includes respective power and return contacts, and wherein each CCA in the plurality of additional CCAs includes a first aperture and a second aperture for passage of power buses. The first power bus can include one or more power wires bonded to power contacts of the CCAs, and one or more return wires bonded to return contacts of the CCAs.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: November 24, 2020
    Assignee: Simmonds Precision Products, Inc.
    Inventors: Neal R. Whatcott, Jason Graham
  • Patent number: 10834853
    Abstract: A semiconductor device includes a substrate; a first functional circuit attached to the substrate; a first thermal circuit attached to the substrate, configured to utilize cryogenic liquid to cool the first functional circuit; a second functional circuit attached to the substrate; and a second thermal circuit attached to the substrate, configured to cool the second functional circuit without using the cryogenic liquid.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: November 10, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Mark E. Tuttle
  • Patent number: 10796604
    Abstract: An apparatus includes a simulated medicament delivery device and an electronic circuit system coupled to the simulated medicament delivery device. The electronic circuit system is configured to output an electronic output associated with a use of the simulated medicament delivery device.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: October 6, 2020
    Assignee: kaleo, Inc.
    Inventors: Eric S. Edwards, Evan T. Edwards, Mark J. Licata, Paul F. Meyers, T. Spencer Williamson, Kai R. Worrell, David A. Weinzierl
  • Patent number: 10790234
    Abstract: A method of manufacturing a component carrier includes providing a known-good layer stack comprising an already formed electrically conductive connection structure and a known-good cavity, and mounting a known-good component on the already formed electrically conductive connection structure in the cavity.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: September 29, 2020
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventors: Marco Gavagnin, Markus Leitgeb, Martin Schrems, Roland Winkler, Steve Anderson
  • Patent number: 10784191
    Abstract: A stacked and electrically interconnected structure is disclosed. The structure can comprise a first element and a second element directly bonded to the first element along a bonding interface without an intervening adhesive. A filter circuit can be integrally formed between the first and second elements along the bonding interface.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: September 22, 2020
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Shaowu Huang, Belgacem Haba, Javier A. DeLaCruz
  • Patent number: 10784208
    Abstract: The present disclosure provides a semiconductor package device and a method for manufacturing the same. In embodiments of the present disclosure, a semiconductor package device includes a carrier, a first antenna, a second antenna, a package body and a first shield. The carrier includes an antenna area and a component area. The first antenna is formed on the antenna area. The second antenna extends from the antenna area and over the first antenna. The second antenna is electrically connected to the first antenna. The package body includes a first portion covering the component area and a second portion covering the antenna area. The first shield is conformally formed on the first portion of the package body and exposes the second portion of package body.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: September 22, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Kuo-Hsien Liao, Cheng-Nan Lin, Chieh-Chen Fu
  • Patent number: 10785874
    Abstract: A technique includes coupling a resistor network to a plurality of card edge connectors. The resistor network has a resistance, and each card edge connector includes electrical contacts to couple a resistor of a circuit card assembly, when inserted into the card edge connector, to the resistor network to alter the resistance of the resistor network. The technique includes determining a state of the plurality of card edge connectors based on a signal that is provided by the resistor network.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: September 22, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Nilashis Dey
  • Patent number: 10772196
    Abstract: According to one embodiment, a display device includes a display panel including pad portions, a flexible printed circuit, the flexible printed circuit includes a base member with a first surface and a second surface, wiring lines, and a protective layer, and including a bend area, and a first edge and a second edge, the base member includes a groove portion located in the bend area and formed in the second surface, a first frame region between the first edge and the groove portion, and a second frame region between the second edge and the groove portion, a thickness of the base member in a position where the groove portion is formed is less than a thickness of the base member in a position which overlaps the first frame region and the second frame region.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: September 8, 2020
    Assignee: Japan Display Inc.
    Inventors: Kota Uogishi, Koji Hiramoto, Kengo Kowata
  • Patent number: 10756316
    Abstract: A device for mounting an electrical energy source in portable electronic equipment is provided, including a cavity and a cover configured to close the cavity, the cover including a housing configured to receive the energy source, the cover and the portable electronic equipment having complementary fixing means in order to retain the cover on the portable electronic equipment and to seal the cavity, and the cover including means for retaining the energy source in the housing of the cover.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: August 25, 2020
    Assignee: ETA SA Manufacture Horlogere Suisse
    Inventors: David Benjamin Kraehenbuehl, Martin Jufer
  • Patent number: 10757801
    Abstract: A printed circuit board having a substrate layer, at least one electrically conductive trace disposed on the substrate layer, and a solder mask layer disposed over the substrate layer and the electrically conductive trace, wherein the solder mask later includes a void region over at least a portion of the electrically conductive trace. Also, a method of optimizing printed circuit board designing including selecting printed circuit board data comprising at least a solder mask layer area, varying the solder mask layer area, determining an insertion loss value for each varied solder mask layer area, comparing the insertion loss values for each varied solder mask layer area, and selecting a solder mask layer area based on the comparing.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: August 25, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: David W. Engler, Stephen F. Contreras
  • Patent number: 10736217
    Abstract: A surface mounting component module according to one embodiment of the present invention comprises: a multi-layer substrate; a side via formed by penetrating the multi-layer substrate, and electrically connecting the multi-layer substrate; a side via pad positioned on at least one layer of the multi-layer substrate, and formed in the vicinity of the side via; and an RF pattern connected to the side via pad by a signal line, wherein all of the RF pattern, the side via, and the side via pad are electrically connected.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: August 4, 2020
    Assignee: LG INNOTEK CO., LTD.
    Inventor: Dong Woo Kim
  • Patent number: 10723920
    Abstract: A conductive adhesive contains a thermosetting resin (A), a conductive filler (B), and a filling-performance improver (C). The thermosetting resin (A) contains a first resin component (A1) having a first functional group, and a second resin component (A2) having a second functional group that reacts with the first functional group. The filling-performance improver (C) contains an organic salt. The conductive adhesive contains from 40 to 140 parts by mass of the filling-performance improver (C) relative to 100 parts by mass of the thermosetting resin.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: July 28, 2020
    Assignee: TATSUTA ELECTRIC WIRE & CABLE CO., LTD.
    Inventors: Yoshihiko Aoyagi, Osamu Isobe, Kenji Kamino
  • Patent number: 10715031
    Abstract: In order to achieve small noise and small vibration, as well as a small size and a low cost in a power converter including a capacitor module, there is provided a power converter including a power module and a capacitor module. The capacitor module includes: a plurality of capacitor elements each having a flat wound surface; an exterior case; a resin filler; and a restraint point. The exterior case has arranged therein an inclusion serving as a beam in a direction orthogonal to a flat wound surface of at least one capacitor element of the plurality of capacitor elements, and the at least one capacitor element, and the restraint point is arranged substantially in front of the flat wound surface via the inclusion.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: July 14, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kengo Nishimura, Satoshi Ishibashi, Masahiro Noguchi
  • Patent number: 10716211
    Abstract: A printed wiring board includes a plurality of first wirings and a plurality of second wirings. The plurality of first wirings each include a first via conductor disposed outside a first region, a second region, and a third region in a plan view, and a first conductor pattern extending from the first via conductor to the first region. The plurality of second wirings each include a second via conductor disposed outside the first region, the second region, and the third region, and a second conductor pattern extending from the second via conductor to the first region. A fourth region overlaps with a fifth region in the plan view, the fourth region being a region in which a plurality of first conductor patterns are disposed, the fifth region being a region in which a plurality of second conductor patterns are disposed.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: July 14, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Takashi Numagi, Shoji Matsumoto, Hiroyuki Yamaguchi, Youhei Tazawa
  • Patent number: 10709043
    Abstract: Disclosed is an electronic device. The electronic device includes a printed circuit board on which one or more circuit components are disposed, and an interposer surrounding at least some circuit components of the one or more circuit components and including an inner surface adjacent to the at least some circuit components and an outer surface facing away from the inner surface and having a plurality of through holes. The interposer is disposed on the printed circuit board such that one or more through holes of the plurality of through holes are electrically connected with a ground of the printed circuit board.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: July 7, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyelim Yun, Bongkyu Min, Dohoon Kim, Taewoo Kim, Jinyong Park, Jungje Bang, Hyeongju Lee
  • Patent number: 10658276
    Abstract: A device includes an integrated circuit (IC) die, a top-side base plate to which the IC die is mounted, and a body attached to the top-side base plate such that the IC die is inside the body, the body configured for attachment to a printed circuit board (PCB) such that the top-side base plate faces away from the PCB. The device may or may not include legs that abut the PCB upon installation.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: May 19, 2020
    Assignee: Tesla, Inc.
    Inventors: William Thomas Chi, Mehmet Ozbek, Satish Thuta
  • Patent number: 10624216
    Abstract: A wiring board includes, a base plate that has a first surface, a second surface opposite to the first surface, and a side surface coupled to the first surface and the second surface, a conductor provided on the side surface, and a protrusion provided over the side surface. The protrusion partitions the conductor into a first portion on the side surface that extends to the first surface and a second portion on the side surface that extends to the second surface. The protrusion has a solder wettability lower than the conductor and protrudes from the conductor.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: April 14, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Nobuo Taketomi, Takahiro Kitagawa, Mitsunori Abe, Shigeru Sugino, Kiyoyuki Hatanaka, Shigeo Iriguchi, Ryo Kanai
  • Patent number: 10622241
    Abstract: A method of dispersing semiconductor chips from a wafer of semiconductor chips onto a substrate while preserving the neighboring relationship of each chip to each adjacent chip is disclosed. The method includes dispersing the wafer into sequential columns of semiconductor chips with a first pitch between columns while preserving the neighboring relationship and sequentially dispersing the columns of semiconductor chips into rows of individual chips with a second pitch between rows onto a substrate while preserving the neighboring relationship.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: April 14, 2020
    Inventors: Chan-Long Shieh, Gang Yu
  • Patent number: 10622761
    Abstract: A movable floating connector is disclosed. In an embodiment, an apparatus includes a fixed structure coupled to a chassis, a movable floating connector assembly, and an elastic object. The movable floating connector assembly includes a receiving connector configured to engage with a module connector of an insertable module removable from the chassis. The elastic object is interfaced between at least a portion of the fixed structure and at least a portion of the movable floating connector assembly. The elastic object is configured to provide a force on the movable floating connector assembly against a direction of insertion of the insertable module to maintain a consistent engagement between the receiving connector of the movable floating connector assembly and the module connector of the insertable module across a variation in length in the direction of insertion.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: April 14, 2020
    Assignee: Facebook, Inc.
    Inventors: Joshua Held, Michael Haken, Tiffany Jin
  • Patent number: 10607952
    Abstract: In accordance with embodiments disclosed herein, there is provided a high density triple diamond stripline interconnect. An interconnect includes a first reference layer, a second reference layer disposed below the first reference layer, and a dielectric disposed between the first reference layer and the second reference layer. The interconnect further includes a first pair of conductors including a first conductor and a second conductor that are in a broadside-facing orientation within the dielectric below the first reference layer and above the second reference layer. The interconnect further includes a second pair of conductors including a third conductor and a fourth conductor that are in an edge-facing orientation within the dielectric below the first conductor and above the second conductor.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: March 31, 2020
    Assignee: Intel Corporation
    Inventor: Albert Sutono
  • Patent number: 10593636
    Abstract: Embodiments of the invention may include a packaged device that includes thermally stable radio frequency integrated circuits (RFICs). In one embodiment the packaged device may include an integrated circuit chip mounted to a package substrate. According to an embodiment, the package substrate may have conductive lines that communicatively couple the integrated circuit chip to one or more external components. One of the external components may be an RFIC module. The RFIC module may comprise an RFIC and an antenna. Additional embodiments may also include a packaged device that includes a plurality of cooling spots formed into the package substrate. In an embodiment the cooling spots may be formed proximate to interconnect lines the communicatively couple the integrated circuit chip to the RFIC.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: March 17, 2020
    Assignee: Intel Corporation
    Inventors: Georgios C. Dogiamis, Sasha N. Oster, Telesphor Kamgaing, Adel A. Elsherbini, Brandon M. Rawlings, Feras Eid
  • Patent number: 10580742
    Abstract: A method of manufacturing a wafer level fan-out package includes preparing a base substrate having a protrusion, providing a chip on a surface of the base substrate adjacent to and spaced from the protrusion, forming an encapsulation layer on the base substrate to encapsulate the chip and the protrusion, removing the base substrate to expose a surface of the chip and to form a recess corresponding to the protrusion in the encapsulation layer, and providing a passive element in the recession. The method obviates a problem of displacement of the passive element by thermal expansion of the encapsulation layer while it is being formed because the passive element is incorporated into the package after the encapsulation layer is formed.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: March 3, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Peng Zhang
  • Patent number: 10568216
    Abstract: A composite sheet includes a resin layer including a liquid crystal polymer as a main material and a first surface and a second surface facing away from each other, a conductor foil disposed on the first surface, and a powder layer including a powder of a liquid crystal polymer as a major component and located on an entirety of the second surface.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: February 18, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Hiroyuki Ohata
  • Patent number: 10535637
    Abstract: Methods to form stacked circuit assemblies include mounting a first wireless device component to a first surface of a substrate and placing a second wireless device component over the first wireless device component such that the first wireless device component is disposed between the second wireless device component and the first surface of the substrate such that a first overhanging portion of the second wireless device component extends beyond a periphery of the first wireless device component. The first wireless device component is in communication with the second wireless device component and second wireless device component is in communication with the substrate.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: January 14, 2020
    Assignee: Skyworks Solutions, Inc.
    Inventors: Darren Roger Frenette, George Khoury, Lori Ann DeOrio
  • Patent number: 10535614
    Abstract: A package includes a plurality of dies, a wall structure, an encapsulant, and a redistribution structure. The wall structure surrounds at least one of the dies. The encapsulant encapsulates the dies and the wall structure. A first portion of the encapsulant penetrates through the wall structure. The redistribution structure is disposed on the encapsulant and is electrically connected to the dies and the wall structure.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Po-Hao Tsai
  • Patent number: 10529666
    Abstract: A semiconductor structure includes a first die; a first molding encapsulating the first die; a second die disposed over the first molding, and including a first surface, a second surface opposite to the first surface, and a sidewall between the first surface and the second surface; and a second molding disposed over the first molding and surrounding the second die, wherein the first surface of the second die faces the first molding, and the second die is at least partially covered by the second molding.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: January 7, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chen-Hua Yu, Kai-Chiang Wu, Chun-Lin Lu
  • Patent number: 10517465
    Abstract: A cable connection structure includes: a cable having a core and a jacket made of an insulating material to cover the core; and a substrate connected with the cable. The substrate includes: a base material made of an insulating material; an external connection electrode formed on a surface of the base material and connected with the core; and a via provided in the base material and having an end exposed from a mounting surface of the substrate on which the cable is mounted, the via being connected with the external connection electrode. The via is provided at least at one of both ends of a surface of the external connection electrode perpendicular to an axial direction of the cable, on a proximal end side of the cable.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: December 31, 2019
    Assignee: OLYMPUS CORPORATION
    Inventor: Masato Mikami
  • Patent number: 10512171
    Abstract: The present invention relates to a method for producing a metal wire embedded flexible substrate from a laminate structure. The laminate structure includes a carrier substrate, a debonding layer disposed on at least one surface of the carrier substrate and including a polyimide resin, a metal wiring layer disposed in contact with the debonding layer, and a flexible substrate layer disposed in contact with the metal wiring layer. The adhesion strength between the metal wiring layer and the flexible substrate layer is greater than that between the metal wiring layer and the debonding layer. According to the method of the present invention, the flexible substrate with the metal wiring layer can be easily separated from the carrier substrate even without the need for other processes, such as laser and light irradiation.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: December 17, 2019
    Assignee: LG CHEM, LTD.
    Inventors: Hye Won Jeong, Bo Ra Shin, Kyungjun Kim, Ji Eun Myung, Yong Goo Son
  • Patent number: 10491728
    Abstract: A key module for a mobile terminal, and which includes a key having a neck part and a head key pressed to enter an input to the mobile terminal; a circuit support configured to support a circuit board having a dome terminal to be pressed when the key head is pressed for entering the input to the terminal; and a waterproof member positioned between the key and the circuit support and configured to block a moisture penetration path along a hole in a case member of the mobile terminal into which the key module is inserted.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: November 26, 2019
    Assignee: LG ELECTRONICS INC.
    Inventors: Ikhyun Jo, Sehoon Chun, Jangwoo Hong, Chalkee Jung