With Specific Lead Configuration Patents (Class 361/772)
  • Patent number: 10286860
    Abstract: The present invention provides an electricity storage unit in which the influence of noise from a circuit portion can be suppressed, and the circuit portion and a power storage element can be consolidated. The electricity storage unit includes a circuit portion on which an electronic component is mounted, power storage elements, and a holding member that holds the power storage elements. The holding member includes an electrically conductive shield wall portion between the circuit portion and the power storage elements, and the shield wall portion shields noise generated by the circuit portion. The electricity storage unit may further have an electrically conductive heat dissipation member that dissipates heat from the circuit portion.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: May 14, 2019
    Assignees: AutoNetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventors: Tatsuya Sumida, Kyohei Morita, Kazuhide Kitagawa, Hisao Hattori
  • Patent number: 10163773
    Abstract: An electronics package includes an interconnect assembly comprising a first insulating substrate, a first wiring layer formed on a lower surface of the first insulating substrate, and at least one through hole extending through the first insulating substrate and the first wiring layer. The electronics package also includes an electrical component assembly comprising an electrical component having an active surface coupled to an upper surface of the first insulating substrate opposite the lower surface. The active surface of the electrical comprises at least one metallic contact pad. At least one conductive stud is coupled to the at least one metallic contact pad and is positioned within the at least one through hole. A conductive plug contacts the first wiring layer and extends into the at least one through hole to at least partially surround the at least one conductive stud.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: December 25, 2018
    Assignee: General Electric Company
    Inventors: Christopher James Kapusta, Kaustubh Ravindra Nagarkar, Arun Virupaksha Gowda, James Wilson Rose
  • Patent number: 10154590
    Abstract: Provided are a circuit assembly in which it is possible to eliminate or reduce a level difference between a mounting surface of a substrate and portions to which terminals that are electrically connected to a conductive member are connected, and that can be easily produced, and a method for manufacturing the same. A circuit assembly includes a substrate provided with openings and an electronic component mounted on one side of the substrate, a conductive member that is a plate-shaped member fixed to another side of the substrate, the conductive member constituting a conductive path, and a relay member that is fixed to a surface on the substrate side of the conductive member and made of an electrically conductive material, the relay member being accommodated in the openings formed in the substrate, at least one terminal of the electronic component being connected to the relay member.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: December 11, 2018
    Assignees: AutoNetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventors: Tou Chin, Yu Muronoi
  • Patent number: 10096436
    Abstract: A method for manufacturing a trip unit that connects to a circuit breaker. The method includes mounting an assembly formed by a shaft and a trip member in a first case, mounting a detecting member in a second case, and assembling the first case and the second case, a contact end cooperating mechanically with the trip member such that the trip member trips the circuit breaker in the assembled configuration of the trip unit when the corresponding detecting member detects an electric fault.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: October 9, 2018
    Assignee: SCHNEIDER ELECTRIC INDUSTRIES SAS
    Inventor: Mickael Bertrand
  • Patent number: 9847323
    Abstract: In an example, an IC package includes a package substrate including a plurality of bumps configured for coupling to a printed circuit board, the package substrate including a core disposed between a plurality of top-side conductive layers and a plurality of bottom-side conductive layers. The IC package further includes an IC die coupled to the package substrate and disposed on top of the plurality of top-side conductive layers. The IC die further includes a voltage regulator IC die disposed on the package substrate adjacent to the IC die, the voltage regulator IC die being coupled to the IC die using two of four top-most layers of the plurality of top-side conductive layers nearest the IC die.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: December 19, 2017
    Assignee: XILINX, INC.
    Inventor: Austin H. Lesea
  • Patent number: 9805872
    Abstract: An improved module is provided. The module comprises a multiplicity of electronic components wherein each electronic component comprises a first external termination with at least one first longitudinal edge and a second external termination with at least one second longitudinal edge. A first lead is connected to the first longitudinal edge by a first interconnect and a second lead is connected to the second longitudinal edge by a second interconnect.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: October 31, 2017
    Assignee: KEMET Electronics Corporation
    Inventors: Galen W. Miller, John E. McConnell, John Bultitude, Garry L. Renner
  • Patent number: 9510412
    Abstract: The invention relates to a lighting system comprising: —a substrate comprising a resistive sheet (RS) comprising multiple electrodes (A, B, C, D), each electrode being suitable for connection to a respective voltage source, —a plurality of lighting elements (LEI, LE2, LE3, LE4), each element comprising a light source (LED) and at least two contact pins (CP1, CP2) for electrical connection to respective electrical connection terminals and a control circuit for controlling the light output and/or the color of the light generated by the light source in dependence on the voltage between the contact pins, wherein the electrical connection terminals are distributed over the resistive sheet such that the lighting elements can be connected in different positions and in different orientations, wherein the voltage present between the contact pins depends on the position and orientation of the lighting element and wherein the light output and/or the color of the light generated by the lighting element depends on the mag
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: November 29, 2016
    Assignee: KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventor: Harald Josef Günther Radermacher
  • Patent number: 9407166
    Abstract: An inverter device includes; a switching element; a plurality of flyback diodes each connected in parallel with the switching element; a first conductor plate connected to anode terminals of the flyback diodes and to one side of the switching element; and a second conductor plate connected to cathode terminals of the flyback diodes and to the other side of the switching element. Each of the flyback diodes is formed in a polygonal shape, and the two flyback diodes in each pair of the flyback diodes that are arranged in mutually adjacent positions are arranged so that a vertex of one opposes a vertex of the other.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: August 2, 2016
    Assignee: Hitachi, Ltd.
    Inventors: Masami Ohnishi, Takeshi Tokuyama
  • Patent number: 9379052
    Abstract: An electronic assembly for use in a downhole module may include a multilayer ceramic assembly and an electronic component disposed on the multilayer ceramic assembly. The multilayer ceramic assembly includes a ceramic substrate, a nickel plating layer disposed on the ceramic substrate and a gold plating layer having a thickness of less than about 0.5 microns disposed on the nickel plating layer. A wirebond such as an aluminum wirebond extends between the electronic component and the gold plating layer.
    Type: Grant
    Filed: November 1, 2012
    Date of Patent: June 28, 2016
    Assignee: SCHLUMBERGER TECHNOLOGY CORPORATION
    Inventors: Francois Barbara, Lahcen Garando
  • Patent number: 9318423
    Abstract: There is provided a leadless package type power semiconductor module. According to an exemplary embodiment of the present disclosure, the leadless package type power semiconductor module includes: connection terminals of a surface mounting type (SMT) formed at edges at which respective sides of four surfaces meet each other; a first mounting area connected to the connection terminals through a bridge to be disposed at a central portion thereof and mounted with power devices or control ICs electrically connected to the power devices to control the power devices; and second mounting areas formed between the connection terminals and mounted with the power devices or the control ICs, wherein the first mounting area is disposed at a different height from the second mounting area through the bridge to generate a phase difference from the second mounting area.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: April 19, 2016
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Kwang Soo Kim, Kee Ju Um, Suk Ho Lee, Joon Seok Chae
  • Patent number: 9275930
    Abstract: In a hybrid integrated circuit device of the present invention, leads are fixedly attached on the upper surface of a circuit board. The lead includes an island portion, a slope portion, and a lead portion. A transistor and a diode are mounted on the upper surface of the island portion. Electrodes provided on the upper surfaces of the transistor and the diode are connected to a bonding portion through a fine metal wire. The bonding portion of the lead is disposed at a higher position than the island portion. Thus, the fine metal wires connected to the bonding portion are separated from each other.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: March 1, 2016
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Shigeki Mashimo, Fumio Horiuchi, Kiyoaki Kudo, Akira Sakurai, Yuhki Inagaki
  • Patent number: 9227835
    Abstract: In an example, an interposer chip is provided. The interposer chip includes a base portion and a chip mounting portion. The interposer chip also includes one or more flexures connecting the base portion to the chip mounting portion. Additionally, a first plurality of projections extends from the base portion towards the chip mounting portion, and a second plurality of projections extends from the chip mounting portion towards the base portion and extending into interstices formed by first plurality of projections.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: January 5, 2016
    Assignee: Honeywell International Inc.
    Inventors: Robert D. Horning, Ryan Supino
  • Patent number: 9219026
    Abstract: A semiconductor device has an island portion on which a semiconductor chip is adhered through intermediation of an insulating paste. Recessed portions having an inverted pyramid shape are formed in a semiconductor chip placing region of the island portion. A first opening angle formed by a normal extending upward from a vertex of each of the plurality of recessed portions each having an inverted pyramid shape and an opening line extending to an outer side of the semiconductor chip placing region is smaller than a second opening angle formed by the normal and an opening line extending to an inner side of the semiconductor chip placing region.
    Type: Grant
    Filed: September 15, 2014
    Date of Patent: December 22, 2015
    Assignee: SEIKO INSTRUMENTS INC.
    Inventor: Koji Tsukagoshi
  • Patent number: 9159695
    Abstract: A package structure includes a chip attached to a substrate. The chip includes a bump structure including a conductive pillar having a length (L) measured along a long axis of the conductive pillar and a width (W) measured along a short axis of the conductive pillar. The substrate includes a pad region and a mask layer overlying the pad region, wherein the mask layer has an opening exposing a portion of the pad region. The chip is attached to the substrate to form an interconnection between the conductive pillar and the pad region. The opening has a first dimension (d1) measured along the long axis and a second dimension (d2) measured along the short axis. In an embodiment, L is greater than d1, and W is less than d2.
    Type: Grant
    Filed: January 7, 2013
    Date of Patent: October 13, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yao-Chun Chuang, Chita Chuang, Ming Hung Tseng, Chen-Shien Chen
  • Publication number: 20150124422
    Abstract: There are provided an electronic device mounting board and an electronic apparatus that can be made lower in profile. An electronic device mounting board includes an insulating substrate having an opening in which an electronic device is disposed so as to lie over the opening as seen in a transparent plan view, and a reinforcement portion disposed on a surface or in an interior of the insulating substrate so as to lie around the opening of the insulating substrate as seen in a transparent plan view.
    Type: Application
    Filed: May 31, 2013
    Publication date: May 7, 2015
    Applicant: KYOCERA Corporation
    Inventors: Akihiko Funahashi, Masatsugu Iiyama, Kanae Horiuchi, Yousuke Moriyama
  • Publication number: 20150116969
    Abstract: An electronic device of the present invention includes an insulating base substrate in which a plurality of through electrodes are formed; an electronic element which is electrically connected to the through electrodes and is mounted on one surface of the base substrate; a lid which accommodates the electronic element and is bonded to the one surface of the base substrate; and an external electrode which covers a region ranging from an end face of the through electrode, which is exposed by the other surface of the base substrate, to the other surface in a vicinity of the end face. The external electrode includes a conductive film which covers a region ranging from the end face to the other surface in the vicinity of the end face, a first electrolytic plating film which is formed on a surface of the conductive film by an electrolytic plating method, and a second electrolytic plating film which is formed on a surface of the first electrolytic plating film by an electrolytic plating method.
    Type: Application
    Filed: October 21, 2014
    Publication date: April 30, 2015
    Inventors: Atsushi KOZUKI, Hideshi HAMADA, Yoshifumi YOSHIDA
  • Publication number: 20150109749
    Abstract: A circuit board assembly includes a printed circuit board, at least one wire, at least one wire fixing device, and a plurality of electronic components. A wire fixing method includes following steps. Firstly, the wire fixing device is inserted into a conductive hole of the printed circuit board. Then, the wire fixing device is fixed on the printed circuit board via a soldering material. Then, a conducting terminal of the wire is introduced into an accommodation space of the wire fixing device through the first opening of the wire fixing device. Then, at least one concave structure is formed in an external surface of a first conducting part of the wire fixing device by a jig. Consequently, the conducting terminal of the wire is fixed on the wire fixing device, and the wire is electrically connected with the printed circuit board through the wire fixing device.
    Type: Application
    Filed: April 2, 2014
    Publication date: April 23, 2015
    Applicant: DELTA ELECTRONICS, INC.
    Inventors: Ching-Ho Chou, Do Chen, Shang-Yu Li, Chun-Jen Chung
  • Patent number: 9004950
    Abstract: A card device for insertion into and ejection from a host device. The card device includes a first electrode array including first electrodes linearly aligned in a second direction along the leading edge, and a second electrode array including second electrodes aligned in the second direction between the first electrode array and the trailing edge. A first concave region includes electrodes from the first and second electrode array. A second concave region, adjacent to the first concave region, includes a first region, which is adjacent to the first electrodes in the first concave region, and a second region, which is adjacent to the second electrodes in the first concave region. At least one of the first electrodes is situated in the first region of the second concave region, and no electrodes are situated in the second region of the second concave region.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: April 14, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventor: Yutaka Nakamura
  • Patent number: 9001522
    Abstract: Electronic devices may be provided with printed circuits to which integrated circuits and other electrical components may be mounted. A first printed circuit may have a first surface with an array of contact pads arranged in rows and columns. Each column of contact pads may have a series of contact pads separated by gaps. The contact pads in each column may be staggered with respect to the contact pads in adjacent columns such that each contact pad in a given column is horizontally adjacent to associated gaps in the adjacent columns. A component may be mounted to an opposing surface of the printed circuit such that it overlaps one of the gaps between the staggered contact pads. By mounting the component to portions of the first printed circuit that do not overlap the staggered contact pads, the risk of damaging the electrical component during solder reflow operations may be minimized.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: April 7, 2015
    Assignee: Apple Inc.
    Inventors: Wyeman Chen, Michael Nikkhoo, Amir Salehi
  • Patent number: 9000303
    Abstract: The invention provides a method for preparing a pattern for an electric circuit comprising the steps of: (a) providing a substrate; (b) providing a pattern of an inhibiting material for an electrical circuit onto said substrate by i) applying a layer of the inhibiting material onto said substrate and mechanically removing locally the layer of the inhibiting material to obtain said pattern; or ii) applying a layer of the inhibiting material onto said substrate, wherein said layer has pre-determined pattern which incompletely covers said substrate; (c) establishing a distribution of particles of a first metal or alloy thereof on the layer of the inhibiting material and the pattern as obtained in step.
    Type: Grant
    Filed: June 16, 2008
    Date of Patent: April 7, 2015
    Assignee: Nederlandse Organisatie voor toegepast-natuurwetenschappelijk onderzoek TNO
    Inventors: Roland Anthony Tacken, Renatus Marius De Zwart, Erwin Rinaldo Meinders, Maria Peter
  • Publication number: 20150092377
    Abstract: Embodiments of methods for forming microelectronic device packages include forming a trench on a surface of a package body between exposed ends of first and second device-to-edge conductors, and forming a package surface conductor in the trench to electrically couple the first and second device-to-edge conductors. In one embodiment, the package surface conductor is formed by first forming a conductive material layer over the package surface, where the conductive material layer substantially fills the trench, and subsequently removing portions of the conductive material layer from the package surface adjacent to the trench. In another embodiment, the package surface conductor is formed by dispensing one or more conductive materials in the trench between the first and second exposed ends (e.g., using a technique such as spraying, inkjet printing, aerosol jet printing, stencil printing, or needle dispense). Excess conductive material may then be removed from the package surface adjacent to the trench.
    Type: Application
    Filed: September 30, 2013
    Publication date: April 2, 2015
    Inventors: JASON R. WRIGHT, Michael B. Vincent, Weng F. Yap
  • Patent number: 8987875
    Abstract: An assembly for packaging one or more electronic devices in die form. The assembly includes substrates on opposite sides of the assembly, with lead frames between the electronic devices and the substrates. The substrates, lead frames, and electronic devices are sintered together using silver-based sintering paste between each layer. The material and thicknesses of the substrates and lead frames are selected so stress experienced by the electronic devices caused by changes in temperature of the assembly are balanced from the center of the assembly, thereby eliminating the need for balancing stresses at a substrate level by applying substantially matching metal layers to both sides of the substrates.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: March 24, 2015
    Assignee: Delphi Technologies, Inc.
    Inventors: Carl W. Berlin, Gary L. Eesley
  • Publication number: 20150080050
    Abstract: A composite module includes outer ground electrodes on one main surface of a wiring substrate, a wiring electrode inside the wiring substrate, and a first ground electrode between the wiring electrode and the outer ground electrode. A cutout is provided in the first ground electrode at least at a portion of a region overlapping with the wiring electrode and the outer ground electrode when viewed from above, and the wiring electrode overlaps with at least one of the first ground electrode and the outer ground electrode when viewed from above to reduce stray capacitance produced on the wiring electrode and to adjust impedance of the wiring electrode while preventing signals leaked from the exterior from interfering with the wiring electrode.
    Type: Application
    Filed: November 24, 2014
    Publication date: March 19, 2015
    Inventor: Hiromichi KITAJIMA
  • Patent number: 8976538
    Abstract: Disclosed herein is a printed circuit board, including a base substrate; and a circuit pattern formed on the base substrate and including a first metal layer having an inclined surface on both upper sides thereof and a second metal layer formed on the inclined part.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: March 10, 2015
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Min Sung Kim
  • Publication number: 20150049449
    Abstract: A display device includes: a substrate; electrode terminals for external connection; an insulating film on the respective electrode terminals, the insulating film provided with openings which expose part of the respective electrode terminals, the insulating film covering the other portion of the respective electrode terminals; surface conductive films which are disposed so as to correspond to the respective openings, and are connected to part of the respective electrode terminals; and a circuit board disposed so as to oppose the substrate, the circuit board including circuit electrode terminals which are connected to the surface conductive films through a conductive bonding member so as to oppose the respective openings, the surface conductive films extending from an inside of an opening corresponding thereto to a surface of an insulating film corresponding thereto, peripheral edges of the respective surface conductive films being positioned beyond a peripheral edge of a circuit electrode terminal correspondi
    Type: Application
    Filed: September 27, 2012
    Publication date: February 19, 2015
    Applicant: KYOCERA CORPORATION
    Inventors: Minoru Shibano, Ryoichi Yokoyama
  • Publication number: 20150043181
    Abstract: The present disclosure is directed to a microelectronic assembly that includes first and second microelectronic elements, signal leads, one or more jumper leads, and a dielectric element that has first and second apertures. The signal leads may be connected to one or more of the microelectronic elements and extend through the one or more of the first or second apertures to conductive elements on the dielectric element. The jumper leads may extend through the first aperture and be connected to a contact of the first microelectronic element. The one or more jumper leads may span over the second aperture and be connected to a conductive element on the dielectric element.
    Type: Application
    Filed: October 24, 2014
    Publication date: February 12, 2015
    Inventors: Belgacem Haba, Wael Zohni, Richard Dewitt Crisp
  • Patent number: 8947887
    Abstract: A package assembly comprises an electronic device; a package body; at least a first plurality of leads having a first geometrical shape and a second plurality of leads having a second geometrical shape, protruding from the package body; each of the first plurality of leads being located in corners of the package body; or the first and the second plurality of leads arranged in at least a first row and a second row located in parallel to the first row; each of the rows comprising at least two leads; the first row being transformable into the second row by mirroring the first row along a symmetry plane of the package body; each of the first plurality of leads having the first geometrical shape different from the second geometrical shape.
    Type: Grant
    Filed: February 23, 2009
    Date of Patent: February 3, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Robert Bauer, Thorsten Hauck
  • Patent number: 8947886
    Abstract: An electronic component includes an electrically conductive carrier. The electrically conductive carrier includes a carrier surface and a semiconductor chip includes a chip surface. One or both of the carrier surface and the chip surface include a non-planar structure. The chip is attached to the carrier with the chip surface facing towards the carrier surface so that a gap is provided between the chip surface and the carrier surface due to the non-planar structure of one or both of the carrier surface and the first chip surface. The electronic component further includes a first galvanically deposited metallic layer situated in the gap.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: February 3, 2015
    Assignee: Infineon Technologies AG
    Inventors: Joachim Mahler, Manfred Mengel, Khalil Hosseini, Klaus Schmidt, Franz-Peter Kalz
  • Publication number: 20150022988
    Abstract: To provide a lid body portion with an improved mounting ratio of an electronic device component, an electronic device package and an electronic device including the same. There is provided a lid body portion including a concave portion in which a space portion is formed by a bottom portion and a side plate portion and a flange portion extending from an outer edge portion in an opening portion of the concave portion to the outside, in which a side-plate inner surface as a surface facing the space portion of the concave portion in the side plate portion inclines to the outside of the space portion.
    Type: Application
    Filed: July 15, 2014
    Publication date: January 22, 2015
    Inventors: Masayuki SATOH, Kenji TAKANO, Mitsuo AKIBA, Hitoshi TAKEUCHI, Shuhei KANEKO
  • Publication number: 20150016081
    Abstract: An electronic device may include a substrate, and an integrated circuit over the substrate. The substrate may be provided with an electrical connection network including electrical links for linking the integrated circuit to another electrical device. Some of the electrical links may include an impedance-compensating inductor.
    Type: Application
    Filed: July 14, 2014
    Publication date: January 15, 2015
    Inventors: David Auchere, Laurent Marechal
  • Patent number: 8928049
    Abstract: A module (1) includes a first functional device (2) and a second functional device (3). The first functional device (2) includes a base electrode, an emitter electrode and a collector electrode. The second functional device (3) includes at least one electrode. The module (1) further includes a conductive frame (4). One of the base electrode, the emitter electrode, and the collector electrode of the first functional device (2) is directly connected to the frame (4). The electrode of the second functional device (3) is also directly connected to the frame (4). The frame (4) includes a portion serving as a terminal for external connection.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: January 6, 2015
    Assignee: Rohm Co., Ltd.
    Inventor: Kenichi Yoshimochi
  • Patent number: 8929086
    Abstract: A MCM system board uses a stiffener arrangement to enhance mechanical, thermo and electrical properties by incorporating an LGA compression connector in a computer system. The present designs of large scale computing systems (LSCS) in IBM use a MCM that is attached to a system board and held together by a stiffening frame. Due to the nature of the manufacturing of the system board, there can be significant gaps formed in the mounting area of the MCM between the board and the stiffener. A method is described that not only fills the void, it also, in addition promotes thermo conduction of excess heat away from the MCM and at the same time promotes enhanced electrical properties of the LGA connections of the MCM to the system board.
    Type: Grant
    Filed: September 26, 2005
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Michael F. McAllister, Harald Pross, Gerhard H. Ruehle, Wolfgang A. Scholz, Gerhard Schoor
  • Patent number: 8923007
    Abstract: In at least one embodiment, a circuit board assembly that includes a printed circuit board is provided. The printed circuit board includes a top surface and a bottom surface for supporting at least one through-hole electrical component. The printed circuit board defines at least one component hole extending from the top surface to the bottom surface for receiving the at least one through-hole electrical component. The at least one component hole includes a first section having a first diameter and a second section having a second diameter. The first diameter is different from the second diameter. Each of the first and the second sections are configured to receive solder paste for forming a solder joint with the at least one through-hole electrical component.
    Type: Grant
    Filed: October 2, 2008
    Date of Patent: December 30, 2014
    Assignee: Oracle America, Inc.
    Inventors: Michael Francis Sweeney, Jorge Eduardo Martinez-Vargas, Jr., Michael Clifford Freda
  • Patent number: 8923003
    Abstract: An electronic device may contain components such as flexible printed circuits and rigid printed circuits. Electrical contact pads on a flexible printed circuit may be coupled electrical contact pads on a rigid printed circuit using a coupling member. The coupling member may be configured to electrically couple contact pads on a top surface of the flexible circuit to contact pads on a top surface of the rigid circuit. The coupling member may be configured to bear against a top surface of the flexible circuit so that pads on a bottom surface of the flexible circuit rest against pads on a top surface of the rigid circuit. The coupling member may bear against the top surface of the flexible circuit. The coupling member may include protrusions that extend into openings in the rigid printed circuit. The protrusions may be engaged with engagement members in the openings.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: December 30, 2014
    Assignee: Apple Inc.
    Inventors: Alexander D. Schlaupitz, Joshua G. Wurzel
  • Patent number: 8917521
    Abstract: A semiconductor package, a substrate and a manufacturing method thereof are provided. The substrate comprises a conductive carrier, a first metal layer and a second metal layer. The first metal layer is formed on the conductive carrier and comprises an lead pad having an upper surface. The second metal layer is formed on the first metal layer and comprises a bond pad. The bond pad overlaps and is in contact with the upper surface of the first metal layer. The upper surface of the lead pad is partially exposed. A part of the bond pad overhang outward from the edge of the lead pad.
    Type: Grant
    Filed: April 28, 2011
    Date of Patent: December 23, 2014
    Assignee: Advanpack Solutions Pte Ltd.
    Inventors: Hwee-Seng Jimmy Chew, Shoa-Siong Lim, Kian-Hock Lim
  • Patent number: 8908387
    Abstract: A wiring board includes a substrate having an opening portion, electronic components positioned in the opening portion of the substrate and including first and second electronic components, and an insulation layer formed over the substrate and the first and second components. The first component has first and second electrodes having side portions on side surfaces of the first component, the second component has first and second electrodes having side portions on side surfaces of the second component, the first electrode of the first component and the first electrode of the second component are set to have substantially the same electric potential, and the first component and the second component are positioned in the opening portion of the substrate such that the side portion of the first electrode of the first component is beside the side portion of the first electrode of the second component.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: December 9, 2014
    Assignee: Ibiden Co., Ltd.
    Inventors: Yukinobu Mikado, Shunsuke Sakai, Takashi Kariya, Toshiki Furutani
  • Patent number: 8908383
    Abstract: Embodiments of the present disclosure describe apparatuses, methods, and systems of thermal via structures with surface features. In some embodiments the surface features may have dimensions greater than approximately one micron. The thermal via structures may be incorporated into a substrate of an integrated circuit device. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: May 21, 2012
    Date of Patent: December 9, 2014
    Assignee: TriQuint Semiconductor, Inc.
    Inventors: Tarak A. Railkar, Paul D. Bantz
  • Publication number: 20140355224
    Abstract: A plastic panel forming part of a motor vehicle is disclosed having a number of embedded conductors for electrically connecting together an electrical connector and an electrical unit. Parts of the electrical connector and the electrical unit are formed as integral parts of the plastic panel. The electrical connector includes terminals connected to the electrical conductors for co-operation with terminals formed as part of a plug used to connect the conductors to other electrical circuits of the motor vehicle. In one embodiment the electrical unit is in the form of a fuse box having electrical terminals held in position by the plastic panel and in pairs for cooperation with a respective fuse.
    Type: Application
    Filed: June 2, 2014
    Publication date: December 4, 2014
    Applicant: Ford Global Technologies, LLC
    Inventor: Ian SALSBURY
  • Patent number: 8902605
    Abstract: A surface mount component adapter, assembly and related method for attaching a surface mount component to a printed circuit board. The surface mount component adapter includes a substrate, a surface mount component holder on the substrate, and flexible leads each having a base end attached to the surface mount component holder and a free end configured to engage a plated through hole on a circuit board. The surface mount component holder is configured to engage electrical contacts of a surface mount component. The surface mount component assembly combines the surface mount adapter with the surface mount component. In the surface mount component method, the surface mount assembly is formed and the free ends of the flexible leads are attached to a corresponding number of the plated through holes on the circuit board.
    Type: Grant
    Filed: June 13, 2012
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Daniel J. Buschel, Wai Mon Ma, James E. Tersigni, Raymond D. Birchall
  • Patent number: 8897029
    Abstract: An isolated switching power converter includes a power isolation transformer having at least one primary winding, at least one secondary winding and a plurality of sides, a first power board mechanically coupled to a first side of the transformer, and a second power board mechanically coupled to a second side of the transformer. The first power board includes a primary side circuit electrically coupled to the at least one primary winding, and the second power board includes a secondary side circuit electrically coupled to the at least one secondary winding.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: November 25, 2014
    Assignee: Astec International Limited
    Inventors: Robert H. Kippley, Bradley J. Schumacher, Gary P. Magnuson, Kwong K. Chin
  • Patent number: 8873244
    Abstract: A package structure includes a base body having a first encapsulant and a wiring layer embedded in and exposed from the first encapsulant. The wiring layer has a plurality of conductive traces and a plurality of first electrical contact pads. The first encapsulant has openings for exposing the first electrical contact pads, a chip electrically connected to the wiring layer, and a second encapsulant formed on the base body for covering the chip and the wiring layer, thereby providing an even surface for preventing the encapsulant from cracking when the chip is mounted.
    Type: Grant
    Filed: April 13, 2010
    Date of Patent: October 28, 2014
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Pang-Chun Lin, Hsiao-Jen Hung, Chun-Yuan Li, Chien-Ping Huang, Chun-Chi Ke
  • Patent number: 8869387
    Abstract: Microelectronic packages with leadframes, including leadframes configured for stacked die packages, and associated systems and methods are disclosed. A system in accordance with one embodiment includes a support member having first package bond sites electrically coupled to leadframe bond sites. A microelectronic die can be carried by the support member and electrically coupled to the first packaged bond sites. A leadframe can be attached to the leadframe bond sites so as to extend adjacent to the microelectronic die, with the die positioned between the leadframe and the support member. The leadframe can include second package bond sites facing away from the first package bond sites. An encapsulant can at least partially surround the leadframe and the microelectronic die, with the first and second package bond sites accessible from outside the encapsulant.
    Type: Grant
    Filed: March 17, 2010
    Date of Patent: October 28, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Chin Hui Chong, Choon Kuan Lee, David J. Corisis
  • Publication number: 20140312765
    Abstract: A flat panel display apparatus includes a substrate; a display unit disposed on the substrate; a sealing substrate disposed to face the display unit; a sealing member disposed between the substrate and the sealing substrate to surround the display unit; a wiring unit disposed between the substrate and the sealing substrate, including a region that overlaps the sealing member, and including a plurality of wiring members that are spaced apart from each other in at least a portion of the region that overlaps the sealing member; and a lead-in unit connected to the wiring unit to apply a voltage to the wiring unit, and formed to be electrically connectable to an external power source.
    Type: Application
    Filed: March 11, 2014
    Publication date: October 23, 2014
    Applicants: ENSIL TECH CO., LTD., SAMSUNG DISPLAY CO., LTD.
    Inventors: Oh-Seob KWON, Sung-Soo KOH, Jae-Sang RO, Seog-Young LEE, Won-Eui HONG
  • Patent number: 8867228
    Abstract: An electrode bonding structure sealed with a sealing resin, in which a flexible substrate is bonded to a first substrate via an adhesive, wherein: a region along a bottom face edge of an flexible substrate end part is bonded, via the adhesive, to an inner side region of a region along a top face edge of an first substrate end part; a gap is formed between an inner side region of the region along the bottom face edge of the flexible substrate end part and the region along the top face edge of the first substrate end part; the sealing resin is formed so as to enter, while covering a top face of the flexible substrate end part, at least a portion of the gap; and a height of the gap gets smaller towards the adhesive from the top face edge of the first substrate end part.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: October 21, 2014
    Assignee: Panasonic Corporation
    Inventors: Hiroaki Katsura, Koso Matsuno, Yoji Ueda
  • Publication number: 20140307406
    Abstract: A module includes a multilayer body including laminated ceramic green sheets that have been fired, multiple mounting terminals arranged to mount a component thereon, the mounting terminals each including an end surface that is exposed at a main surface of the multilayer body, and multiple via conductors disposed inside the multilayer body so as to correspond to the mounting terminals at positions overlapped by the corresponding mounting terminals when viewed in a plan view. The lengths of the via conductors are adjusted so that predetermined points on the mounting terminals are positioned on the same plane.
    Type: Application
    Filed: April 7, 2014
    Publication date: October 16, 2014
    Applicant: Murata Manufacturing Co., Ltd.
    Inventor: Hiromichi KITAJIMA
  • Publication number: 20140268577
    Abstract: This disclosure relates generally to a chip package assembly arranged to be electrically coupled to a circuit board including a plurality of circuit board contacts. The chip package assembly may include a chip package including a first side and a second side, the second side including a first plurality of contacts arranged to be electrically coupled to the plurality of circuit board contacts and a second plurality of contacts arranged to be electrically coupled to a remote device via a connector assembly.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Inventors: Rajasekaran Raja Swaminathan, Donald T. Tran, Brent S. Stone, Ram Viswanath
  • Publication number: 20140268610
    Abstract: A method for forming vias in a multilayered printed circuit board is disclosed, which includes providing a multilayered printed circuit board having at least two or more layers; placing a donut pad on an upper layer of at least one layer of the multilayered printed circuit board for forming a via through one or more of the layers of the multilayered printed circuit board, the donut pad having a clearance of less than approximately 80 to 90 percent of a diameter of the via; and forming at least one via through the donut pad and at least one or more layers of the multilayered printed circuit board.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Inventor: Gregory HALVORSON
  • Publication number: 20140254120
    Abstract: Provided is a device packaging structure including: an interposer substrate including a substrate, and a plurality of through-hole interconnections formed inside a plurality of through-holes passing through the substrate from a first main surface toward a second main surface, the first main surface being one main surface of the substrate, the second main surface being the other main surface thereof; a first device which includes a plurality of electrodes and is arranged so that these electrodes face the first main surface; and a second device which includes a plurality of electrodes of which an arrangement is different from an arrangement of each of the electrodes of the first device, and is arranged so that these electrodes face the second main surface.
    Type: Application
    Filed: May 20, 2014
    Publication date: September 11, 2014
    Applicant: FUJIKURA LTD.
    Inventors: Satoshi YAMAMOTO, Hiroyuki HIRANO, Takanao SUZUKI
  • Publication number: 20140247574
    Abstract: A printed circuit board includes a printed circuit board, a semiconductor device mounted on the printed circuit board, a capacitor element mounted on the printed circuit board 2, a ground conductor plane to which a ground terminal of the semiconductor device is connected, and first and second power source conductor planes which are arranged so as not to contact with each other. The second power source conductor plane and the ground conductor plane are arranged so as to oppose to each other to form a planar capacitor. The printed circuit board has a first connecting conductor which connects a power source terminal of the semiconductor device with the second power source conductor plane, and a second connecting conductor which connects the first power source conductor plane with the second power source conductor plane through a first terminal of the capacitor element. Thereby, an electromagnetic radiation noise is reduced.
    Type: Application
    Filed: December 6, 2012
    Publication date: September 4, 2014
    Applicant: Canon Kabushiki Kaisha
    Inventor: Hiroto Tamaki
  • Publication number: 20140240941
    Abstract: A main body of an electronic part has multiple electrodes, to which multiple terminals are connected. The terminals include a normal terminal and a fuse terminal, each of which extends from lands formed in a printed board so as to hold the main body at a position above and separated from a board surface of the printed board. The fuse terminal has a cut-off portion having a smaller width than other portions of the fuse terminal, so that the cut-off portion is melted down when excess current flows in the fuse terminal. The normal terminal holds the main body at the position above and separated from the board surface even in a case of melt-down of the cut-off portion.
    Type: Application
    Filed: February 26, 2014
    Publication date: August 28, 2014
    Applicants: Murata Manufacturing Co., Ltd., DENSO CORPORATION
    Inventors: Yuki MIKAMI, Toru ITABASHI, Ryoichi SHIRAISHI, Shigeki NISHIYAMA