Busbar Patents (Class 361/775)
  • Patent number: 5719748
    Abstract: A semiconductor package including a base having a chip receiving portion and a surrounding portion; a bridge having conductive strips extending over the chip and supported at the surrounding portion; wires connect the conductive strips to power and ground; and wires connect the conductive strips to chip area power and ground bonding pads. Decoupling capacitors may be mounted on the base.
    Type: Grant
    Filed: June 28, 1995
    Date of Patent: February 17, 1998
    Assignee: Honeywell Inc.
    Inventors: Deborah A. Cullinan, Thomas J. Dunaway, Richard K. Spielberger
  • Patent number: 5694301
    Abstract: A hybrid vehicle includes a power unit communicating power between a turbine alternator, flywheel and traction motor. The power unit stores, dc power in capacitors and places power on a dc bus for use in driving the induction machines. The dc bus includes two spaced buses, each of the bus members include a positive plate and a negative plate electrically insulated from one another. A conducting strap member interconnects the first and second bus members. The conducting strap member includes first and second strap plates electrically insulated from one another and secured to one another. A first of the strap plates is connected to the positive plates and a second of the strap plates is connected to the negative plates. Also included is a capacitor bank for storing DC power. The capacitor bank is connected to the DC bus by laminated brackets carrying positive and negative signals.
    Type: Grant
    Filed: May 2, 1996
    Date of Patent: December 2, 1997
    Assignee: Chrysler Corporation
    Inventors: Kevin J. Donegan, Dennis E. Hartzell, Gary P. Millas
  • Patent number: 5655290
    Abstract: A three dimensional module for housing a plurality of integrated circuit chips is shown. The IC chips are mounted in rows on a plurality of substrates. Parallel to each row are communications bars which provide signal paths allowing chips on one substrate to communicate with those on another substrate. The communications bars also serve as spacers between substrates, thereby forming cooling channels. The IC chips are disposed in the cooling channels so that they come into direct contact with the cooling fluid. Signal lines to and from the IC chips are kept as separated as possible from the power lines so as to minimize noise. To this end, relatively thick power supply straps are mounted to each substrate below each row of IC chips. The power supply straps are, in turn, connected to power feed straps such that a very low impedance power supply path to the IC chips is maintained.
    Type: Grant
    Filed: January 30, 1995
    Date of Patent: August 12, 1997
    Assignee: Fujitsu Limited
    Inventors: Larry L. Moresco, David A. Horine, Wen-Chou Vincent Wang
  • Patent number: 5648892
    Abstract: A multilayer circuit board system or laminated circuit board system for use in a motor controller includes a motherboard, at least one power substrate circuit board, and a capacitor circuit board. The power substrate module includes a mounting area provided in a recess, window or portion of the circuit board where the circuit board is only a single layer thick. The single circuit board layer at the mounting area provides a heat conductive yet highly electrically insulated mounting area for receiving a heat sink. The heat sink can be mounted on a side opposite the electrical device. The capacitor circuit board, power substrate circuit board, and mother circuit board are interconnected without the use of external connectors or wires. A flexible circuit board layer or SCM.TM. interconnect interface allows the circuit boards to be connected solely by printed circuit (PC) wires.
    Type: Grant
    Filed: September 29, 1995
    Date of Patent: July 15, 1997
    Assignee: Allen-Bradley Company, Inc.
    Inventors: Christopher J. Wieloch, Thomas E. Babinski, John C. Mather, Gerard A. Woychik, Steven R. McLaughlin
  • Patent number: 5629840
    Abstract: Power bus bars are provided for a semiconductor die. Power bus bars are thick electrical conductors that extend the length of the die in an electrically isolated array of stripes. The electrical stripes are divided into two or more interdigitated groups, each group connected to a power supply, or connected to a ground supply. This arrangement of alternate power and ground stripes minimizes inductance and resistance, and brings power and ground close to every transistor in the semiconductor die with minimized voltage variations.
    Type: Grant
    Filed: March 28, 1994
    Date of Patent: May 13, 1997
    Assignee: Digital Equipment Corporation
    Inventors: William R. Hamburgen, John S. Fitch, Norman P. Jouppi
  • Patent number: 5625537
    Abstract: The invention concerns a carrier arrangement (10) comprising a longitudinal column-type carrier (15), whereby a coupling arrangement is provided to establish a mechanical and simultaneously electrical connection to a medical apparatus (40). The coupling arrangement comprises two guide rails (20, 30) which are electrically insulated against each other and extend along the entire length of the carrier (15).
    Type: Grant
    Filed: February 9, 1996
    Date of Patent: April 29, 1997
    Assignee: Fresenius AG
    Inventor: Klaus Neuder
  • Patent number: 5586009
    Abstract: The present invention is a rail-less bus system for a high density integrated circuit package, or module, made up of a plurality of vertically stacked high density integrated circuit devices. Each device has leads extending therefrom with bifurcated or trifurcated distal lead ends which electrically connect with lead ends of adjacent integrated circuit devices. The bus system provides a path for communication from the module to external electronic devices and internal communication between the individual integrated circuit devices in the module.
    Type: Grant
    Filed: April 9, 1996
    Date of Patent: December 17, 1996
    Assignee: Staktek Corporation
    Inventor: Carmen D. Burns
  • Patent number: 5541812
    Abstract: The present invention is a rail-less bus system for a high density integrated circuit package, or module, made up of a plurality of vertically stacked high density integrated circuit devices. Each device has leads extending therefrom with bifurcated or trifurcated distal lead ends which electrically connect with lead ends of adjacent integrated circuit devices. The bus system provides a path for communication from the module to external electronic devices and internal communication between the individual integrated circuit devices in the module.
    Type: Grant
    Filed: September 11, 1995
    Date of Patent: July 30, 1996
    Inventor: Carmen D. Burns
  • Patent number: 5535133
    Abstract: Within an integrated circuit chip, digital logic gates are intercoupled by signal lines called nets. If one net (called the "victim net") has several segments that respectively lie next to several other nets (called "aggressor nets"), then a certain amount of crosstalk voltage will be coupled into the victim net by each of the aggressor nets; and that can cause a malfunction. But with the preset invention, a process is provided whereby an integrated circuit chip is physically laid out and built such that the total crosstalk voltage which is coupled into the victim net by all of the aggressor nets is kept within an acceptable level. This process includes a repetitive cycle where during each cycle, a previously tried layout is modified, and the crosstalk which is coupled into the victim net in the modified layout is estimated by means of a table.
    Type: Grant
    Filed: February 9, 1995
    Date of Patent: July 9, 1996
    Assignee: Unisys Corporation
    Inventors: Richard J. Petschauer, Roland D. Rothenberger, Paul G. Tumms
  • Patent number: 5532907
    Abstract: A power bus is described that connects a matrix of power supplies to a circuit board in a computer system. The power bus is substantially planar and attached to the circuit board so that the power bus and circuit board are parallel to one another. This parallel relationship decreases the amount of space utilized by the circuit board in the computer system. The circuit board also has connectors for delivering power directly to a load which increases the efficiency of power delivery.
    Type: Grant
    Filed: November 2, 1993
    Date of Patent: July 2, 1996
    Assignee: International Business Machines Corporation
    Inventors: John A. Asselta, Albert L. Balan, Stephen Boyko, James E. Myers
  • Patent number: 5526225
    Abstract: A receptacle including a casing to hold a positive contact metal plate, a negative contact metal plate, which is connected to the negative terminal of power supply, and a ground plate, a T-shaped copper plate mounted inside the casing and connected to the positive terminal of power supply, a bimetal strip connected to the positive contact metal plate and disposed in contact with the T-shaped copper plate, an insulative member turned about a post inside the casing and supported on a spring, and a press button mounted on the outside of the casing, wherein when the press button is depressed, the bimetal strip is forced away from the T-shaped copper plate by the insulative member to cut off power supply; when the receptacle is electrically overloaded, the bimetal strip is heated to deform and to disconnect from the T-shaped copper plate to cut off power supply.
    Type: Grant
    Filed: June 29, 1995
    Date of Patent: June 11, 1996
    Inventor: Ming-Shan Wang
  • Patent number: 5517063
    Abstract: A power bridge assembly for providing electric current to stator windings of an electric motor used in an electric propulsion system for an electric vehicle. The power bridge is assembled on a laminated bus bar. An upper plate of the bus bar connects to one side of a high voltage battery, a lower plate of the bus bar connects to the other side of the high voltage battery, and an insulation layer is sandwiched between the upper and lower plates. Electrical switches and capacitors sandwich the laminated bus bar. With this structure, two fasteners, one for positive voltage and one for negative voltage, can connect the bus bar, capacitors, and switches both electrically and mechanically. The sandwich structure eliminates parasitic inductance from the electrical connections.
    Type: Grant
    Filed: June 10, 1994
    Date of Patent: May 14, 1996
    Assignee: Westinghouse Electric Corp.
    Inventors: David L. Schantz, Jr., James H. Deoms, Brian H. Smith
  • Patent number: 5502615
    Abstract: A meter module assembly includes a combination meter panel implemented with meters/indicating lamps and a drive circuit thereof, an electric junction box integrating functional circuits to distribute and control power sources and input/output signals for vehicle-mounted electric equipment including the meters/indicating lamps, and a switch unit integrating switches for vehicle-mounted electric equipment. The combination meter panel, the electric junction box, and the switch unit are integrally united. The electric junction box is integrally combined with the switch unit at the rear surface of the unit being arranged side by side with the combination meter panel. The electric junction box is electrically connected with the combination meter panel by a flexible circuit board.
    Type: Grant
    Filed: May 10, 1995
    Date of Patent: March 26, 1996
    Assignee: Yazaki Corporation
    Inventors: Minoru Kubota, Keizo Nishitani, Yoshiaki Nakayama
  • Patent number: 5502278
    Abstract: The invention relates to the encapsulation of integrated circuits, and more particularly encapsulation in a multi-layer ceramic case. In order to permit the disposition of chips of variable size on a monolithic chip (22, 24, 26) reception site (23, 25, 27) without the risk of having excessively long connection wires between the chip and the conductive regions (44) surrounding the reserved site, it is proposed according to the invention to cover the chip-reception site with a number of mutually insulated conductive contacts which can serve as soldering relays for these connection wires (80, 90, 100). If the chip is large (chip 24) it is bonded or soldered to these contacts; if it is small (chip 22) it is surrounded by relay-contacts.
    Type: Grant
    Filed: October 6, 1993
    Date of Patent: March 26, 1996
    Assignee: Thomson Composants Militaires et Spatiaux
    Inventors: Henri Mabboux, Michel Mermet-Guyennet
  • Patent number: 5495396
    Abstract: Collector clips arranged on a circuit breaker trip unit printed circuit board allow removable connection between the trip unit circuit and the circuit within a field-installable rating plug as well as other auxiliary electrical devices. The connector clips are oriented to the rating plug and the trip unit to prevent cold flow of the solder at the junction between the ends of the connector clips and the receiving holes formed within the trip unit circuit board.
    Type: Grant
    Filed: February 6, 1995
    Date of Patent: February 27, 1996
    Assignee: General Electric Company
    Inventors: Robin L. Mendick, Ira B. Goldman
  • Patent number: 5493476
    Abstract: The present invention is a rail-less bus system for a high density integrated circuit package, or module, made up of a plurality of vertically stacked high density integrated circuit devices. Each device has leads extending therefrom with bifurcated or trifurcated distal lead ends which electrically connect with lead ends of adjacent integrated circuit devices. The bus system provides a path for communication from the module to external electronic devices and internal communication between the individual integrated circuit devices in the module.
    Type: Grant
    Filed: May 22, 1995
    Date of Patent: February 20, 1996
    Assignee: Staktek Corporation
    Inventor: Carmen D. Burns
  • Patent number: 5475568
    Abstract: A power supply structure for a multichip package is provided to improve the transmission performance of signals. Cases are fitted onto one face of a ceramic substrate. On the other face are aligned substrates. On each of the substrates are erected I/O pins. The I/O pins are connected to signal pins of LSIs via the ceramic substrate's internal layer. On side faces of the substrates are provided power supply pads. To the power supply pads are connected the power supply pins of the LSIs via the ceramic substrate's internal layer. When power is to be supplied, electroconductive bars are inserted between the substrates. The electroconductive bars supply power to the LSIs via the power supply pads. A cable is connected to one of the I/O pins.
    Type: Grant
    Filed: April 28, 1994
    Date of Patent: December 12, 1995
    Assignee: NEC Corporation
    Inventor: Shoji Umesato
  • Patent number: 5461544
    Abstract: A plurality of integrated circuit devices are bonded to a substrate. Signal traces for corresponding pins of the devices are run to the same location, but are not electrically connected. They are, however, located in close physical proximity at a designated location. At this designated location, a properly shaped and sized contact can be used to contact all of the corresponding traces simultaneously, allowing parallel burn-in of all devices on the substrate to be performed. The devices can still be tested individually after burn-in. Once functionality of the overall subsystem has been confirmed and encapsulation completed, a permanent contact can be made at the designated location to all traces simultaneously so that the devices will be in parallel, and the substrate can be encapsulated to form a completed subsystem.
    Type: Grant
    Filed: June 1, 1994
    Date of Patent: October 24, 1995
    Assignee: SGS-Thomson Microelectronics, Inc.
    Inventor: Charles R. Ewers
  • Patent number: 5446674
    Abstract: A crosstalk verification device for preventing cross talk of an LSI layout pattern. An error extracting portion (17) which, referring to the contents of a design rule file (12) and a crosstalk noise reference voltage storing portion (18), processes coordinate data of an output wiring pattern in an output wiring pattern file (16) to determine a wire-to-wire capacitance of an overlap/parallel portion between an output wire of a transistor prone to exert crosstalk influence and an output wire of a transistor susceptible to crosstalk. The error extracting portion (17) then calculates the magnitude of crosstalk noise as a function of the wire-to-wire capacitance to specify a portion in which the magnitude of crosstalk noise exceeds reference voltages. The specified coordinate data is applied as error information to an error file (19).
    Type: Grant
    Filed: June 2, 1993
    Date of Patent: August 29, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Minoru Ikeda, Tsunesato Munakata
  • Patent number: 5442135
    Abstract: An electrical power distribution busway system which includes a housing having side channels and top and bottom channels is described. The channels enclose and secure at least one stack of conductive busbars in place. At least one of the top or bottom housing channels is adjustably mounted between the side channels so the overall housing may be adjusted to accommodate various arrangements of busbars or busbars having different thicknesses. In a preferred form of the invention, the adjustable channels include holes which are aligned with elongate slots through the side channels. Fasteners extending through the aligned holes and slots allow the adjustable channel to be moved and fixed at different locations along the elongate slot.
    Type: Grant
    Filed: March 25, 1993
    Date of Patent: August 15, 1995
    Assignee: Siemens Energy & Automation, Inc.
    Inventors: Nathan H. Faulkner, Ronald D. Nordenbrock
  • Patent number: 5436801
    Abstract: An integrated circuit structure which employs at least two metal levels overlying an array of circuit elements. Each metal level contains signal routing resources which can be used for supplying power and interconnecting circuit elements. The metal levels include a first metal level directly overlying the array of circuit elements, intermediate metal levels (if there are more than two metal levels), and a top metal level overlying all other metal levels. Power carrying tracks are disposed in the top metal level. Power antennae are disposed in the first metal level, but only where necessary to provide power to the circuit elements. The power antennae are for connecting the power carrying tracks to the circuit elements. Power bridges are disposed in intermediate metal levels between the first metal level and the top metal level. The power bridges are for connecting the power carrying tracks to the power antennae.
    Type: Grant
    Filed: September 9, 1993
    Date of Patent: July 25, 1995
    Assignee: CrossCheck Technology, Inc.
    Inventors: Tushar Gheewala, Rustam Mehta, Timothy Saxe
  • Patent number: 5434749
    Abstract: This invention concerns a hybrid printed circuit board which permits easy and reliable connection between small-current circuit conductors and large-current circuit conductors. The hybrid printed circuit board of this invention comprises: an insulating substrate of synthetic resin having fixing bosses erected thereon; a flexible printed circuit sheet having small-current circuit conductors; and busbars as large-current circuit conductors; wherein the flexible printed circuit sheet is stacked and arranged on the insulating substrate so that the fixing bosses erected on the insulating substrate pass through and above the flexible printed circuit sheet, the busbars as large-current circuit conductors are put in contact with the small-current circuit conductors, and the fixing bosses are heated and deformed to fix the busbars in place.
    Type: Grant
    Filed: March 9, 1994
    Date of Patent: July 18, 1995
    Assignee: Yazaki Corporation
    Inventor: Yoshiaki Nakayama
  • Patent number: 5426563
    Abstract: A three dimensional module for housing a plurality of integrated circuit chips is shown. The IC chips are mounted in rows on a plurality of substrates. Parallel to each row are communications bars which provide signal paths allowing chips on one substrate to communicate with those on another substrate. The communications bars also serve as spacers between substrates, thereby forming cooling channels. The IC chips are disposed in the cooling channels so that they come into direct contact with the cooling fluid. Signal lines to and from the IC chips are kept as separated as possible from the power lines so as to minimize noise. To this end, relatively thick power supply straps are mounted to each substrate below each row of IC chips. The power supply straps are, in turn, connected to power feed straps such that a very low impedance power supply path to the IC chips is maintained.
    Type: Grant
    Filed: November 22, 1993
    Date of Patent: June 20, 1995
    Assignee: Fujitsu Limited
    Inventors: Larry L. Moresco, David A. Horine, Wen-Chou V. Wang
  • Patent number: 5414219
    Abstract: A circuit control device includes two intermating foil pads separated from one another by a narrow gap having a maximum dimension of 0.006 inches. A circuit path having one side connected to one of the pads and a second side connected to the other of the pads is selectively closed and opened by solder application and removal operations. Interdigitated, triangular fingers which are intermated to form the device ensure the formation of acutely angled junctures along the gap to ensure solder bridging of the gap. Emergency control elements are coupled to the circuit control device to permit control of an associated circuit path if the circuit control device itself fails. In that event, an emergency control device is coupled to the emergency control elements to control opening and closing of the circuit path.
    Type: Grant
    Filed: April 22, 1994
    Date of Patent: May 9, 1995
    Assignee: AT&T Corp.
    Inventors: Curtis L. Huetson, Rick D. Jussel
  • Patent number: 5390081
    Abstract: Fault-tolerant power distribution system for back-mounted hardware in which a backplane arrangement delivers alternative sources of system power in a prioritized pattern to each of a plurality of fault-tolerant electronic cards via a plurality of system slots, each slot including a power port having electrical contacts in a common system pinout, and the cooperating system cards have electrical contacts in the same common system pinout. Any of the system cards can be installed in any system slot and will receive the system power in one of a plurality of fault-tolerant prioritizations.
    Type: Grant
    Filed: March 22, 1993
    Date of Patent: February 14, 1995
    Assignee: Stratus Computer, Inc.
    Inventor: Keith St. Pierre
  • Patent number: 5388028
    Abstract: A low impedance interconnection assembly for use with high frequency switching power semiconductor devices includes a low inductance modular capacitor, multi-layer planar bus structure and semiconductor switching devices assembled as a laminated unitary structure. Terminals electrically and physically connect the positive electrode of the modular capacitor to the positive DC voltage potential carried by the bus structure and the positive DC input of the semiconductor switch and other terminals electrically and mechanically couple the negative electrode of the modular capacitor to the negative DC voltage potential layer of the bus structure and the negative DC input of the switching device. The low inductance modular capacitor is made of a number of capacitor elements having their respective positive electrodes bonded to a copper foil pattern strip to define a positive electrode and their respective negative electrode terminals to a second copper foil strip to define the negative electrode.
    Type: Grant
    Filed: February 22, 1994
    Date of Patent: February 7, 1995
    Assignee: Kaman Electromagnetics Corporation
    Inventor: Zeljko Arbanas
  • Patent number: 5365108
    Abstract: A power semiconductor assembly, particularly a semiconductor switch assembly which has a number of discrete emitter connection pads, comprised of a metal matrix composite housing and a copper or aluminum post with a cross-sectional area sufficiently large to carry the rated current providing a single-point, external connection to all emitter pads. The post passes through and is supported by an insulating ceramic insert such as aluminum oxide in the wall of the metal matrix composite housing. The post is hollowed out in the region where it passes through the ceramic insert in order to reduce the mechanical stress between the post and the insulating insert as a result of the mismatch in their thermal expansion coefficients. Buses on either side of the semiconductor die provide surfaces for connection from the post to the discrete emitter connection pads on the die.
    Type: Grant
    Filed: November 19, 1992
    Date of Patent: November 15, 1994
    Assignee: Sundstrand Corporation
    Inventors: W. Kyle Anderson, Richard J. Hoppe, William J. Durako, Jr., Mark Metzler, Lawrence Hughes, Stephen E. Jackson
  • Patent number: 5363279
    Abstract: A semiconductor package having outer leads which are not protruded from the package but only exposed to outside. The semiconductor package comprises a semiconductor chip which is formed with a plurality of bond pads at a central portion of its bottom surface, a lead frame including leads connected to bond pads for input/output of the bond pads respectively and bus bars connected to power supplying pads of the bond pads, insulation adhesives for attaching inner leads of the leads and inner leads of the bus bars to a bottom surface of the semiconductor chip formed with the bond pads, metal wires for electrically connecting the inner leads of the leads and the inner leads of the bus bars to the bond pads respectively, and a molding compound enveloping the semiconductor chip assembly with outer leads of the lead frame exposed to outside. The adhesive tapes are removed after a molding procedure.
    Type: Grant
    Filed: November 3, 1992
    Date of Patent: November 8, 1994
    Assignee: Goldstar Electron Co., Ltd.
    Inventor: Gi Bon Cha
  • Patent number: 5341509
    Abstract: Disclosed is a parallel processing system comprising, in combination, a stack assembly of bus-printed disks and a plurality of processing unit boards standing upright around and electrically connected to the stack assembly of bus-printed disks. Each bus-printed disk has an IC crossbar switch at its center and printed signal conductors radiating from the IC crossbar switch, and terminated with impedance matching elements. A selected processing unit board has an IC crossbar switch controller to allow the switch elements of each crossbar switch to open and close in a predetermined sequence. With this arrangement communication lines of equal, shortest possible length are provided to make a required electrical connection between selected processing units. Thus, reliable, noise-free, high-speed transportation of data is permitted.
    Type: Grant
    Filed: November 6, 1991
    Date of Patent: August 23, 1994
    Assignee: Graphico Co. Ltd.
    Inventor: Tokuhei Takashima
  • Patent number: 5329424
    Abstract: A busbar holder includes a supporting base having engaging prongs located at opposing ends of the supporting base. These engaging prongs engage receptacles in a printed circuit board (PCB) to secure the supporting base to the PCB. Four securing prongs extending vertically upward and having catch hooks at their free end are attached to the respective corners of the supporting base. A supporting wall extending vertically upward is attached to the supporting base and located intermediate the four securing prongs. Busbars are inserted between the wall and two of the securing prongs and are secured in place by the catch hooks.
    Type: Grant
    Filed: September 1, 1993
    Date of Patent: July 12, 1994
    Assignee: AT&T Bell Laboratories
    Inventor: Jayesh R. Patel
  • Patent number: 5323214
    Abstract: An electrostatic actuator for forming an electric field for transporting the particles of a developer having a predetermined charge in a predetermined direction. A plurality of stripe-like drive electrodes are continuously formed on only one of opposite sides of a substrate in parallel. Pins are affixed to three electrode terminals and contact every third drive electrode selected in matching relation to the electrode terminals. The three terminals are held on an electrode connector which is fitted on one edge of the substrate. The portions of the pins contacting the drive electrodes are thinner than the portions connected to the electrode terminals.
    Type: Grant
    Filed: August 5, 1993
    Date of Patent: June 21, 1994
    Assignee: Ricoh Company, Ltd.
    Inventor: Tsukuru Kai
  • Patent number: 5313363
    Abstract: A low impedance interconnection assembly for use with high frequency switching power semiconductor devices includes a modular capacitor, multi-layer bus structure and semiconductor switching devices assembled as a laminated unitary structure. Terminals electrically and physically connect the positive electrode of the modular capacitor to the positive DC voltage potential carried by the bus structure and the positive DC input of the semiconductor switch and other terminals electrically and mechanically couple the negative electrode of the modular capacitor to the negative DC voltage potential layer of the bus structure and the negative DC input of the switching device. The modular capacitor is made of a number of capacitor elements having their respective positive electrodes bonded to a copper foil pattern strip to define a positive electrode and their respective negative electrode terminals to a second copper foil strip to define the negative electrode.
    Type: Grant
    Filed: July 28, 1993
    Date of Patent: May 17, 1994
    Assignee: EML Research, Inc.
    Inventor: Zeljko Arbanas
  • Patent number: 5304737
    Abstract: A semiconductor package comprising a connection pad device for electrically connecting at least a part of chip pads of a semiconductor chip with the corresponding inner leads of a lead frame. The connection pad device comprises a film as a connection pad device body, a plurality of copper foil wirings each having one end positioned to correspond to each chip pad of the semiconductor chip and the other end positioned to correspond to each inner lead of the lead frame, a plurality of first jumper pads protruded from the film, each of the first jumper pads being connected to one end of each corresponding copper foil wiring and wire-bonded to each corresponding chip pad, and a plurality of second jumper pads protruded from the film, each of the second jumper pads being connected to the other end of each corresponding copper foil wiring and wire-bonded to each corresponding inner lead.
    Type: Grant
    Filed: October 2, 1992
    Date of Patent: April 19, 1994
    Assignee: Goldstar Electron Co., Ltd.
    Inventor: Jin Sung Kim
  • Patent number: 5282112
    Abstract: A backplane comprises several socket connectors that are arranged in parallel, side by side on a side that faces the modules. The socket connector has pins which form a pin field that face away from the modules. At least one bus comprises at least one bus line. A bus contact pin of each socket connector of the bus has an associated contact pin. These contact pins are electrically connected to each other with a bus line. Each contact pin can be electrically connected with a jumper plug to its associated bus contact pin. A backplane comprising a bus that extends beyond the modules is thus obtained where modules can be separated from the bus without having to pull the modules from their plug-in locations on a module carrier.
    Type: Grant
    Filed: November 16, 1992
    Date of Patent: January 25, 1994
    Assignee: Siemens Aktiengesellschaft
    Inventor: Klaus Bremer
  • Patent number: 5276587
    Abstract: An electrical device to be electrically mounted to a cooling mounting structure so that the electrical device is in intimate physical contact with the mounting structure for cooling the electrical device. The electrical device having a first pivot allowing contact for allowing the electrical device to be pivoted as it is mounted to the cooling mounting structure so that the electrical device is in intimate physical contact with the cooling mounting structure and for providing an electrical connection to the cooling mounting structure and the electrical device further having a second nonpivot allowing contact having a shape for providing electrical contact with the mounting structure when the electrical device is in intimate physical contact with the cooling mounting structure.
    Type: Grant
    Filed: April 8, 1993
    Date of Patent: January 4, 1994
    Assignee: Sundstrand Corporation
    Inventor: Michael P. Ciaccio
  • Patent number: 5274528
    Abstract: An assembly for both distributing electricity and limiting the flow of current has a housing, input conductors, first output conductors, second output conductors, an insulating spacer block, and limiters. Portions of the input conductors and first output conductors overlay each other with the insulating spacer block therebetween. The limiters electrically connect the input conductors to the output conductors with pairs of limiters connected between a single input conductor and separate output conductors.
    Type: Grant
    Filed: August 3, 1992
    Date of Patent: December 28, 1993
    Assignee: Burndy Corporation
    Inventors: Rocco J. Noschese, Frederick D. Hooper