Abstract: If misalignment in a line width direction of an electrode (pad) of a connection terminal is caused in attachment of a substrate and an FPC, a connection area of the FPC terminal and the connection terminal becomes smaller and contact resistance is increased. In particular, an increase in contact resistance of the connection terminal to which a power supply potential serving as a power source is inputted is a cause of defective display. In view of the above, an object of the present invention is to decrease the resistance of a power supply line, to suppress a voltage drop in the power supply line, and to prevent defective display. A connection terminal portion includes a plurality of connection terminals. The plurality of connection terminals is provided with a plurality of connection pads which is part of the connection terminal. The plurality of connection pads includes a first connection pad and a second connection pad having a line width different from that of the first connection pad.

Abstract: As a multi-layered board, an EMI noise reduction board, having an electromagnetic bandgap structure with band stop frequency properties inserted into an inner portion of the board, includes a first area, in which a ground layer and a power layer are formed, and a second area, placed on a side surface of the first area, in which it has the electromagnetic bandgap structure formed therein so as to shield an EMI noise radiated to the outside through the side surface of the first area. The electromagnetic bandgap structure includes a plurality of first conductive plates, placed along the edge of the board, a plurality of second conductive plates, disposed on a planar surface that is different from the first conductive plates such that the second conductive plates are alternately disposed with the first conductive plates, and a via, which connects the first conductive plates to the second conductive plates.

Abstract: A circuit board laminated module includes: a first circuit board having a multi-layer structure in which ground layers are provided in a plurality of layers; a second circuit board mounted on the first circuit board; and a semiconductor chip mounted on the second circuit board, wherein in the first circuit board, a noise guiding through via which guides an electromagnetic noise generated in the semiconductor chip to a lower layer side is provided on a side different from a circuit portion or a circuit element desired to be protected against influence of the electromagnetic noise in a surrounding direction of an occurrence place of the electromagnetic noise.

Abstract: Disclosed is a printed circuit board including an electromagnetic bandgap structure. The electromagnetic bandgap structure for blocking a noise is inserted into the printed circuit board. The electromagnetic bandgap structure can include a first conductive plate; a second conductive plate arranged on a planar surface that is different from that of the first conductive plate; a third conductive plate arranged on a planar surface that is different from that of the second conductive plate; and a stitching via unit configured to connect the first conductive plate and the third conductive plate by bypassing the planar surface on which the second conductive plate is arranged and including a first inductor element.

Abstract: An intelligent network patch field management system is provided that includes electronic hardware, firmware, mechanical assemblies, cables, and software that provide visible and audible cues for connecting and disconnecting patch cords in an interconnect or cross-connect patching environment. Systems of the present invention also monitor patch cord connections in a network.

Abstract: A motherboard interconnection device includes a top layer, a bottom layer, a first and a third electronic elements positioned on the top layer, and a second and a fourth electronic elements positioned on the bottom layer. A first end of the first electronic element on the top layer is connected to the first end of the second electronic element on the bottom layer with a first via hole, and the first end of the third electronic element on the top layer is connected to the first end of the fourth electronic element on the bottom layer with a second via hole. The second ends of the two electronic elements on the top layer are connected to a first part, and the second ends of the two electronic elements on the bottom layer are connected to a second part.

Abstract: A semiconductor device reduces the impedance of a wiring for supplying the circuit excluding a data output circuit with a power source voltage or a ground voltage and of speedup of data signal transmission in the data output circuit. Additional substrates 2a, 2b are on the upper surface of semiconductor chip 1. First additional wiring layer for power source 10d and first additional wiring layer for ground 10s formed on respective additional substrates 2a, 2b form prescribed conductive areas on semiconductor chip 1. First power source wiring 40C1d or first ground wiring 40C1s are interconnected through additional wiring layers 10d and 10s. Second power source wiring 40C2d and second ground wiring 40C2s, which is extended in the same direction as with DQ system signal wiring 40CDQ, forms a feedback current path. Second power source wiring 40C2d and second ground wiring 40C2s are disposed adjacent to DQ system signal wiring 40CDQ.

Abstract: A circuit arrangement comprising a set of signal layers, a set of first power layers, a set of second power layers, a set of signal vias, a set of first power vias, a set of second power vias, wherein a signal via of the set of signal vias provides a signal path for a high-frequency (HF) signal current, wherein at least a power via of the set of first power vias and at least a power via of the set of second power vias provide return paths for return currents associated with the signal current, wherein the return path provided by the power via of the set of second power vias is connected with a power layer of the set of second power layers, wherein at least one power layer of the set of first power layers is arranged between the power layer of the set of second power layers and each signal layer of the set of signal layers.

Abstract: A light-emitting diode element including a through hole and a thermal via hole is mounted. An electrical connection region and a heat radiation region with respect to a plurality of packages or substrates are separately mounted on a printed circuit board. Electrical connection is made in the printed circuit board, and a driver, a resistance, a capacitor, and the like are connected. Heat is diffused and radiated by heat transport to a heat radiation base material connected to the printed circuit board.

Abstract: Provided is an integrated circuit system and method for biasing the same that features bifurcating a power distribution network to provide a bias voltage to the integrated circuit system. One of the branches of the power distribution network attenuates an impedance in the power distribution network that supplies transient currents and the remaining branch supplies a substantially steady-state currents.

Abstract: A wireless communication module includes: amounting board including a dielectric frame and a dielectric panel that are stacked together, the frame defining a frame space; at least one electronic component mounted on the mounting board and extending into the frame space; and a plurality of conductive bodies embedded in the dielectric frame and surrounding the frame space so as to prevent electromagnetic interference resulting from the electronic component.

Abstract: A wiring board has a wiring board main body, a solder resist and solder bumps. The solder resist is formed on a top surface of the wiring board main body, and includes first openings, and second openings that have a diameter larger than that of the first openings. The solder bumps are disposed in the first openings and in the second openings. In addition, top portions of the solder bumps disposed in the first openings have a flat face, while top portions of the solder bumps disposed in the second openings have a non-flat face.

Abstract: A power switch assembly includes a flip-chip type integrated circuit chip and a lead-frame with a plurality of spaced apart parallel lead sections. The flip-chip type integrated circuit chip includes a distributed transistor, and first and second pluralities of flip-chip interconnects connected to source and drain regions, respectively. The first and second lead sections at least partially overlap along the first axis. Each of the plurality of lead sections includes a contact portion and an extended portion extending laterally from the contact portion. The extended portions of the first and second lead section extend from the contact portion in opposite directions. The first side of the first and second lead section contacts at least two of the first and plurality of flip-chip interconnects, respectively. The second side of the first and second lead are configured to contact a first and second contact area on a printed circuit board, respectively.

Abstract: A printed circuit board includes a first signal via, a second signal via, and a first ground via. A distance between the first ground via and the first signal via is substantially equal to a distance between the first ground via and the second signal via.

Abstract: An electrically conductive structure includes a first conductive structure and a second conductive structure. Each has a conducting section at one end and a coupling section at the other end. The first and second conducting sections are electrically connected to a power and ground contact of an electronic device, respectively. The first and second coupling sections are respectively connected with power and ground layer of a circuit board. The first coupling sections are connected with the first conducting section through first extending sections and the second coupling sections are connected with the second conducting section through second extending sections. At least two coupling sections of the conductive structures are arranged in pairs. The first conductive structure and the second conductive structure are arranged in a staggered array to form two wiring loops having opposite current directions, thereby generating a magnetic flux cancellation effect.

Abstract: A semiconductor device including a pair of stacked semiconductor ICs capable of communicating with each other by wireless. Each IC has: a transmitter circuit operable to send, by wireless, transmit data together with a clock signal deciding a transmission timing, and arranged so that the wireless transmission timing is adjustable; a receiver circuit operable to receive data in synchronization with a clock signal received by wireless, and arranged so that its wireless reception timing is adjustable; and a control circuit operable to perform timing adjustments of the transmitter and receiver circuits based on a result of authentication of data returned by the other IC in response to data transmitted through the transmitter circuit, and received by the receiver circuit. This arrangement for near field communication between stacked semiconductor ICs enables: reduction of the scale of a circuit for communication timing adjustment; and highly accurate adjustment of the communication timing.

Abstract: A method of fabricating a rechargeable battery having an electrode assembly, a PCB and a battery case, wherein the electrode assembly is connected to the PCB, the method including preparing a PCB having a first surface with an external contact terminal formed thereon and having a second surface with a conductive feature formed thereon, wherein the conductive feature is electrically connected to the external contact terminal through a conductive trace, and plating the external contact terminal by electrically connecting a plating electrode to the conductive feature.

Abstract: A circuit board including a first patterned metal layer and a second patterned metal layer is provided. The first patterned metal layer has metal blocks and spiral structures. A gap is kept between any two adjacent metal blocks. Each of the spiral structures is electrically connected between any two adjacent metal blocks. The second patterned metal layer is disposed beside the first patterned metal layer and has jumper segments. Each of the jumper segments has a first end and a second end opposite to the first end. Each of the spiral structures has an outer end and an inner end. The outer end is connected to one of the two adjacent metal blocks. The inner end is electrically connected to the first end of one of the jumper segments, and the second end of the jumper segment is electrically connected to the other one of the two the metal blocks.

Abstract: A circuit structure for modifying characteristic impedance by using different reference planes is provided. The structure comprises an analog signal line, a digital signal line, a corresponding reference plane for analog signals and a corresponding reference plane for digital signals. Wherein, the line width of the analog signal line is the same as that of the digital signal line. In addition, the distance between the analog signal line and the corresponding analog signal reference plane is longer than the distance between the digital signal line and the corresponding digital signal reference plane. Accordingly, the characteristic impedance mismatch during signal transmission can be solved and the quality of signal transmission can be improved.

Abstract: Provided are vertical transitions which have the high electrical performance and the high shielding properties in the wide frequency band in a multilayer PCB, printed circuit boards with the vertical transitions and semiconductor packages with the printed circuit boards and semiconductor chips. In vertical transitions for a multilayer PCB, a wave guiding channel is a conductor which includes at least more than one of signal vias 201, an assembly of ground vias 202 surrounding the signal via, ground plates from conductor layers of the PCB connected to the ground vias, closed ground striplines 205 connecting the ground vias and power supply layer.

Abstract: A circuit board includes a plurality of conductive layers, a plurality of insulating layers, a telecommunication network connection port and a modem card processing module. A high voltage signal line is laid out at one of the conductive layers. The insulating layers are disposed between each of the conducting layers, respectively. The telecommunication network connection port is disposed on the conductive layers and is electrically connected to one end of the high voltage signal line. The modem card processing module is disposed on the conductive layers and is electrically connected to the other end of the high voltage signal line.

Abstract: A circuit arrangement for buck converters has a multiplicity of half bridges (10, 11). Each half bridge (10, 11) contains a first chip (HS1, HS2, HS3, HS4) and a second chip (LS1, LS2, LS3, LS4) , the first chip (HS1, HS2, HS3, HS4) and the second chip (LS1, LS2, LS3, LS4) in each case having a vertical power transistor. The load paths of the power transistor of the first chip (HS1, HS2, HS3, HS4) and of the power transistor of the second chip (LS1, LS2, LS3, LS4) are connected in series. The control inputs (G1, . . . , G8) of the power transistors can be driven individually. The half bridges (10, 11) are jointly accommodated in a semiconductor package and the first chip (HS1, HS2, HS3, HS4) and the second chip (LS1, LS2, LS3, LS4) lie above one another in each half bridge (10, 11).

Abstract: An electrical assembly (300, 400) includes a power IC such as a MOSFET (112, 412) attached to a substrate module (114, 214). The MOSFET includes a top surface comprising first and second conductive device surfaces (A, B), associated with first and second device ports, and a bottom surface comprising a third conductive device surface C associated with a third device port. A first foil element is bonded to the first conductive device surface(s) A and to each of the first conductive substrate surfaces (A1, A2) and provides a continuous conductive pathway from each conductive surface (A) to each other conductive surface (A) and to each conductive surface (A1, A2). A second foil element is bonded to the second conductive device surface(s) B and to the second conductive substrate surface B1 and provides a continuous conductive pathway from each device conductive surface (B) to the substrate conductive surface (B1).

Abstract: Embodiments of the present invention provide an electronic device. The electronic device includes a circuit board. A first circuit is disposed on a first side of the circuit board. The first circuit is connected to a first ground plane of the circuit board. A second circuit is disposed on a second side of the circuit board. The second side is opposite the first side, and the second circuit is connected to a second ground plane of the circuit board. Moreover, the first and second ground planes respectively lie in different planes of the circuit board and are electrically interconnected by a conductive trace disposed within the circuit board.

Abstract: An intelligent network patch field management system is provided that includes electronic hardware, firmware, mechanical assemblies, cables, and software that provide visible and audible cues for connecting and disconnecting patch cords in an interconnect or cross-connect patching environment. Systems of the present invention also monitor patch cord connections in a network.

Abstract: A multilayered printed circuit board includes a first surface layer that includes a semiconductor integrated circuit, a second surface layer that includes a bypass capacitor and that is opposite to the first surface layer, a main power supply wiring layer, and a ground layer between the first and second surface layers. In the multilayered printed circuit board, one terminal of the bypass capacitor is connected to a midpoint of a wiring path from the main power supply wiring layer to a power supply terminal of the semiconductor integrated circuit, and an impedance of a first wiring path from the main power supply wiring layer to the terminal of the bypass capacitor is higher than an impedance of a second wiring path from the terminal of the bypass capacitor to the power supply terminal of the semiconductor integrated circuit.

Abstract: The present invention provides an electronic control unit which is capable of suppressing harmful effects caused by liquid while suppressing increase in the size thereof. The electronic control unit includes an electronic component in which a circuit element coated with an anti-splash agent is implemented, a casing, and a liquid discharge portion. The casing includes a base on which the electronic component is mounted, a cover which is connected to the base in the state where the electronic component is covered with the cover, and a connector which electrically connects the electronic component to the outside. The liquid discharge portion includes a flow passage in which liquid which has intruded into an internal space in the casing formed by the base, the cover and the connector for housing the electronic component flows, and an opening portion which discharges the liquid to the outside of the internal space via the flow passage.

Abstract: Plated through holes pass through clearances in a ground plane of a circuit board. A conductive collar/spoke arrangement is constructed on the ground plane adjacent the clearance, to provide an inductive component to the coupling between a plated through hole and the ground plane. The inductive component impedes the transfer of high-frequency noise between the through hole and the ground plane. Other embodiments are also described and claimed.

Abstract: A shielding structure is provided for shielding a signal path extending between a first layer and a second layer in an electronic device at a transition region with a transition that extends in a first direction and a second direction orthogonal to the first direction. The shielding structure includes a shielding structure portion, which includes a first shielding via in proximity to a first area of the signal path at the transition; a second shielding via in proximity to a second area of the signal path at the transition; and an area metallization electrically coupled to the first shielding via.

Abstract: A circuit board includes a plurality of signal lines and a plurality of shielding walls. The shield walls are disposed between the signal lines. Each shield wall includes an upper surface, a lower surface, a rectangular groove, a first metal layer and a second metal layer. The lower surface is opposite to the upper surface. The rectangular groove extends from the upper surface to the lower surface. The first metal layer is disposed on the upper surface. The second metal layer is disposed in the rectangular groove and electrically connected to the first metal layer.

Abstract: First sheet-like substrate is arranged at a region surrounded by first terminals of male connector and first circuit substrate, and second sheet-like substrate is arranged at a region surrounded by second terminals of female connector and second circuit substrate, and male connector and female connector are fitted together so that a first passive element of first sheet-like substrate and a second passive element of second sheet-like substrate configure a filter circuit.

Abstract: The present invention is directed to a method of fabricating an integrated circuit package having decoupling capacitors using a package design conceived for use without decoupling capacitors. The package is implemented with a minimal redesign of the original design and not requiring any redesign of the signal trace pattern. The invention involves replacing top and bottom bond pads with via straps and then covering the top and bottom reference planes with a dielectric layer having conductive vias that electrically connect with the underlying via straps. Planes having the opposite polarity of the underlying reference plane are then formed on the dielectric layer. These planes include an array of bonding pads in registry with the vias. Decoupling capacitors are mounted to the top of the package and electrically connected with the plane on top of the package and the immediately underlying reference plane without the electrical connections to the capacitors passing through the signal planes of the package.

Abstract: The present invention describes methods for enhancing the performance of two-capacitor low-pass filters. In certain embodiments of the invention, the capacitors are placed on opposite sides of a PCB board.

Abstract: A component having reference layer openings to contribute towards achieving a differential impedance in a circuit, is described herein.

Abstract: A heat-conductive package structure includes a carrier board having a first surface and an opposing second surface and formed with a through opening passing the carrier board; a first heat-conductive structure including a heat-conductive hole in the through opening, a first heat-conductive sheet on the carrier board, and a second heat-conductive sheet on the carrier board, wherein the first and second heat-conductive sheets are conductively connected by the heat-conductive hole; a first dielectric layer formed on the first surface of the carrier board and formed with a first opening for exposing the first heat-conductive sheet; a second dielectric layer formed on the second surface of the carrier board and formed with at least a second opening for exposing a portion of the second heat-conductive sheet; and a second heat-conductive structure formed in the second opening and mounted on the second heat-conductive sheet.

Abstract: Substrates having power and ground planes, such as, for example, printed circuit boards, include at least one noise suppression structure configured to suppress electrical waves propagating through at least one of a power plane and a ground plane. The noise suppression structure may include a power plane extension that extends from the power plane generally toward the ground plane, and a ground plane extension that extends from the ground plane generally toward the power plane. The ground plane extension may be separated from the power plane extension by a distance that is less than the distance separating the power and ground planes. Electronic device assemblies and systems include such substrates. Methods for suppressing noise in at least one of a power plane and a ground plane include providing such noise suppression structures between power and ground planes.

Abstract: A multilayered printed circuit board includes a first surface layer that includes a semiconductor integrated circuit, a second surface layer that includes a bypass capacitor and that is opposite to the first surface layer, a main power supply wiring layer, and a ground layer between the first and second surface layers. In the multilayered printed circuit board, one terminal of the bypass capacitor is connected to a midpoint of a wiring path from the main power supply wiring layer to a power supply terminal of the semiconductor integrated circuit, and an impedance of a first wiring path from the main power supply wiring layer to the terminal of the bypass capacitor is higher than an impedance of a second wiring path from the terminal of the bypass capacitor to the power supply terminal of the semiconductor integrated circuit.

Abstract: If misalignment in a line width direction of an electrode (pad) of a connection terminal is caused in attachment of a substrate and an FPC, a connection area of the FPC terminal and the connection terminal becomes smaller and contact resistance is increased. In particular, an increase in contact resistance of the connection terminal to which a power supply potential serving as a power source is inputted is a cause of defective display. In view of the above, an object of the present invention is to decrease the resistance of a power supply line, to suppress a voltage drop in the power supply line, and to prevent defective display. A connection terminal portion includes a plurality of connection terminals. The plurality of connection terminals is provided with a plurality of connection pads which is part of the connection terminal. The plurality of connection pads includes a first connection pad and a second connection pad having a line width different from that of the first connection pad.

Abstract: The invention relates to an electrical device comprising a substrate carrying at least one component comprising at least one electrode, a first connecting line electrically connected to said electrode, wherein the first connecting line bridges a second connecting line by means of a crossover. The crossover is, at least at one side, bounded by an electrically insulating structure. The invention allows new testing methods and efficient lead-outs for an electrical device, such as electroluminescent display devices.

Abstract: A multilayered printed circuit board includes a first surface layer that includes a semiconductor integrated circuit, a second surface layer that includes a bypass capacitor and that is opposite to the first surface layer, a main power supply wiring layer, and a ground layer between the first and second surface layers. In the multilayered printed circuit board, one terminal of the bypass capacitor is connected to a midpoint of a wiring path from the main power supply wiring layer to a power supply terminal of the semiconductor integrated circuit, and an impedance of a first wiring path from the main power supply wiring layer to the terminal of the bypass capacitor is higher than an impedance of a second wiring path from the terminal of the bypass capacitor to the power supply terminal of the semiconductor integrated circuit.

Abstract: A protective circuit board for a battery pack for controlling charge and discharge states of the battery pack includes an insulation layer and a first signal pattern disposed inside the insulation layer. The circuit can further include a second signal pattern disposed inside the insulation layer. The circuit can include a first dummy pattern spaced from a first side of the first signal pattern and a second dummy pattern spaced from a second side of the first signal pattern.

Abstract: An electronic circuit, preferable as a sensor node, has a highly sensitive radio function and is capable of performing a low-power-consumption operation. The electronic device has a board; a connector for connecting a sensor; a first signal processor circuit receiving an input of sensor data from the sensor through the connector and forming transmission data; and a second signal processor circuit converting a transmission signal from the first signal processor circuit into a high-frequency signal. The connector and the first signal processor circuit are mounted on a first surface of the board, and the second signal processor circuit is mounted on a second surface of the board.

Abstract: An in-chip system and method for removing heat from integrated circuits is disclosed. One embodiment is a substrate with a front side and a back side. The front side of the substrate is capable of having formed thereon a plurality of transistors. A plurality of structures within the substrate contain a solid heat conductive media comprising carbon nanotubes and/or a metal, such as copper. At least some of the plurality of structures extend from the back side of the substrate into the substrate. In some embodiments, the carbon nanotubes are formed within the substrate using a catalyst.

Abstract: A circuit board may include first and second sides, a plurality of circuit board layers between the sides, and a plurality of signal traces located in respective circuit board layers. The circuit board layers and the signal traces may extend from a first component connection region at the first side of the circuit board to a second component connection region at the first side of the circuit board. The signal traces may thus form stubless signal paths through the circuit board between the component connection regions. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

Abstract: A chassis and associated telecommunication circuit card are disclosed. The chassis has heat dissipation and flame containment features while accommodating a high density of the circuitry cards. Embodiments include an inner housing with a double-layer middle floor dividing the chassis into top and bottom chambers. Each layer has partially aligned slots, and an air gap is provided between the two layers. Embodiments also include a double-layer mesh cover with an air gap existing between the two mesh layers. Projections and grooves are provided on the inner surfaces of the inner housing to receive circuit cards having a guide on one edge and a fin on another. The circuit card includes conductor structures such as multiple board layers with paired and segregated conductors. The circuit card also includes some components positioned to cooperate with the ventilation features of the chassis and includes some components chosen for low-power consumption or reduced flammability.

Abstract: An arrangement of non-signal through vias suitable for a wiring board is provided. The wiring board has a contact surface, a core layer and pads. The contact pads are disposed on the contact surface, while the arrangement of non-signal through vias includes first non-signal through vias and a second non-signal through via. The first non-signal through vias pass through the core layer and are electrically connected to some of the contact pads. The second non-signal through via which passes through the core layer is disposed between the first non-signal through vias and is not electrically connected to the contact pads. The interval between the second non-signal through via and anyone of the surrounding first non-signal through vias is smaller than or equal to 0.72 times of the minimum interval between any two of the contact pads electrically connected to the corresponding first non-signal through vias.

Abstract: An embodiment of the present invention is a technique to assemble multi-core dice. A first socket has first N sets of front side bus (FSB) contacts to house a first package having first 2N dice. Each of the first 2N dice has M cores. N and M are positive integers. A first chipset has 2N FSB signal groups interfacing to the first package via the first N sets of FSB contacts using first N FSB signal groups of the 2N FSB signal groups.

Abstract: A mounting structure includes: a first substrate; a second substrate; a first terminal being formed on the first substrate and having a plurality of terminal portions arranged with a gap therebetween; a different terminal being formed on the first substrate and being adjacent to the first terminal; and a second terminal being formed on the second substrate and being electrically connected to at least one of the terminal portions of the first terminal. Here, the first terminal is supplied with a potential higher than that supplied to the different terminal.

Abstract: The invention provides a multilayer printed wiring board including: a power supply wiring layer and a ground wiring layer provided so as to oppose each other via an insulation layer; mounted integrated circuits; and decoupling capacitors mounted in proximity to the integrated circuits and connected between the power supply wiring layer and the ground wiring layer to absorb noise from the integrated circuits. The power supply wiring layer includes through holes for connecting the decoupling capacitors to the power supply wiring layer and has a polygonal form formed by straight lines which link some of the through holes.

Abstract: According to the package board of the present invention, each soldering pad formed on the top surface of the package board, on which an IC chip is to be mounted, is small (133 to 170 ?m in diameter), so the metallic portion occupied by the soldering pads on the surface of the package board is also small. On the other hand, each soldering pad formed on the bottom surface of the package board, on which a mother board, etc. are to be mounted, is large (600 ?m in diameter), so the metallic portion occupied by the soldering pads on the surface of the package board is also large. Consequently, a dummy pattern 58M is formed between conductor circuits 58U and 58U for forming signal lines on the IC chip side surface of the package board thereby to increase the metallic portion on the surface and adjust the rate of the metallic portion between the IC chip side and the mother board side of the package board, protecting the package board from warping in the manufacturing processes, as well as during operation.