Abstract: An interconnect module for an integrated circuit chip incorporates a thin, high dielectric constant embedded capacitor structure to provide reduced power distribution impedance, and thereby promote higher frequency operation. The interconnect module is capable of reliably attaching an integrated circuit chip to a printed wiring board via solder ball connections, while providing reduced power distribution impedance of less than or equal to approximately 0.60 ohms at operating frequencies in excess of 1.0 gigahertz.

Abstract: A decoupling capacitor structure and its use in a circuit board mounting an ASIC is provided. The decoupling capacitor structure is arranged so that parasitic inductance caused by the connection to the decoupling capacitor and the decoupling capacitor itself is reduced. The circuit boards include at least two voltage planes. An ASIC having active device(s) is connected to one face of the circuit board. A decoupling capacitor structure is provided having at least two conductive plates in a dielectric material and is connected directly or indirectly to the ASIC. Vias extend from the conductive plates through the dielectric material to connect to circuit board vias on a second face of the printed circuit board or to the ASIC. The decoupling capacitor vias are parallel to each other; and each via connected to one conductive plate is located adjacent a via connected to another conductive plate to minimize voltage deviation.

Abstract: To provide a printed circuit board, a buildup substrate and a method of manufacturing the printed circuit board capable of curbing a transmission loss thereof at a desired frequency.

Abstract: A system and method for distributing power to an integrated circuit. In one embodiment, a power laminate may be mounted to a printed circuit board (PCB). The integrated circuit for which power is to be distributed may be electrically coupled to the PCB. The power laminate may include one or more power planes and one or more reference (i.e. ground) planes, with each pair of power/reference planes separated by a dielectric layer. The power laminate may also include a connector or other means for receiving power from an external power source. The power laminate may be electrically coupled to the integrated circuit, thereby enabling it to provide core power to the integrated circuit. The power laminate may also include a voltage regulator circuit, and a plurality of decoupling capacitors. In one embodiment, the power laminate may include a plurality of apertures which allow for the passing of connections between the integrated circuit and the PCB.

Abstract: Disclosed is a printed circuit board which is advantageous in terms of high capacitance by embedding capacitors comprising polymer capacitor pastes with high-dielectric constant coated on an inner layer of the printed circuit board and then semi-dried to a state of B-stage.

Abstract: The present invention is a reconfigurable substrate which includes at least one signal line layer stack. Each signal line layer stack is defined to include two substantially parallel insulating layers and a signal line layer interposed between the two insulating layers and substantially parallel to the insulating layers. The substrate includes at least one conductive isolation layer adjacent to at least one signal line layer stack and substantially parallel to the at least one signal line layer stack. The substrate is reconfigurable to different performance levels by adding or removing at least one conductive isolation layer.

Abstract: A power amplifier assembly combines a single printed circuit board with a housing for providing isolation between subcircuits of the circuit board. The printed circuit board is provided with four conductive layers and contains a power supply subcircuit, an upconverter subcircuit, a monitor and control subcircuit, a low power gain subcircuit, and a high power gain subcircuit. The printed circuit board is further provided with plated-through vias in an isolation path which, in conjunction with internal chassis lid walls, serves to increase electromagnetic and radio frequency isolation between subcircuits on the printed circuit board.

Abstract: An integrated circuit having multiple power/ground connections to a single external terminal and method for manufacturing an integrated circuit provides an integrated circuit having a reduced number of external power/ground terminals. The multiple connections may be made by conductive circuit paths on one side of the substrate and a terminal pad on the same side of the substrate, with the conductive circuit paths leading from die terminals terminating at the terminal pad, or a via may be formed either directly above the terminal pad or contacting its circumference to provide a connection through from the opposite side of the substrate. Multiple vias may be formed above the terminal pad and within its circumference to provide connection of multiple die terminals to the terminal pad.

Abstract: A semiconductor device includes: a multi-layered wiring substrate in which a multiple wiring pattern layers are laminated through insulating layers. The multi-layered wiring substrate has a first, semiconductor element mounting face and a second face opposite to the first face. A semiconductor element is mounted on and connected to connecting pads on the first face. A chip-capacitor is arranged on and connected to the connecting pads on the second face. An electric power supply circuit includes the chip-capacitor for supplying electric power to the semiconductor element. Conductor paths for electrically connecting the first connecting pads with the second connecting pads are substantially extended vertically and penetrate through the multi-layered wiring substrate through so as to reduce the length of the conductor paths to a minimum, so that the chip-capacitor is located at the opposite side of the semiconductor element.

Abstract: According to one embodiment, a printed circuit board (PCB) is disclosed. The PCB includes a first functional unit block (FUB) and differential traces coupled to the first FUB. The first FUB transmits high-speed serial data. The differential traces carry the high-speed serial data from the first FUB. In addition, the differential traces crossover on the same layer of the PCB while maintaining a constant impedance.

Abstract: Apparatus is described for capacitively signalling between different semiconductor chips and modules without the use of connectors, solder bumps, wire-bond interconnections or the like. Preferably, pairs of half-capacitor plates, one half located on each chip, module or substrate are used to capacitively couple signals from one chip, module or substrate to another. The use of plates relaxes the need for high precision alignment as well as reduces the area needed to effect signalling, and reduces or eliminates the requirements for exotic metallurgy.

Abstract: A system and method are disclosed in which separate impedance compensation circuitry is allocated for an interface according to the space occupied on a printed circuit board (PCB) by the interface. Where an interface occupies two or more layers of the PCB, an impedance compensation circuit is dedicated to each layer on behalf of the interface. By dedicating impedance compensation, not just to the interface alone, but to the physical space occupied by the interface, the system and method are able to exploit multiple-layer and same-layer trace impedances, save board space and/or provide AC timings recovery.

Abstract: A first signal path is connected to a first plane via a plated hole. A first metal flood is connected to the plated hole to form a first plate. A second signal path is on a second plane. A second metal flood connected to the second signal path to form a second plate above the first plate.

Abstract: A method of reducing electromagnetic interference and improving signal quality in printed circuit boards with plane splits is described. The use of a lossy slot filling is described. The lossy filling is applied above plane splits and squeezed into the slots. The lossy material helps to damp antenna resonance.

Abstract: A multi-layer wiring board comprises an insulating substrate having, on a central part of its top surface, a semiconductor device mounting portion and having, on its under surface, an external electrode. The insulating substrate includes a multilayered wiring having a first group of parallel wiring lines; a second group of parallel wiring lines arranged orthogonal thereto; and a group of through conductors for providing electrical connection therebetween. Power is supplied from the external electrode to the semiconductor device through built-in capacitors formed therewithin. The built-in capacitors are connected in parallel that have different resonance frequencies within a range from an operating frequency band for the semiconductor device to a frequency band for a harmonic component, and at an anti-resonance frequency occurring between the different resonance frequencies, a composite impedance is equal to or below a predetermined value.

Abstract: A reduced noise ultrasound piezo film array on a printed circuit board. A printed circuit board carries a piezo array on one end and a standard coupling at the other end. The board is made in four layers with the two external layers being ground planes to prevent noise pickup. The two internal layers carry printed circuit lines between various elements of the array and terminals of the connector. The various arrays are sequentially scanned. All of the lines except the one selected are connected to ground to prevent crosstalk and noise pickup.

Abstract: In a circuit board comprising multiple layers and having an integrated circuit mounted on the outer layer thereof, a main power supply plane and a sub-power supply plane, which is disposed in an island fashion with a clearance that terminates electric connection with the main power supply plane, are formed on the same layer. The main power supply plane and the sub-power supply plane are connected by first power supply patterns that are formed on a layer different from the layer on which the power supply planes are formed and to which bypass condensers are connected. Power supply to some power supply terminals is achieved via second power supply patterns that are connected to the sub-power supply plane. The leakage of noise from the power supply terminals connected to the second power supply patterns is controlled by the first power supply patterns. Through this construction, the EMI noise radiated from the circuit board can be reduced while minimizing the number of bypass condensers.

Abstract: There has been a problem that a mode (a high-order mode) different from a basic propagation mode occurs at a point of a through conductor and a transmission characteristic deteriorates greatly. The present invention is a high-frequency wiring board wherein L>&lgr;/4 and &pgr;(A+B)≦&lgr; are satisfied in which L is a length of a through conductor, A is a diameter of the through conductor, B is shortest distances between the through conductor and a plurality of ground through conductors, &pgr; is a circle ratio and &lgr; is an effective wavelength of a high-frequency signal transmitted by the through conductor. It is possible to inhibit a high-order mode which occurs at a point of the through conductor.

Abstract: An interconnect module for an integrated circuit chip incorporates a thin, high dielectric constant embedded capacitor structure to provide reduced power distribution impedance, and thereby promote higher frequency operation. The interconnect module is capable of reliably attaching an integrated circuit chip to a printed wiring board via solder ball connections, while providing reduced power distribution impedance of less than or equal to approximately 0.60 ohms at operating frequencies in excess of 1.0 gigahertz.

Abstract: An insulation layer is formed on a ground layer. The insulation layer includes first and second regions for forming wiring layers. The impedance of a wiring layer formed on the second region is lower than that of a wiring layer formed on the first region. A signal line pattern is formed on the wiring layer on the first region of the insulation layer. A power supply plane is formed on the wiring layer on the second region of the insulation layer in order to feed power to the signal line pattern through a termination resistor connected to the signal line pattern.

Abstract: A technique for electrically interconnecting electrical signals between an electronic component and a multilayer signal routing device is disclosed. In one particular exemplary embodiment, the technique may be realized as an interconnect array for electrically interconnecting electrical signals between an electronic component and a multilayer signal routing device having a plurality of electrically conductive signal path layers. In such a case, the interconnect array comprises a plurality of electrically conductive contacts grouped into a plurality of arrangements of electrically conductive contacts, wherein each of the plurality of arrangements of electrically conductive contacts are separated from other adjacent ones of the plurality of arrangements of electrically conductive contacts by a channel that is correspondingly formed in the multilayer signal routing device such that an increased number of electrical signals may be routed therein on the plurality of electrically conductive signal path layers.

Abstract: An output of a voltage regulator is a core voltage line that runs adjacent to a die attach area on a packaging substrate. An input of the voltage regulator is typically coupled to a power supply which, in one embodiment, is also an I/O voltage line that runs adjacent to the die attach area. In one embodiment, the core voltage line is shaped as a ring encircling the die attach area on the packaging substrate. In another embodiment, the I/O voltage line is also shaped as a ring encircling the die attach area on the packaging substrate. Further, a semiconductor die having at least one I/O Vdd bond pad and at least one core Vdd bond pad can be mounted in the die attach area. The I/O Vdd bond pad and the core Vdd bond pad can be connected, respectively, to the I/O voltage ring and the core voltage ring.

Abstract: A multilayer ceramic semiconductor chip carrier is provided by a method of interconnecting ground, signal and power lines in a semiconductor chip carrier. The method involves forming a plurality of insulating layers with conductor lines comprising power and ground lines connected in parallel in a single plane formed in planes between the insulating layers. The parallel lines are directed in orthogonal directions in parallel between any two of the insulating layers with alternation successively between planes of X-directed lines and planes of Y-directed coplanar signal, power and ground lines. There are via connections formed between planes connecting a power line in one plane to another power line in another plane. Other via connections between planes connect a ground line in a first plane to another ground line in a second plane, and signal lines are formed in parallel between a ground line and a power line in a given plane.

Abstract: A stacked radio-frequency module is formed by stacking packages each storing MMICs and mounting another package upside down which stores a control circuit for controlling MMICs. The MMICs and control circuits are each sealed by a metal sealing lid within the cavity of each of the packages which are spatially completely separated from each other. Each of the pads for wiring paths for radio-frequency signals and for power supply/control signals and ground pads are provided within each package and at opposing surfaces of packages to be stacked with corresponding pads joined by a gold bump.

Abstract: A breadboard comprising a plate made of an insulating material and having a connection strip portion including a grouping of at least three rows of sets of at least three spaced apart holes in each set in the plate, the centers of the holes in each set being spaced from each other by a predetermined distance defined as a space, groups of at least three connector clips in the plate each connected in at least a three gang grouping, each referred to as a conductive strip which is aligned with and beneath one of the rows of sets of pinholes with all conductive strips being electrically isolated from each other, and all the in each row being offset from the conductive strip in an adjacent row by the predetermined distance and the sets being aligned in each row, end-to-end, with one space between end holes of two adjacent sets in a row, and each row being offset or staggered from each adjacent row by at least one space such that an array of spaces is formed, with each interior space in the middle row forming a cent

Abstract: A circuit board includes (i) a section of circuit board material having a signal conductor, a ground conductor, and dielectric material that separates the signal conductor and the ground conductor, and (ii) a signal launch. The signal launch includes a signal via that contacts the signal conductor and the dielectric material of the section of circuit board material, a first set of ground vias and a second set of ground vias. The ground vias contact the ground conductor and the dielectric material of the section of circuit board material. The first set of ground vias is disposed a first radial distance from the signal via. The second set of ground vias is disposed a second radial distance from the signal via. A coaxial connector mounts to the signal launch of the circuit board in order to provide electrical access to the signal and ground conductors.

Abstract: The invention relates to an integrated circuit assembly and a method of making same. The method according to the invention comprising providing a flex substrate having one or more dielectric tape layers, assembling one or more semiconductor chips to said flex substrate, said semiconductor chips having an active surface and a plurality of contact pads on said active surface, providing one or more conductive layers on said flex substrate, said conductive layers forming the electrical connections required for the assembly, electrically connecting the contact pads to the conductive layers.

Abstract: Each wiring layer of a multilayered wiring substrate includes signal wirings disposed in parallel with one another, and dummy wirings disposed at each side parallel to the signal wirings of the signal wiring group made by signal wiring, respectively. The dummy wirings have the same shape as the signal wirings, and are disposed in parallel to the signal wirings at the same intervals as that in the signal wirings. Through holes are formed in the respective clearances among the signal wirings. Dummy through holes having the same shape as the through holes are formed between the dummy wiring and signal wiring. A conductive layer is formed on the inner wall of the through holes. The multilayered wiring substrate is able to reduce or eliminate the delay time difference between signals that propagate along the signal wirings.

Abstract: A method for forming an electrically isolated via in a multilayer ceramic package and an electrical connection formed within the via are disclosed. The method includes punching a first via in a first layer, filling the first via with a cross-linkable paste, curing the paste to form an electrical insulator precursor and forming the via in the insulator precursor. The electrical connection formed includes an insulator made from a cross-linked paste supported by a substrate of a multilayer ceramic package and a conductive connection supported by the insulator.

Abstract: A method including routing a signal from a memory device on an integrated circuit in a package to a memory module, and returning the signal to a reference line in the package between the memory module and the integrated circuit. Also, a method including providing a memory module including at least one memory package configured for electrically coupling to a bus on a system board, the at least one memory package comprising an integrated circuit including a plurality of memory devices, and a package substrate including a surface having a plurality of externally accessible contact points coupled to the memory devices and an externally accessible reference signal line and a surface of the package, and tuning the electrical characteristics of the memory package using an electrical potential between the contact points and the reference signal line.

Abstract: The invention relates to an electronic component comprising a first conductive layer, a non-conductive layer and a second conductive layer. A hole is etched through the non-conductive layer. A nanotube, which is provided in said hole, links the first conductive layer to the second conductive layer in a conductive manner.

Abstract: Power and ground planes used in Printed Circuit Boards (PCBs) having porous, conductive materials allow liquids (e.g., water and/or other solvents) to pass through the power and ground planes, thus decreasing failures in PCBs (or PCBs used as laminate chip carriers) caused by cathodic/anodic filament growth and delamination of insulators. Porous conductive materials suitable for use in PCBs may be formed by using metal-coated organic cloths (such as polyester or liquid crystal polymers) or fabrics (such as those made from carbon/graphite or glass fibers), using metal wire mesh instead of metal sheets, using sintered metal, or making metal sheets porous by forming an array of holes in the metal sheets. Fabrics and mesh may be woven or random. If an array of holes is formed in a metal sheet, such an array may be formed with no additional processing steps than are performed using conventional PCB assembly methods.

Abstract: A PCSB assembly including a PCSB; a first plurality of LVD SCSI bus signal trace pairs formed in the PCSB; a second plurality of LVD SCSI bus signal trace pairs formed in the PCSB and positioned next adjacent one another for the entire length thereof comprising a RESET signal trace pair, a SELECT signal trace pair and a BUSY signal trace pair.

Abstract: In a circuit board having a multilayer structure comprising a ground pattern and a power-supply pattern both, for example, by forming a plurality of slits along each side of the ground pattern or the power-supply pattern, a long thin conduction path connecting a corner and a side center of the ground pattern is formed and resistive elements are placed in the middles of the conduction path to short, circuit the corner and a side center of the ground pattern. Therefore, portions corresponding to an antinode and a node or antinode and an antinode of a standing wave are short-circuited. The standing wave is generated when electric power is supplied to ICs and LSIs mounted on the circuit board. Thus, noise sources caused by the standing wave cancel each other. As a result, the occurrence of an antiresonance phenomenon and an increase in impedance of the power supplying system caused by the standing wave can be suppressed.

Abstract: A circuit comprising is disclosed herein. An embodiment of the circuit may comprise first and second printed circuit boards. The first printed circuit board may comprise first and second conductive planes. The first conductive plane has a first shape and the second conductive plane has a second shape, wherein the first shape is substantially similar to the second shape. The first conductive plane is located adjacent the second conductive plane, wherein the first conductive plane is parallel to and aligned with the second conductive plane. The second printed circuit board is connected to the first printed circuit board.

Abstract: A substrate having a conductive plane and a via passing through the conductive plane is provided. The conductive plane contacts the via to electrically interconnect the via and the conductive plane. A gap in the conductive plane separates a surface of the via from the conductive plane to provide an uninterrupted path for electrical current flowing substantially on the surface of the via.

Abstract: A connecting method of connecting covered wires with each other and recessed resinous tips used in the method are provided. In the method, it is executed at the first step to put a connecting part constituted by a shield wire and a ground wire between a first resin tip and a second resin tip. The first resin tip has, around the connecting part, first recessed parts for accommodating the molten cover of the shield wire and second recessed parts for accommodating the molten cover of the ground wire. The second resin tip has second recessed parts formed for accommodating the molten cover of the ground wire.

Abstract: Embodiments of the present invention provide an electronic device. The electronic device includes a circuit board. A first circuit is disposed on a first side of the circuit board. The first circuit is connected to a first ground plane of the circuit board. A second circuit is disposed on a second side of the circuit board. The second side is opposite the first side, and the second circuit is connected to a second ground plane of the circuit board. Moreover, the first and second ground planes respectively lie in different planes of the circuit board and are electrically interconnected by a conductive trace disposed within the circuit board.

Abstract: An integrated circuit package and a method of manufacturing the package. A silicon chip is attached to the surface of a substrate or attached to the bottom surface of a cavity in the substrate so that the active surface of the chip is exposed. One or more build-up circuit structures are formed over the substrate. Each build-up circuit structure has at least one insulation layer, at least one patterned circuit layer and a plurality of via openings with conductive material therein so that bonding pads on the active surface of the chip connect electrically with the patterned circuit layer through the vias. To form a ball grid array package, solder balls may also be attached to the solder ball pads on the patterned circuit layer so that the bonding pads on the chip are electrically connected to an external circuit through the build-up circuit structure and the solder balls.

Abstract: An enhanced Printed Circuit Board (PCB) and stacked substrate structure. In one embodiment, each middle layer is coupled between two ground layers except for the top signal layer and the bottom solder layer. In another embodiment, the top signal layer and the bottom solder layer are respectively coupled between two ground layers, so all signal layers are implemented in the stacked substrate structure and any internal signal layer is coupled between two ground layers. Thus, all signals can refer to adjacent ground layers and achieve better signal quality. Also, each capacitance structure formed by a signal layer and a ground layer increases the operating speed of the entire circuit.

Abstract: High aspect ratio (5:1-30:1) and small (5 &mgr;m-125 &mgr;m) diameter holes in a dielectric substrate are provided, which are filled with a solidified conductive material, as well as a method of filling such holes using pressure and vacuum. In certain embodiments, the holes are lined with conductive material and/or capped with a conductive material. The invention also contemplates a chip carrier formed by such material.

Abstract: An apparatus comprising an integrated circuit comprising a plurality of memory devices and signal circuitry coupled to the plurality of memory devices, and a package substrate comprising a first surface coupled to the integrated circuit, a second surface having a plurality of externally accessible contact points coupled to the signal circuitry, and an externally accessible reference signal line disposed between the integrated circuit and the second surface.

Abstract: In one embodiment, reducing electromagnetic radiation from sources within a substrate, such as a substrate for supporting an integrated circuit die, where the substrate comprises power layers, ground layers, and ground rings surrounding all or a portion of the power layers, where the ground layers and the ground rings are extended at least to the edges of the substrate so that conductive plates may be in electrical contact with the ground layers and the ground rings so as to define an enclosure to substantially contain electromagnetic radiation from sources within the defined enclosure.

Abstract: A PCB (Printed Circuit Board) design support system and a PCB design method reduce radiation of electromagnetic waves by optimizing layout of a substrate while following a conventional method for designing a PCB and maintaining a conventional structure. The PCB design support system includes an input information section for a ground plane structure, power plane structure and layout of a PCB, a circuit model section for calculating voltages between the ground plane and power plane and distribution of currents flowing on the ground plane and power plane using input information, a frequency selection section and a section to display obtained voltage and current distribution in a form of two-dimensional voltage and current distribution maps corresponding to shapes of the PCB. The PCB design support system enables a via-hole disposed between planes and/or wiring installed between planes causing variations in voltages to be specified in a precautionary manner from a PCB design stage.

Abstract: A technique for reducing the number of layers in a multilayer circuit board is disclosed. The multilayer circuit board has a plurality of electrically conductive signal layers for routing electrical signals to and from at least one electronic component mounted on a surface of the multilayer circuit board. In one embodiment, the technique is realized by forming a first plurality of electrically conductive vias in the multilayer circuit board extending from the surface of the multilayer circuit board to a first of the plurality of electrically conductive signal layers, wherein the first plurality of electrically conductive vias are arranged so as to form a channel in a second of the plurality of electrically conductive signal layers beneath the first plurality of electrically conductive vias.

Abstract: A printed circuit board includes a signal layer and a supply voltage plane layer. The signal layer includes traces to communicate signals that are not associated with regulated supply voltages. The supply voltage plane is embedded in the signal layer to supply power to multiple supply voltage pins of a component that is mounted to the printed circuit board. The printed circuit board may also include a supply voltage plane layer to communicate a supply voltage. A ground plane may be embedded in the supply voltage plane layer to provide ground connections to multiple pins of the component.

Abstract: A circuit device board having a desired characteristic is provided by bonding dielectric substrates. A printed board 11 carrying patterns 11a and 11b incorporating a resonator is joined by a prepreg 13 to a printed board 12 carrying patterns 12a and 12b, which are substantially identical to the patterns 11a and 11b, so that the patterns come opposite to each other. As a grounding conductor is provided on the outer side of each of the printed boards 11 and 12, a band-pass filter having the three-plate structure is completed. The patterns 11a and 12a are connected to each other for determining the signal input while the patterns 11b and 12b are connected to each other for determining the signal output. Accordingly, the frequency response can be obtained at a desired level regardless of the thickness of the prepreg 13.

Abstract: A package for housing a device (e.g., an integrated circuit chip or die) includes a Faraday cage. The Faraday cage is at least partially formed in the integrated circuit die. The die includes conductive vias and solder balls surrounding a circuit. The package can be a ball grid array (BGA) package or flip chip package. The package substrate can include a ground plane.

Abstract: The present invention relates to a structure for providing an interconnect between layers of a multilayer circuit board. The structure comprises a stack that includes at least one layer and a via opening that extends through at least one layer of the stack. Each individual via opening is filled with a solid conductive plug and each solid conductive plug has a first contact pad and a second contact pad.

Abstract: A wiring lay-out is provided, for electrically connecting a decoupling cap on a front surface of a multilayer printed circuit board (e.g., a motherboard), with a surface-mounted electrical component (e.g., a micro-ball grid array packaged semiconductor device, such as a PC core logic chip set) on the front surface of the printed circuit board. The wiring lay-out includes a wiring portion formed from a copper plane on the front surface of the printed circuit board; this wiring portion, providing electrical connection from one of the balls of the ball grid array to the decoupling cap, is provided only on the front surface of the printed circuit board. In order to provide a route for the wiring between the electrical component and decoupling cap, vias through the printed circuit board are positioned in a row with bonding pads. All decoupling caps on the printed circuit board are provided on the front surface of the printed circuit board.