Having Semiconductive Device Patents (Class 361/783)
  • Patent number: 11017292
    Abstract: Artificial neuron apparatus includes first and second resistive memory cells. The first resistive memory cell is connected in first circuitry having a first input and output. The second resistive memory cell is connected in second circuitry having a second input and output. The first and second circuitry are operable in alternating read and write phases to apply a programming current to their respective memory cells on receipt of excitatory and inhibitory neuron input signals, respectively. During the write phase, resistance of the respective cells is changed in response to successive excitatory and inhibitory neuron input signals. During the read phase, a read current is applied to their respective cells to produce first and second measurement signals, respectively. An output circuit connected to the first and second outputs produces a neuron output signal at a neuron output when a difference between the first and second measurement signals traverses a threshold.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: May 25, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Evangelos S. Eleftheriou, Lukas Kull, Manuel Le Gallo-Bourdeau, Angeliki Pantazi, Abu Sebastian, Tomas Tuma
  • Patent number: 10978366
    Abstract: An object is to provide a power module in which adhesion of a sealing resin is sufficient and which is highly reliable. The power module includes: an insulative board in which a pattern of a conductor layer is formed on a ceramic plate; power semiconductor elements placed on the insulative board; lead frames each in a plate shape connecting from electrodes of the power semiconductor elements to screw-fastening terminal portions; and a sealing resin portion that seals connection portions between the power semiconductor elements and the lead frames, and regions around the connection portions; wherein, in the lead frames, opening portions are formed at positions where each of the lead frames at least partly overlaps, in planar view, with a portion of the insulative board on which the conductor layer is not formed.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: April 13, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Junji Fujino, Yuji Imoto, Shohei Ogawa, Mikio Ishihara
  • Patent number: 10956764
    Abstract: An electronic device according to various embodiments of the present invention comprises: a display panel; a biometric sensor module disposed on the back surface of the display panel; a processor electrically connected to the display panel and the biometric sensor module, and configured to acquire biometric information by using the biometric sensor module; a first adhesive member filling the gap formed between the back surface of the display panel and the biometric sensor module; and a second adhesive member applied on the first adhesive member, wherein the biometric sensor module can be attached to the back surface of the display panel by using the second adhesive member. In addition, other embodiments are possible.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: March 23, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joo Han Kim, Jin Man Kim, Byung Kyu Kim, Jin Woo Park, Young Bae Sim, Yeun Wook Lim
  • Patent number: 10936780
    Abstract: A method of manufacturing an integrated circuit includes identifying a first cell of a layout, placing a first pair of conductive patterns on a first set of routing tracks, placing a second pair of conductive patterns on a second set of routing tracks, and forming, by a first mask, a first set of conductive structures based on the first pair or second pair of conductive patterns. The first cell abuts a second cell. The first cell has a first set of routing tracks. The second cell has a second set of routing tracks. The first and second cell have a same cell height that is a non-integer multiple of a minimum pitch. A top and bottom boundary of the first cell overlaps a pair of the first set of routing tracks. A top and bottom boundary of the second cell overlaps a pair of the second set of routing tracks.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: March 2, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Mahantesh Hanchinal, Chi Wei Hu, Min-Yuan Tsai, Shu-Yi Ying
  • Patent number: 10886254
    Abstract: A solution relating to electronic devices of flip-chip type is provided, which includes at least one chip carrier having a carrier surface, the carrier(s) including one or more contact elements of electrically conductive material on the carrier surface, at least one integrated circuit chip having a chip surface, the chip(s) including one or more terminals of electrically conductive material on the chip surface each one facing a corresponding contact element, solder material soldering each terminal to the corresponding contact element, and a restrain structure around the contact elements for restraining the solder material during a soldering of the terminals to the contact elements. The carrier includes one or more heat dissipation elements of thermally conductive material on the carrier surface facing the chip surface displaced from the terminals, the dissipation elements being free of any solder mask.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: January 5, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stefano Oggioni, Thomas Brunschwiler, Gerd Schlottig
  • Patent number: 10879157
    Abstract: An improved interconnect substrate having high density routings for a chip package assembly, a chip package assembly having a high density substrate, and methods for fabricating the same are provided that utilize substrates having a region of high density routings disposed over a region of low density routings. In one example, a method for fabricating an interconnect substrate is provided that includes forming a high density routing region by depositing a seed layer on a top surface of a low density routing region, patterning a mask layer on the seed layer, forming a plurality of conductive posts on the seed layer, removing the mask layer and the seed layer exposed between the conductive posts, and depositing a dielectric layer between the between the conductive posts, wherein at least some of the conductive posts are electrically coupled to conductive routing comprising the low density routing region.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: December 29, 2020
    Assignee: XILINX, INC.
    Inventor: Jaspreet Singh Gandhi
  • Patent number: 10861741
    Abstract: Electronic packages and related methods are disclosed. An example electronic package apparatus includes a substrate and an electronic component. A protective material is positioned on a first surface, a second surface and all side surfaces of the electronic component to encase the electronic component. An enclosure is coupled to the substrate to cover the protective material and the electronic component.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: December 8, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kurt Peter Wachtler, Anindya Poddar, Usman Mahmood Chaudhry
  • Patent number: 10847435
    Abstract: A method of fabricating a semiconductor package structure is provided. The structure is configured to include a base substrate, a die disposed on the base substrate, the die including a semiconductor device, a solder bump disposed on a surface of the die, and configured to discharge heat generated in the die to an outside; and a solder ball disposed on another surface, opposite to the surface, of the die, and configured to transmit a signal, which is produced by the semiconductor device of the die, to an external device.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: November 24, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Youngho Kim, Hwanpil Park
  • Patent number: 10818568
    Abstract: A charger comprises a housing, a first multi-layer printed circuit board (PCB), a second multi-layer PCB, and a third multi-layer PCB. The first PCB comprises at least a portion of a primary side circuit. The second PCB comprises at least a portion of a secondary side circuit. The third PCB is perpendicular to the first PCB and the second PCB. An isolation coupling element is disposed on the third PCB. The isolation coupling element comprises a multi-layer PCB. The first PCB comprises a high voltage (HV) semiconductor package. A surface of a die paddle of the HV semiconductor package is exposed from a molding encapsulation of the HV semiconductor package.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: October 27, 2020
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.
    Inventors: Pei-Lun Huang, Yu-Ming Chen, Tien-Chi Lin, Jung-Pei Cheng, Yueh-Ping Yu, Zhi-Qiang Niu, Xiaotian Zhang, Long-Ching Wang
  • Patent number: 10797020
    Abstract: A semiconductor device assembly is provided. The assembly comprises a package substrate, a first stack of semiconductor dies having a first set of planform dimensions disposed over a first location on the substrate, a second stack of semiconductor dies having a second set of planform dimensions different from the first set disposed over a second location on the substrate, and an encapsulant at least partially encapsulating the substrate, the first stack and the second stack. The first stack of semiconductor dies has a first planform area, the second stack of semiconductor dies has a second planform area, and a sum of the first and second planform areas can be at least 50%, 67%, 75%, or even more of an area of the package substrate.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: October 6, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Blaine J. Thurgood
  • Patent number: 10782318
    Abstract: A testing probe structure for wafer level testing semiconductor IC packaged devices under test (DUT). The structure includes a substrate, through substrate vias, a bump array formed on a first surface of the substrate for engaging a probe card, and at least one probing unit on a second surface of the substrate. The probing unit includes a conductive probe pad formed on one surface of the substrate and at least one microbump interconnected to the pad. The pads are electrically coupled to the bump array through the vias. Some embodiments include a plurality of microbumps associated with the pad which are configured to engage a mating array of microbumps on the DUT. In some embodiments, the DUT may be probed by applying test signals from a probe card through the bump and microbump arrays without direct probing of the DUT microbumps.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: September 22, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mill-Jer Wang, Ching-Fang Chen, Sandeep Kumar Goel, Chung-Sheng Yuan, Chao-Yang Yeh, Chin-Chou Liu, Yun-Han Lee, Hung-Chih Lin
  • Patent number: 10756012
    Abstract: A circuit assembly is provided. The circuit assembly includes: a first bus bar and a second bus bar that are part of a power circuit; and a control board to which a control circuit configured to control current flow in the power circuit is mounted, the circuit assembly including: a semiconductor switching element including a drain terminal and a source terminal that are connected to the first bus bar and the second bus bar, respectively, and a gate terminal configured to receive input of a control signal from the control circuit configured to control current flow in the power circuit; and a third bus bar configured to electrically connect the gate terminal and the control board.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: August 25, 2020
    Assignees: AutoNetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventors: Yuuichi Hattori, Yoshikazu Sasaki, Jun Ikeda
  • Patent number: 10716215
    Abstract: A display device includes a display substrate with a display area, a first peripheral area, and a second peripheral area, the display area having first and second sides extending in directions crossing each other, the first peripheral area adjacent to the first side, and the second peripheral area adjacent to the second side, a first driving substrate attached to the first peripheral area, the first driving substrate including a first driving circuit portion and a first link wire connected to the first driving circuit portion, a second driving substrate attached to the second peripheral area, the second driving substrate including a second driving circuit portion and a second link wire connected to the second driving circuit portion, and a flexible circuit board attached to the first driving substrate, the flexible circuit board including a third link wire connected to the first and second link wires.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: July 14, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventor: Sang Woo Kim
  • Patent number: 10535622
    Abstract: A substrate structure includes a first portion, a second portion, and an intermedia portion disposed between the first and the second portion and the electrically connected business. The first portion includes a first fine redistribution layer (RDL) and a first coarse RDL. The first coarse RDL includes a first coarse conductive pattern, electrically connected to the first fine conductive pattern, where a, the first coarse RDL includes a first coarse conductive pattern Layout density of the first fine conductive pattern is denser than that of the first coarse conductive pattern. The second portion includes at least one of a second fine RDL and a second coarse RDL. An electronic device including a substrate structure is also provided.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: January 14, 2020
    Inventor: Dyi-Chung Hu
  • Patent number: 10485111
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to via and skip via structures and methods of manufacture. The method includes: forming a first metallization layer with a first capping layer over the first metallization layer; forming a second metallization layer with a second capping layer over the second metallization layer; forming a partial skip via structure to the first metallization layer by removing a portion of the first capping layer and the second capping and depositing conductive material in an opening formed in the second metallization layer; forming a third capping layer over the filled partial skip via and the second capping layer; and forming a remaining portion of a skip via structure in alignment with the partial skip via structure by opening the third capping layer to expose the conductive material of the partial skip via.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: November 19, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Shao Beng Law, Nicholas V. LiCausi, Errol Todd Ryan, James McMahon, Ryan S. Smith, Xunyuan Zhang
  • Patent number: 10477671
    Abstract: There is provided a laminated body capable of lowering thermal resistance and capable of suppressing peeling off after a cooling/heating cycle. The laminated body according to the present invention includes an insulating resin layer, a first metal material being a metal foil or a metal plate, and a second metal material being a metal foil or a metal plate, the first metal material is layered on a first surface of the insulating resin layer and the second metal material is layered on a second surface opposite to the first surface of the insulating resin layer, the thickness of the insulating resin layer is 200 ?m or less, the total thickness of the first metal material and the second metal material is 200 ?m or more, the ratio of the thickness of the first metal material to the thickness of the second metal material is 0.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: November 12, 2019
    Assignee: SEKISUI CHEMICAL CO., LTD.
    Inventors: Hiroshi Maenaka, Osamu Inui
  • Patent number: 10475764
    Abstract: A method includes bringing into contact respective first sides of a plurality of dies and a die attach film on a major surface of a carrier wafer, and simultaneously heating portions of the die attach film contacting the plurality of dies in order to simultaneously bond the plurality of dies to the die attach film.
    Type: Grant
    Filed: April 14, 2015
    Date of Patent: November 12, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Shing-Chao Chen, Chung-Shi Liu, Ming-Da Cheng
  • Patent number: 10448513
    Abstract: A display device includes a display substrate with a display area, a first peripheral area, and a second peripheral area, the display area having first and second sides extending in directions crossing each other, the first peripheral area adjacent to the first side, and the second peripheral area adjacent to the second side, a first driving substrate attached to the first peripheral area, the first driving substrate including a first driving circuit portion and a first link wire connected to the first driving circuit portion, a second driving substrate attached to the second peripheral area, the second driving substrate including a second driving circuit portion and a second link wire connected to the second driving circuit portion, and a flexible circuit board attached to the first driving substrate, the flexible circuit board including a third link wire connected to the first and second link wires.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: October 15, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Sang Woo Kim
  • Patent number: 10423878
    Abstract: Artificial neuron apparatus includes first and second resistive memory cells. The first resistive memory cell is connected in first circuitry having a first input and output. The second resistive memory cell is connected in second circuitry having a second input and output. The first and second circuitry are operable in alternating read and write phases to apply a programming current to their respective memory cells on receipt of excitatory and inhibitory neuron input signals, respectively. During the write phase, resistance of the respective cells is changed in response to successive excitatory and inhibitory neuron input signals. During the read phase, a read current is applied to their respective cells to produce first and second measurement signals, respectively. An output circuit connected to the first and second outputs produces a neuron output signal at a neuron output when a difference between the first and second measurement signals traverses a threshold.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: September 24, 2019
    Assignee: International Business Machines Corporation
    Inventors: Evangelos S. Eleftheriou, Lukas Kull, Manuel Le Gallo-Bourdeau, Angeliki Pantazi, Abu Sebastian, Tomas Tuma
  • Patent number: 10423016
    Abstract: A modulator drive circuit, including: a first transistor having: a first output terminal connected to a first reference voltage, a second output terminal connected to a first output terminal of the modulator drive circuit, and a control terminal; and a second transistor having: a first output terminal connected to a second reference voltage different from the first reference voltage, a second output terminal connected to the first output terminal of the modulator drive circuit, and a control terminal.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: September 24, 2019
    Assignee: Rockley Photonics Limited
    Inventor: David Arlo Nelson
  • Patent number: 10418308
    Abstract: A system includes a heat sink, a semiconductor device, a layer of thermal interface material (TIM) disposed between the heat sink and the semiconductor device, and a fastener system that couples the semiconductor device, the layer of TIM, and the heat sink together. The TIM may facilitate dissipation of heat generated by the semiconductor device via the heat sink during operation of the semiconductor device. The fastener system includes a first Belleville-type washer configured to cooperate with the TIM, which flows when heated beyond a threshold temperature, to maintain a substantially constant coupling force between the semiconductor device and the heat sink during operation of the semiconductor device.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: September 17, 2019
    Assignee: Rockwell Automation Technologies, Inc.
    Inventors: Paul Jerome Grosskreuz, Rui Zhou, Kelly James Bronk, Jeremiah John Kopiness
  • Patent number: 10412830
    Abstract: According to an aspect of the present inventive concept there is provided a system comprising: a conductive textile including conductive fibers, an electronic circuit unit arranged on a first main surface of the conductive textile and including circuitry and a carrier supporting the circuitry, the carrier having a first main surface and a second main surface facing the first main surface of the textile and including a through-hole extending from the first main surface to the second main surface, a conductive pin including an leg segment arranged at least partly in the through-hole, and a grip segment arranged to grip about at least one fiber of the conductive textile. There is also provided a method for mounting an electronic circuit unit on a conductive textile.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: September 10, 2019
    Assignee: IMEC VZW
    Inventors: Riet Labie, Frederic Duflos
  • Patent number: 10276719
    Abstract: In a method of manufacturing a semiconductor device, an opening is formed in an interlayer dielectric layer such that a source/drain region is exposed in the opening. A first semiconductor layer is formed to fully cover the exposed source/drain region within the opening. A heating process is performed to make an upper surface of the first semiconductor layer substantially flat. A conductive contact layer is formed over the first semiconductor layer.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Blandine Duriez, Gerben Doornbos, Mark Van Dal, Martin Christopher Holland
  • Patent number: 10262946
    Abstract: A wiring substrate includes a first wiring structure and a second wiring structure having a higher wiring density. The second wiring structure includes a wiring layer formed on a first insulation layer of the first wiring structure. The wiring layer includes a first wiring pattern, the upper surface of which includes smooth and rough surfaces. A protective film, formed from a conductive material having a higher migration resistance than the wiring layer, covers only the smooth surface and includes a smooth upper surface. A second insulation layer stacked on the first insulation layer covers the wiring layer and the protective film. The smooth surface is continuous with and downwardly recessed from the smooth surface to expose a peripheral portion of the protective film. The second insulation layer covers upper, lower, and side surfaces of the peripheral portion.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: April 16, 2019
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Yusuke Gozu, Yuta Sakaguchi, Norikazu Nakamura, Noriyoshi Shimizu
  • Patent number: 10245682
    Abstract: A method of removing material from a surface, which includes the steps of providing a base layer, at least one layer attached to the base layer, an intermediate finish surface, and a bonding interface surface. The intermediate finish surface is formed by removing the at least one layer and a portion of the base layer during a material removal process. The bonding interface surface is formed by a polishing process applied to the intermediate finish surface. There is an oxidation layer which is part of the base layer, as well as a mold release layer and a contamination layer, both of which are part of the at least one layer. The material removal process involves laser etching the at least one layer to create the intermediate finish surface, and the polishing process includes applying a second laser etching to the intermediate finish surface, forming the bonding interface surface.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: April 2, 2019
    Assignee: Continental Automotive Systems, Inc.
    Inventors: Jared Yagoda, Dana Gradler
  • Patent number: 10147707
    Abstract: A semiconductor device includes a first and a second metal layer, the second provided on a same plane as the first layer, and first second and third terminals. A first metal wiring layer is electrically connected to the first terminal. A second metal wiring layer is electrically connected to the second terminal and the second metal layer and disposed over the first metal wiring layer. A third metal wiring layer is electrically connected to the third terminal and the first metal layer. A first semiconductor chip is provided between the first metal wiring layer and the first metal layer. A second semiconductor chip is provided between the third metal wiring layer and the second metal layer. The first chip has electrodes connected to the first metal wiring layer and the first metal layer. The second chip has electrodes connected to the third metal wiring layer and the second metal layer.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: December 4, 2018
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Tatsuo Tonedachi
  • Patent number: 10117335
    Abstract: A power module includes a power semiconductor device, and a chip component arranged on first and second circuit patterns that are electrically connected to the power semiconductor device, and arranged so as to bridge the first and second circuit patterns. The chip component is arranged so that first and second electrodes are respectively positioned on the first and second circuit patterns, and the first and second electrodes and the first and second circuit patterns are respectively joined with solder layers. Between a lower surface of the chip component and the first circuit pattern and between the lower surface of the chip component and the second circuit pattern, two spacers are provided in parallel with each other respectively at positions close to the first and second electrodes. The solder layers do not exist on an inner side of the two spacers in parallel with each other.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: October 30, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takuya Takahashi, Yasutaka Shimizu
  • Patent number: 10111333
    Abstract: An embodiment of a power-supply module includes a molded package, power-supply components disposed within the package, and an inductor disposed within the package and over the power-supply components. For example, for a given output-power rating, such a power-supply module may be smaller, more efficient, and more reliable than, and may run cooler than, a power-supply module having the inductor mounted outside of the package or side-by-side with other components. And for a given size, such a module may have a higher output-power rating than a module having the inductor mounted outside of the package or side-by-side with other components.
    Type: Grant
    Filed: March 7, 2011
    Date of Patent: October 23, 2018
    Assignee: INTERSIL AMERICAS INC.
    Inventors: Jian Yin, Matthew Harris
  • Patent number: 10077359
    Abstract: The embodiments relate to a polymerizable thermoset composition having improved flame retardant properties, a polymerized thermoset having improved flame retardant properties, a process for manufacturing the polymerized thermoset, and use of the polymerizable thermoset composition to produce lightweight construction components, preferably carbon fiber composites (CFRP), and a lightweight construction component, preferably carbon fiber composite (CFRP), containing the polymerized thermoset.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: September 18, 2018
    Assignee: AIRBUS DEFENCE AND SPACE GMBH
    Inventors: Christoph Meier, Patricia Parlevliet, Manfred Doering
  • Patent number: 10037981
    Abstract: A display system is disclosed. The display system comprises a light emitting diode (LED) device and a backplane (BP) device. The LED device comprises a plurality of LEDs having LED terminals. An LED bonding surface comprising a dielectric layer with LED bonding surface contact pads is coupled to diode terminals of the LEDs. The backplane (BP) device comprises a BP substrate having top and bottom surfaces. A plurality of system on chip (SoC) chips are bonded to chip pads disposed on a bottom surface of the BP device. The SoC chips are electrically coupled to the CMOS components of the BP device and LEDs of the LED device.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: July 31, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Srinivasa Banna, Sanjay Jha, Deepak Nayak, Ajey P. Jacob
  • Patent number: 10026720
    Abstract: An integrated circuit package including a substrate having a cavity and one or more semiconductor devices assembled within the cavity of the substrate. The one or more semiconductor devices electrically coupled using redistribution layers, wherein the cavity is a first cavity, the substrate includes the first cavity and a second cavity, the one or more semiconductor devices are fully embedded within the first cavity of the substrate, the one or more semiconductor devices are fully embedded between the substrate and a first redistribution layer of said redistribution layers, bumps are fully embedded within the second cavity of the substrate, the bumps are fully embedded between the substrate and the first redistribution layer of said redistribution layers, and the first redistribution layer is fully embedded between the substrate and a semiconductor interposer.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: July 17, 2018
    Assignee: BroadPak Corporation
    Inventor: Farhang Yazdani
  • Patent number: 9960133
    Abstract: An integrated circuit package includes a die. An electrically conductive layer comprises a redistribution layer (RDL) in the die, or a micro-bump layer above the die, or both. The micro bump layer comprises at least one micro-bump line. A filter comprises the electrically conductive layer. A capacitor comprises an electrode formed in the electrically conductive layer.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: May 1, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiao-Tsung Yen, Jhe-Ching Lu, Yu-Ling Lin, Chin-Wei Kuo, Min-Chie Jeng
  • Patent number: 9944766
    Abstract: A prepreg includes a fiber base material and a thermosetting resin composition impregnated into the fiber base material. The thermosetting resin composition contains a thermosetting resin including an epoxy resin; a curing agent; an inorganic filler; and an acrylic acid ester copolymer having a weight average molecular weight of 10×104 or more and less than 45×104. A content of the inorganic filler is 150 parts by mass or more relative to a total of 100 parts by mass of the thermosetting resin and the curing agent. A content of the acrylic acid ester copolymer is more than 30 parts by mass and 90 parts by mass or less relative to the total of 100 parts by mass of the thermosetting resin and the curing agent.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: April 17, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Masaaki Matsumoto, Takatoshi Mito, Tatuo Yonemoto
  • Patent number: 9922921
    Abstract: A semiconductor package includes: a semiconductor chip including an effective chip region at a center of the semiconductor chip and in which pads connected to chip wirings are formed, and a dummy chip region at a side of the effective chip region and in which pads not connected to the chip wirings are formed; a base film including a chip mounting section on which the semiconductor chip is mounted; and a plurality of wiring patterns disposed on the base film and electrically connected to the chip wirings of the semiconductor chip, wherein first wiring patterns, which are a part of the plurality of wiring patterns, extend on a first region of the chip mounting section corresponding to the dummy chip region.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: March 20, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-min Jung, Na-rae Shin
  • Patent number: 9902880
    Abstract: A film material includes a substrate and a film layer arranged on one main surface of the substrate. The film layer contains a fibrous first resin and a thermosetting second resin in an uncured or semi-cured state, and a linear expansion coefficient CF of the first resin is smaller than a linear expansion coefficient CR of the second resin in cured state.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: February 27, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Koji Motomura
  • Patent number: 9872394
    Abstract: A method for filling vias with metal includes receiving a substrate having vias, forming a metal plating layer over the vias on a first side of the substrate, fill-plating the vias with a first metal beginning with the metal plating layer on the first side of the substrate and advancing to a second side of the substrate to provide filled vias. The metal plating layer may be subsequently patterned to provide selected circuit connections or chemically-mechanically polished to completely remove the metal plating layer. Forming a metal plating layer over the vias may include filling the vias with a sacrificial filler to enable formation of the metal plating layer and subsequently removing the sacrificial filler via an etching operation or the like. In other embodiments, forming the metal plating layer over the vias is accomplished by bonding a metallic layer onto the first side of the substrate.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: January 16, 2018
    Assignee: International Business Machines Corporation
    Inventors: Steven A. Cordes, Bing Dang, Sung K. Kang, Yu Luo, Peter J. Sorce
  • Patent number: 9831776
    Abstract: An apparatus that includes a resonant DC-DC converter with switching frequencies based on stray inductances of the physical components used to construct the apparatus. This results in a relatively high efficiency and high density DC-DC converter that, in some implementations, does not require a discrete inductor component.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: November 28, 2017
    Assignee: Google Inc.
    Inventors: Shuai Jiang, Xin Li
  • Patent number: 9706660
    Abstract: A solar junction box includes a housing having a base and walls defining a cavity. The base has an opening configured to receive a conductive foil. A power cable is held in the housing having a power terminal terminated to an end of the power cable positioned within the housing. An electronic module is removably received in the cavity. The electronic module has a circuit board including electronic components mounted to the circuit board, a foil contact configured to be removably coupled to the foil, and a power contact configured to be removably coupled to the power terminal. The circuit board has a power circuit electrically connecting the foil contact and the power contact.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: July 11, 2017
    Assignees: TE Connectivity Corporation, Tyco Electronics UK Ltd.
    Inventors: Matthew Edward Mostoller, Subhash Mungarwadi
  • Patent number: 9627496
    Abstract: A semiconductor device includes a two-input NOR circuit including four MOS transistors arranged in a line. Each of the MOS transistors is disposed on a planar silicon layer disposed on a substrate. The drain, gate, and source of the MOS transistor are arranged in the vertical direction. The gate surrounds a silicon pillar. The planar silicon layer is constituted by a first activation region of a first conductivity type and a second activation region of a second conductivity type. The first and second activation regions are connected to each other via a silicon layer disposed on a surface of the planar silicon layer, so as to form a NOR circuit having a small area.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: April 18, 2017
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Masamichi Asano
  • Patent number: 9514076
    Abstract: An information handling system is set forth which includes a fully connected 4S topology that can also be populated with two processors and two link modules (e.g., two passive “slugs”) to implement a fully connected 2S topology. More specifically, the link module is a printed circuit board that implements a loopback connection between certain links of the architecture. In certain embodiment, the link module includes no electrical components. The link module merely includes a set of electrical connections (e.g., copper traces) connecting pads (e.g., gold plated pads) on a thick printed circuit board (PCB) dielectric material that is shaped to fit the processor socket. The link module is used to carry user data when the information handling system is configured in a 2S topology. The link module includes proper lane assignment that allows the module to be passive without performance reduction.
    Type: Grant
    Filed: June 2, 2008
    Date of Patent: December 6, 2016
    Assignee: Dell Products L.P.
    Inventors: Sandor T. Farkas, Fernando Meschino, Thomas Edwin Garvens, Michael Jon Roberts, Scott Michael Ramsey, Charles L. Haley
  • Patent number: 9502344
    Abstract: Wafer level packaged semiconductor device with enhanced heat dissipation properties. The semiconductor device includes a top and a bottom face and at least one metal pad is positioned on the top and the bottom faces. A top cover is affixed to the top face of the semiconductor device and a bottom cover is affixed to the bottom face of the semiconductor device. Vias extend through the top and bottom covers and an electroplated metal layer extends from an external face of the covers, through the visas to the metal pads on the semiconductor device.
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: November 22, 2016
    Inventor: Mordechai Margalit
  • Patent number: 9478489
    Abstract: The width of scribe lines may be reduced in semiconductor devices by applying a process technique in which trenches may be formed first from the rear side on the basis of a required width of the corresponding trenches, while subsequently it may be cut into the substrate from the front side on the basis of a reduced thickness of the corresponding saw blades, thereby also enabling a reduction of the scribe line width. Furthermore, contamination of the front side, i.e., of the metallization system, may be reduced, for instance, by performing an optional intermediate cleaning process.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: October 25, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Daniel Richter, Frank Kuechenmeister
  • Patent number: 9462696
    Abstract: The invention relates to a circuit module (10) having a circuit carrier (12), at least one circuit (14) mounted on the circuit carrier (12), encapsulated by a protective material (16), and at least one electrical/electronic component (18) encapsulated by a protective coating (20), protecting the at least one electrical/electronic component (18) from the protective material (16), and to a method for producing the circuit module (10). According to the invention, the protective coating (20) protecting the at least one electrical/electronic component (18) is only partially encapsulated by the protective material (16).
    Type: Grant
    Filed: December 7, 2010
    Date of Patent: October 4, 2016
    Assignee: Robert Bosch GmbH
    Inventors: Stephan Mazingue-Desailly, Michael Mueller
  • Patent number: 9449937
    Abstract: There is provided a semiconductor device. The semiconductor device of the present invention includes a semiconductor element and a metal buffer layer in an electrical connection to the semiconductor element. The metal buffer layer and the semiconductor element are in a connection with each other by mutual surface contact of the metal buffer layer and the semiconductor element. The metal buffer layer is an external connection terminal used for a mounting with respect to a secondary mount substrate, and the metal buffer layer serves as a buffer part having a stress-relaxation effect between the semiconductor element and the secondary mount substrate.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: September 20, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Koji Kawakita, Susumu Sawada, Seiichi Nakatani, Yoshihisa Yamashita
  • Patent number: 9433101
    Abstract: A method for filling vias with metal includes receiving a substrate having vias, forming a metal plating layer over the vias on a first side of the substrate, fill-plating the vias with a first metal beginning with the metal plating layer on the first side of the substrate and advancing to a second side of the substrate to provide filled vias. The metal plating layer may be subsequently patterned to provide selected circuit connections or chemically-mechanically polished to completely remove the metal plating layer. Forming a metal plating layer over the vias may include filling the vias with a sacrificial filler to enable formation of the metal plating layer and subsequently removing the sacrificial filler via an etching operation or the like. In other embodiments, forming the metal plating layer over the vias is accomplished by bonding a metallic layer onto the first side of the substrate.
    Type: Grant
    Filed: October 16, 2014
    Date of Patent: August 30, 2016
    Assignee: International Business Machines Corporation
    Inventors: Steven A. Cordes, Bing Dang, Sung K. Kang, Yu Luo, Peter J. Sorce
  • Patent number: 9425166
    Abstract: A GOA layout method, an array substrate and a display device are provided. The array substrate includes a plurality of GOA unit groups, each of which includes two adjacent GOA units. The plurality of GOA unit groups includes a first GOA unit group, two GOA units of the first GOA unit group have an overlapping region with at least one via hole provided therein, and the two GOA units of the first GOA unit group are electrically connected through the at least one via hole. With the array substrate, the density of gate lines can be increased.
    Type: Grant
    Filed: October 20, 2014
    Date of Patent: August 23, 2016
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Song Song, Kazuyoshi Nagayama
  • Patent number: 9412674
    Abstract: An integrated circuit includes a die having a conductive layer. The conductive layer includes a data wire, a first power supply wire of a first voltage potential, and a second power supply wire of a second voltage potential different from the first voltage potential. A segment of the data wire is located between, and substantially parallel to, a segment of the first power supply wire and a segment of the second power supply wire. Further, the first power supply wire is coupled to a first probe structure; and, the second power supply wire is coupled to a second probe structure.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: August 9, 2016
    Assignee: XILINX, INC.
    Inventors: Myongseob Kim, Henley Liu, Cheang-Whang Chang, Sanjiv Stokes
  • Patent number: 9391026
    Abstract: Package substrate, semiconductor packages and methods for forming a semiconductor package are presented. The package substrate includes a base substrate having first and second major surfaces and a plurality of via contacts extending through the first to the second major surfaces of the base substrate. A first conductive layer having a plurality of openings is disposed over the first surface of the base substrate and via contacts. The openings are configured to match conductive trace layout of the package substrate. Conductive traces are disposed over the first conductive layer. The conductive traces are directly coupled to the via contacts through some of the openings of the first conductive layer.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: July 12, 2016
    Assignee: UTAC HEADQUARTERS PTE. LTD.
    Inventor: Chuen Khiang Wang
  • Patent number: 9385103
    Abstract: A method for manufacturing a semiconductor device, includes preparing a solder, a soldering article, a base material, a weight having a foot where a center of gravity of the weight is shifted from a center of the soldering article, a positioning jig having a hole for holding the soldering article in the base material, and a dam member; disposing the dam member on a side having a relatively lower height due to a warp of an edge portion of the base material; placing the positioning jig on a principal surface of the base material; placing the soldering article on the solder in the hole; placing the weight on an upper surface of the soldering article to position the center of gravity on the side having relatively lower height; and raising the temperature of the solder to a temperature equal to or higher than the melting point of the solder.
    Type: Grant
    Filed: April 11, 2014
    Date of Patent: July 5, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Shinji Sano, Tatsuo Nishizawa
  • Patent number: 9368890
    Abstract: An electrical connector assembly essentially consists of four connector units neighboring with one another each occupying a quadrant in a square manner so that each connector units defines two unexposed neighboring sides and two exposed outer sides. Each connector unit includes an insulative housing with a plurality of passageways to receive the corresponding contacts therein. A vertically and horizontally staggered structure is formed on each neighboring side of the housing. A pair of inner interengaging structures and a pair of outer neighboring structures are respectively formed on two opposite ends of the corresponding neighboring sides of the neighboring connector units so as to allow the neighboring connector units to be assembled in a pivotal way with the pair of outer interengaging structures as a fulcrum.
    Type: Grant
    Filed: July 1, 2015
    Date of Patent: June 14, 2016
    Assignee: FOXCONN INTERCONNECT TECHNOLOGY LIMITED
    Inventor: Fang-Jwu Liao