Having Semiconductive Device Patents (Class 361/783)
  • Patent number: 10423016
    Abstract: A modulator drive circuit, including: a first transistor having: a first output terminal connected to a first reference voltage, a second output terminal connected to a first output terminal of the modulator drive circuit, and a control terminal; and a second transistor having: a first output terminal connected to a second reference voltage different from the first reference voltage, a second output terminal connected to the first output terminal of the modulator drive circuit, and a control terminal.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: September 24, 2019
    Assignee: Rockley Photonics Limited
    Inventor: David Arlo Nelson
  • Patent number: 10423878
    Abstract: Artificial neuron apparatus includes first and second resistive memory cells. The first resistive memory cell is connected in first circuitry having a first input and output. The second resistive memory cell is connected in second circuitry having a second input and output. The first and second circuitry are operable in alternating read and write phases to apply a programming current to their respective memory cells on receipt of excitatory and inhibitory neuron input signals, respectively. During the write phase, resistance of the respective cells is changed in response to successive excitatory and inhibitory neuron input signals. During the read phase, a read current is applied to their respective cells to produce first and second measurement signals, respectively. An output circuit connected to the first and second outputs produces a neuron output signal at a neuron output when a difference between the first and second measurement signals traverses a threshold.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: September 24, 2019
    Assignee: International Business Machines Corporation
    Inventors: Evangelos S. Eleftheriou, Lukas Kull, Manuel Le Gallo-Bourdeau, Angeliki Pantazi, Abu Sebastian, Tomas Tuma
  • Patent number: 10418308
    Abstract: A system includes a heat sink, a semiconductor device, a layer of thermal interface material (TIM) disposed between the heat sink and the semiconductor device, and a fastener system that couples the semiconductor device, the layer of TIM, and the heat sink together. The TIM may facilitate dissipation of heat generated by the semiconductor device via the heat sink during operation of the semiconductor device. The fastener system includes a first Belleville-type washer configured to cooperate with the TIM, which flows when heated beyond a threshold temperature, to maintain a substantially constant coupling force between the semiconductor device and the heat sink during operation of the semiconductor device.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: September 17, 2019
    Assignee: Rockwell Automation Technologies, Inc.
    Inventors: Paul Jerome Grosskreuz, Rui Zhou, Kelly James Bronk, Jeremiah John Kopiness
  • Patent number: 10412830
    Abstract: According to an aspect of the present inventive concept there is provided a system comprising: a conductive textile including conductive fibers, an electronic circuit unit arranged on a first main surface of the conductive textile and including circuitry and a carrier supporting the circuitry, the carrier having a first main surface and a second main surface facing the first main surface of the textile and including a through-hole extending from the first main surface to the second main surface, a conductive pin including an leg segment arranged at least partly in the through-hole, and a grip segment arranged to grip about at least one fiber of the conductive textile. There is also provided a method for mounting an electronic circuit unit on a conductive textile.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: September 10, 2019
    Assignee: IMEC VZW
    Inventors: Riet Labie, Frederic Duflos
  • Patent number: 10276719
    Abstract: In a method of manufacturing a semiconductor device, an opening is formed in an interlayer dielectric layer such that a source/drain region is exposed in the opening. A first semiconductor layer is formed to fully cover the exposed source/drain region within the opening. A heating process is performed to make an upper surface of the first semiconductor layer substantially flat. A conductive contact layer is formed over the first semiconductor layer.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Blandine Duriez, Gerben Doornbos, Mark Van Dal, Martin Christopher Holland
  • Patent number: 10262946
    Abstract: A wiring substrate includes a first wiring structure and a second wiring structure having a higher wiring density. The second wiring structure includes a wiring layer formed on a first insulation layer of the first wiring structure. The wiring layer includes a first wiring pattern, the upper surface of which includes smooth and rough surfaces. A protective film, formed from a conductive material having a higher migration resistance than the wiring layer, covers only the smooth surface and includes a smooth upper surface. A second insulation layer stacked on the first insulation layer covers the wiring layer and the protective film. The smooth surface is continuous with and downwardly recessed from the smooth surface to expose a peripheral portion of the protective film. The second insulation layer covers upper, lower, and side surfaces of the peripheral portion.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: April 16, 2019
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Yusuke Gozu, Yuta Sakaguchi, Norikazu Nakamura, Noriyoshi Shimizu
  • Patent number: 10245682
    Abstract: A method of removing material from a surface, which includes the steps of providing a base layer, at least one layer attached to the base layer, an intermediate finish surface, and a bonding interface surface. The intermediate finish surface is formed by removing the at least one layer and a portion of the base layer during a material removal process. The bonding interface surface is formed by a polishing process applied to the intermediate finish surface. There is an oxidation layer which is part of the base layer, as well as a mold release layer and a contamination layer, both of which are part of the at least one layer. The material removal process involves laser etching the at least one layer to create the intermediate finish surface, and the polishing process includes applying a second laser etching to the intermediate finish surface, forming the bonding interface surface.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: April 2, 2019
    Assignee: Continental Automotive Systems, Inc.
    Inventors: Jared Yagoda, Dana Gradler
  • Patent number: 10147707
    Abstract: A semiconductor device includes a first and a second metal layer, the second provided on a same plane as the first layer, and first second and third terminals. A first metal wiring layer is electrically connected to the first terminal. A second metal wiring layer is electrically connected to the second terminal and the second metal layer and disposed over the first metal wiring layer. A third metal wiring layer is electrically connected to the third terminal and the first metal layer. A first semiconductor chip is provided between the first metal wiring layer and the first metal layer. A second semiconductor chip is provided between the third metal wiring layer and the second metal layer. The first chip has electrodes connected to the first metal wiring layer and the first metal layer. The second chip has electrodes connected to the third metal wiring layer and the second metal layer.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: December 4, 2018
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Tatsuo Tonedachi
  • Patent number: 10117335
    Abstract: A power module includes a power semiconductor device, and a chip component arranged on first and second circuit patterns that are electrically connected to the power semiconductor device, and arranged so as to bridge the first and second circuit patterns. The chip component is arranged so that first and second electrodes are respectively positioned on the first and second circuit patterns, and the first and second electrodes and the first and second circuit patterns are respectively joined with solder layers. Between a lower surface of the chip component and the first circuit pattern and between the lower surface of the chip component and the second circuit pattern, two spacers are provided in parallel with each other respectively at positions close to the first and second electrodes. The solder layers do not exist on an inner side of the two spacers in parallel with each other.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: October 30, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takuya Takahashi, Yasutaka Shimizu
  • Patent number: 10111333
    Abstract: An embodiment of a power-supply module includes a molded package, power-supply components disposed within the package, and an inductor disposed within the package and over the power-supply components. For example, for a given output-power rating, such a power-supply module may be smaller, more efficient, and more reliable than, and may run cooler than, a power-supply module having the inductor mounted outside of the package or side-by-side with other components. And for a given size, such a module may have a higher output-power rating than a module having the inductor mounted outside of the package or side-by-side with other components.
    Type: Grant
    Filed: March 7, 2011
    Date of Patent: October 23, 2018
    Assignee: INTERSIL AMERICAS INC.
    Inventors: Jian Yin, Matthew Harris
  • Patent number: 10077359
    Abstract: The embodiments relate to a polymerizable thermoset composition having improved flame retardant properties, a polymerized thermoset having improved flame retardant properties, a process for manufacturing the polymerized thermoset, and use of the polymerizable thermoset composition to produce lightweight construction components, preferably carbon fiber composites (CFRP), and a lightweight construction component, preferably carbon fiber composite (CFRP), containing the polymerized thermoset.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: September 18, 2018
    Assignee: AIRBUS DEFENCE AND SPACE GMBH
    Inventors: Christoph Meier, Patricia Parlevliet, Manfred Doering
  • Patent number: 10037981
    Abstract: A display system is disclosed. The display system comprises a light emitting diode (LED) device and a backplane (BP) device. The LED device comprises a plurality of LEDs having LED terminals. An LED bonding surface comprising a dielectric layer with LED bonding surface contact pads is coupled to diode terminals of the LEDs. The backplane (BP) device comprises a BP substrate having top and bottom surfaces. A plurality of system on chip (SoC) chips are bonded to chip pads disposed on a bottom surface of the BP device. The SoC chips are electrically coupled to the CMOS components of the BP device and LEDs of the LED device.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: July 31, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Srinivasa Banna, Sanjay Jha, Deepak Nayak, Ajey P. Jacob
  • Patent number: 10026720
    Abstract: An integrated circuit package including a substrate having a cavity and one or more semiconductor devices assembled within the cavity of the substrate. The one or more semiconductor devices electrically coupled using redistribution layers, wherein the cavity is a first cavity, the substrate includes the first cavity and a second cavity, the one or more semiconductor devices are fully embedded within the first cavity of the substrate, the one or more semiconductor devices are fully embedded between the substrate and a first redistribution layer of said redistribution layers, bumps are fully embedded within the second cavity of the substrate, the bumps are fully embedded between the substrate and the first redistribution layer of said redistribution layers, and the first redistribution layer is fully embedded between the substrate and a semiconductor interposer.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: July 17, 2018
    Assignee: BroadPak Corporation
    Inventor: Farhang Yazdani
  • Patent number: 9960133
    Abstract: An integrated circuit package includes a die. An electrically conductive layer comprises a redistribution layer (RDL) in the die, or a micro-bump layer above the die, or both. The micro bump layer comprises at least one micro-bump line. A filter comprises the electrically conductive layer. A capacitor comprises an electrode formed in the electrically conductive layer.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: May 1, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiao-Tsung Yen, Jhe-Ching Lu, Yu-Ling Lin, Chin-Wei Kuo, Min-Chie Jeng
  • Patent number: 9944766
    Abstract: A prepreg includes a fiber base material and a thermosetting resin composition impregnated into the fiber base material. The thermosetting resin composition contains a thermosetting resin including an epoxy resin; a curing agent; an inorganic filler; and an acrylic acid ester copolymer having a weight average molecular weight of 10×104 or more and less than 45×104. A content of the inorganic filler is 150 parts by mass or more relative to a total of 100 parts by mass of the thermosetting resin and the curing agent. A content of the acrylic acid ester copolymer is more than 30 parts by mass and 90 parts by mass or less relative to the total of 100 parts by mass of the thermosetting resin and the curing agent.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: April 17, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Masaaki Matsumoto, Takatoshi Mito, Tatuo Yonemoto
  • Patent number: 9922921
    Abstract: A semiconductor package includes: a semiconductor chip including an effective chip region at a center of the semiconductor chip and in which pads connected to chip wirings are formed, and a dummy chip region at a side of the effective chip region and in which pads not connected to the chip wirings are formed; a base film including a chip mounting section on which the semiconductor chip is mounted; and a plurality of wiring patterns disposed on the base film and electrically connected to the chip wirings of the semiconductor chip, wherein first wiring patterns, which are a part of the plurality of wiring patterns, extend on a first region of the chip mounting section corresponding to the dummy chip region.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: March 20, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-min Jung, Na-rae Shin
  • Patent number: 9902880
    Abstract: A film material includes a substrate and a film layer arranged on one main surface of the substrate. The film layer contains a fibrous first resin and a thermosetting second resin in an uncured or semi-cured state, and a linear expansion coefficient CF of the first resin is smaller than a linear expansion coefficient CR of the second resin in cured state.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: February 27, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Koji Motomura
  • Patent number: 9872394
    Abstract: A method for filling vias with metal includes receiving a substrate having vias, forming a metal plating layer over the vias on a first side of the substrate, fill-plating the vias with a first metal beginning with the metal plating layer on the first side of the substrate and advancing to a second side of the substrate to provide filled vias. The metal plating layer may be subsequently patterned to provide selected circuit connections or chemically-mechanically polished to completely remove the metal plating layer. Forming a metal plating layer over the vias may include filling the vias with a sacrificial filler to enable formation of the metal plating layer and subsequently removing the sacrificial filler via an etching operation or the like. In other embodiments, forming the metal plating layer over the vias is accomplished by bonding a metallic layer onto the first side of the substrate.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: January 16, 2018
    Assignee: International Business Machines Corporation
    Inventors: Steven A. Cordes, Bing Dang, Sung K. Kang, Yu Luo, Peter J. Sorce
  • Patent number: 9831776
    Abstract: An apparatus that includes a resonant DC-DC converter with switching frequencies based on stray inductances of the physical components used to construct the apparatus. This results in a relatively high efficiency and high density DC-DC converter that, in some implementations, does not require a discrete inductor component.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: November 28, 2017
    Assignee: Google Inc.
    Inventors: Shuai Jiang, Xin Li
  • Patent number: 9706660
    Abstract: A solar junction box includes a housing having a base and walls defining a cavity. The base has an opening configured to receive a conductive foil. A power cable is held in the housing having a power terminal terminated to an end of the power cable positioned within the housing. An electronic module is removably received in the cavity. The electronic module has a circuit board including electronic components mounted to the circuit board, a foil contact configured to be removably coupled to the foil, and a power contact configured to be removably coupled to the power terminal. The circuit board has a power circuit electrically connecting the foil contact and the power contact.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: July 11, 2017
    Assignees: TE Connectivity Corporation, Tyco Electronics UK Ltd.
    Inventors: Matthew Edward Mostoller, Subhash Mungarwadi
  • Patent number: 9627496
    Abstract: A semiconductor device includes a two-input NOR circuit including four MOS transistors arranged in a line. Each of the MOS transistors is disposed on a planar silicon layer disposed on a substrate. The drain, gate, and source of the MOS transistor are arranged in the vertical direction. The gate surrounds a silicon pillar. The planar silicon layer is constituted by a first activation region of a first conductivity type and a second activation region of a second conductivity type. The first and second activation regions are connected to each other via a silicon layer disposed on a surface of the planar silicon layer, so as to form a NOR circuit having a small area.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: April 18, 2017
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Masamichi Asano
  • Patent number: 9514076
    Abstract: An information handling system is set forth which includes a fully connected 4S topology that can also be populated with two processors and two link modules (e.g., two passive “slugs”) to implement a fully connected 2S topology. More specifically, the link module is a printed circuit board that implements a loopback connection between certain links of the architecture. In certain embodiment, the link module includes no electrical components. The link module merely includes a set of electrical connections (e.g., copper traces) connecting pads (e.g., gold plated pads) on a thick printed circuit board (PCB) dielectric material that is shaped to fit the processor socket. The link module is used to carry user data when the information handling system is configured in a 2S topology. The link module includes proper lane assignment that allows the module to be passive without performance reduction.
    Type: Grant
    Filed: June 2, 2008
    Date of Patent: December 6, 2016
    Assignee: Dell Products L.P.
    Inventors: Sandor T. Farkas, Fernando Meschino, Thomas Edwin Garvens, Michael Jon Roberts, Scott Michael Ramsey, Charles L. Haley
  • Patent number: 9502344
    Abstract: Wafer level packaged semiconductor device with enhanced heat dissipation properties. The semiconductor device includes a top and a bottom face and at least one metal pad is positioned on the top and the bottom faces. A top cover is affixed to the top face of the semiconductor device and a bottom cover is affixed to the bottom face of the semiconductor device. Vias extend through the top and bottom covers and an electroplated metal layer extends from an external face of the covers, through the visas to the metal pads on the semiconductor device.
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: November 22, 2016
    Inventor: Mordechai Margalit
  • Patent number: 9478489
    Abstract: The width of scribe lines may be reduced in semiconductor devices by applying a process technique in which trenches may be formed first from the rear side on the basis of a required width of the corresponding trenches, while subsequently it may be cut into the substrate from the front side on the basis of a reduced thickness of the corresponding saw blades, thereby also enabling a reduction of the scribe line width. Furthermore, contamination of the front side, i.e., of the metallization system, may be reduced, for instance, by performing an optional intermediate cleaning process.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: October 25, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Daniel Richter, Frank Kuechenmeister
  • Patent number: 9462696
    Abstract: The invention relates to a circuit module (10) having a circuit carrier (12), at least one circuit (14) mounted on the circuit carrier (12), encapsulated by a protective material (16), and at least one electrical/electronic component (18) encapsulated by a protective coating (20), protecting the at least one electrical/electronic component (18) from the protective material (16), and to a method for producing the circuit module (10). According to the invention, the protective coating (20) protecting the at least one electrical/electronic component (18) is only partially encapsulated by the protective material (16).
    Type: Grant
    Filed: December 7, 2010
    Date of Patent: October 4, 2016
    Assignee: Robert Bosch GmbH
    Inventors: Stephan Mazingue-Desailly, Michael Mueller
  • Patent number: 9449937
    Abstract: There is provided a semiconductor device. The semiconductor device of the present invention includes a semiconductor element and a metal buffer layer in an electrical connection to the semiconductor element. The metal buffer layer and the semiconductor element are in a connection with each other by mutual surface contact of the metal buffer layer and the semiconductor element. The metal buffer layer is an external connection terminal used for a mounting with respect to a secondary mount substrate, and the metal buffer layer serves as a buffer part having a stress-relaxation effect between the semiconductor element and the secondary mount substrate.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: September 20, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Koji Kawakita, Susumu Sawada, Seiichi Nakatani, Yoshihisa Yamashita
  • Patent number: 9433101
    Abstract: A method for filling vias with metal includes receiving a substrate having vias, forming a metal plating layer over the vias on a first side of the substrate, fill-plating the vias with a first metal beginning with the metal plating layer on the first side of the substrate and advancing to a second side of the substrate to provide filled vias. The metal plating layer may be subsequently patterned to provide selected circuit connections or chemically-mechanically polished to completely remove the metal plating layer. Forming a metal plating layer over the vias may include filling the vias with a sacrificial filler to enable formation of the metal plating layer and subsequently removing the sacrificial filler via an etching operation or the like. In other embodiments, forming the metal plating layer over the vias is accomplished by bonding a metallic layer onto the first side of the substrate.
    Type: Grant
    Filed: October 16, 2014
    Date of Patent: August 30, 2016
    Assignee: International Business Machines Corporation
    Inventors: Steven A. Cordes, Bing Dang, Sung K. Kang, Yu Luo, Peter J. Sorce
  • Patent number: 9425166
    Abstract: A GOA layout method, an array substrate and a display device are provided. The array substrate includes a plurality of GOA unit groups, each of which includes two adjacent GOA units. The plurality of GOA unit groups includes a first GOA unit group, two GOA units of the first GOA unit group have an overlapping region with at least one via hole provided therein, and the two GOA units of the first GOA unit group are electrically connected through the at least one via hole. With the array substrate, the density of gate lines can be increased.
    Type: Grant
    Filed: October 20, 2014
    Date of Patent: August 23, 2016
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Song Song, Kazuyoshi Nagayama
  • Patent number: 9412674
    Abstract: An integrated circuit includes a die having a conductive layer. The conductive layer includes a data wire, a first power supply wire of a first voltage potential, and a second power supply wire of a second voltage potential different from the first voltage potential. A segment of the data wire is located between, and substantially parallel to, a segment of the first power supply wire and a segment of the second power supply wire. Further, the first power supply wire is coupled to a first probe structure; and, the second power supply wire is coupled to a second probe structure.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: August 9, 2016
    Assignee: XILINX, INC.
    Inventors: Myongseob Kim, Henley Liu, Cheang-Whang Chang, Sanjiv Stokes
  • Patent number: 9391026
    Abstract: Package substrate, semiconductor packages and methods for forming a semiconductor package are presented. The package substrate includes a base substrate having first and second major surfaces and a plurality of via contacts extending through the first to the second major surfaces of the base substrate. A first conductive layer having a plurality of openings is disposed over the first surface of the base substrate and via contacts. The openings are configured to match conductive trace layout of the package substrate. Conductive traces are disposed over the first conductive layer. The conductive traces are directly coupled to the via contacts through some of the openings of the first conductive layer.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: July 12, 2016
    Assignee: UTAC HEADQUARTERS PTE. LTD.
    Inventor: Chuen Khiang Wang
  • Patent number: 9385103
    Abstract: A method for manufacturing a semiconductor device, includes preparing a solder, a soldering article, a base material, a weight having a foot where a center of gravity of the weight is shifted from a center of the soldering article, a positioning jig having a hole for holding the soldering article in the base material, and a dam member; disposing the dam member on a side having a relatively lower height due to a warp of an edge portion of the base material; placing the positioning jig on a principal surface of the base material; placing the soldering article on the solder in the hole; placing the weight on an upper surface of the soldering article to position the center of gravity on the side having relatively lower height; and raising the temperature of the solder to a temperature equal to or higher than the melting point of the solder.
    Type: Grant
    Filed: April 11, 2014
    Date of Patent: July 5, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Shinji Sano, Tatsuo Nishizawa
  • Patent number: 9368890
    Abstract: An electrical connector assembly essentially consists of four connector units neighboring with one another each occupying a quadrant in a square manner so that each connector units defines two unexposed neighboring sides and two exposed outer sides. Each connector unit includes an insulative housing with a plurality of passageways to receive the corresponding contacts therein. A vertically and horizontally staggered structure is formed on each neighboring side of the housing. A pair of inner interengaging structures and a pair of outer neighboring structures are respectively formed on two opposite ends of the corresponding neighboring sides of the neighboring connector units so as to allow the neighboring connector units to be assembled in a pivotal way with the pair of outer interengaging structures as a fulcrum.
    Type: Grant
    Filed: July 1, 2015
    Date of Patent: June 14, 2016
    Assignee: FOXCONN INTERCONNECT TECHNOLOGY LIMITED
    Inventor: Fang-Jwu Liao
  • Patent number: 9355906
    Abstract: Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a method of manufacturing a packaging device includes forming an interconnect wiring over a substrate, and forming conductive balls over portions of the interconnect wiring. A molding material is deposited over the conductive balls and the substrate, and a portion of the molding material is removed from over scribe line regions of the substrate.
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: May 31, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Tsung-Yuan Yu, Ming-Da Cheng, Wen-Hsiung Lu
  • Patent number: 9313394
    Abstract: A waterproof electronic device with a soft polymer embedding enclosure configured to seal components embedded in the soft polymer embedding enclosure from water by direct contact of the soft polymer embedding enclosure with the components, and including an embedded microswitch operated by pressing on an outer surface of the soft polymer embedding enclosure. The apparatus may be built using various degrees of integration of its components.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: April 12, 2016
    Assignee: H4 Engineering, Inc.
    Inventors: Christopher T. Boyle, Scott K. Taylor, Alexander G. Sammons, Denes Marton
  • Patent number: 9263300
    Abstract: A method for manufacturing vias in a glass substrate includes bonding, through a bonding layer, a first face of the glass substrate including a plurality of holes to a first face of a glass carrier. The bonding layer has a thickness t between the first face of the glass substrate and the first face of the glass carrier and extends into at least some of the plurality of holes to a depth h from the first face of the glass substrate. The method includes etching back the bonding layer to a depth d through the plurality of holes in the glass substrate. The depth d is less than the sum of the thickness t and the depth h. The method can include filling the plurality of holes with an electrically conductive material, and de-bonding the glass substrate from the bonding layer and the glass carrier.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: February 16, 2016
    Assignee: Corning Incorporated
    Inventors: Chih-Wei Tsai, Bor Kai Wang
  • Patent number: 9123713
    Abstract: A microelectronic structure includes a first row of contacts (14) and a second row of contacts (24) offset from the first row, so that the first and second rows cooperatively define pairs of contacts. These pairs of contacts include first pairs (30a) and second pairs (30b) arranged in alternating sequence in the row direction. The first pairs are provided with low connectors (32a), whereas the second pairs are provided with high connectors (32b). The high connectors and low connectors have sections vertically offset from one another to reduce mutual impedance between adjacent connectors.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: September 1, 2015
    Assignee: Tessera, Inc.
    Inventors: Richard Dewitt Crisp, Belgacem Haba, Wael Zohni
  • Patent number: 9059187
    Abstract: An electronic component including a wiring board having interlayer insulation layers and conductive patterns, the wiring board having a first surface and a second surface on the opposite side of the first surface, multiple first bumps formed on a first conductive pattern positioned on the first surface of the wiring board among the conductive patterns of the wiring board, a semiconductor element mounted on the first surface of the wiring board through the first bumps, an encapsulating resin encapsulating the semiconductor element and at least a portion of a side surface of the wiring board, the side surface of the wiring board extending between the first surface and second surface of the wiring board, and multiple of second bumps formed on the second surface of the wiring board and connected to a second conductive pattern of the conductive patterns in the wiring board.
    Type: Grant
    Filed: August 22, 2011
    Date of Patent: June 16, 2015
    Assignee: IBIDEN CO., LTD.
    Inventors: Toshiki Furutani, Daiki Komatsu, Nobuya Takahashi
  • Publication number: 20150144985
    Abstract: An electronic device includes a base body, which has a top side and also an underside lying opposite the top side. The base body has connection locations at its underside. An electronic component is arranged at the base body at the top side of the base body. The base body has at least one side area having at least one point of inspection having a first region and second region. The second region is embodied as an indentation in the first region. The first and the second region contain different materials.
    Type: Application
    Filed: January 28, 2015
    Publication date: May 28, 2015
    Inventors: Michael Zitzlsperger, Stefan Groetsch
  • Patent number: 9035194
    Abstract: Embodiments of the present disclosure are directed towards a circuit board having integrated passive devices such as inductors, capacitors, resistors and associated techniques and configurations. In one embodiment, an apparatus includes a circuit board having a first surface and a second surface opposite to the first surface and a passive device integral to the circuit board, the passive device having an input terminal configured to couple with electrical power of a die, an output terminal electrically coupled with the input terminal, and electrical routing features disposed between the first surface and the second surface of the circuit board and coupled with the input terminal and the output terminal to route the electrical power between the input terminal and the output terminal, wherein the input terminal includes a surface configured to receive a solder ball connection of a package assembly including the die. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: October 30, 2012
    Date of Patent: May 19, 2015
    Assignee: Intel Corporation
    Inventors: M D Altaf Hossain, Jin Zhao, John T. Vu
  • Publication number: 20150131254
    Abstract: The present invention discloses a printed circuit board, a semiconductor package having the same, and a method for manufacturing the same. A printed circuit board according to an aspect of the present invention includes: a package board including a mounting area and a peripheral area, the mounting area having a semiconductor chip mounted therein, the peripheral area surrounding the mounting area; a first central circuit pattern formed in the mounting area on one surface of the package board; a second central circuit pattern formed in the mounting area on the other surface of the package board and having a greater thickness than the first central circuit pattern; a first peripheral circuit pattern formed in the peripheral area on the one surface of the package board; and a second peripheral circuit pattern formed in the peripheral area on the other surface of the package board and having a greater thickness than the second peripheral circuit pattern.
    Type: Application
    Filed: March 28, 2014
    Publication date: May 14, 2015
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Min-Sung KIM, Jun-Hyung SON
  • Publication number: 20150131255
    Abstract: A semiconductor package may include: a substrate including a core layer having a first surface and a second surface which is opposite to the first surface, a wiring layer formed over the first and second surfaces and in an inside of the core layer, and having a first electrode disposed in the inside of the core layer and exposed from the core layer and a second electrode disposed over the first surface, and a passivation layer formed over the first and second surface of the core layer such that the first and the second electrodes are exposed; a first semiconductor chip disposed over the first surface of the core layer; a second semiconductor chip stacked over the first semiconductor chip; a first connection member for connecting the first semiconductor chip with the first electrode; and a second connection member for connecting the second semiconductor chip with the second electrode.
    Type: Application
    Filed: April 15, 2014
    Publication date: May 14, 2015
    Applicant: SK hynix Inc.
    Inventor: Eun Hye DO
  • Publication number: 20150126134
    Abstract: Devices and methods related to packaging of radio-frequency (RF) devices on ceramic substrates. In some embodiments, a packaged electronic device can include a ceramic substrate configured to receive one or more components. The ceramic substrate can include a conductive layer in electrical contact with a ground plane. The packaged electronic device can further include a die having an integrated circuit and mounted on a surface of the ceramic substrate. The packaged electronic device can further include a conformal conductive coating implemented over the die to provide shielding functionality. The packaged electronic device can further include an electrical connection between the conformal conductive coating and the conductive layer.
    Type: Application
    Filed: October 30, 2014
    Publication date: May 7, 2015
    Inventors: Anthony James LOBIANCO, Howard E. CHEN, David Scott WHITEFIELD
  • Publication number: 20150124423
    Abstract: A method of manufacturing a circuit board includes forming a first electrode on a support substrate, covering the support substrate and the first electrode with a first insulating layer, polishing the first insulating layer to expose a first surface of the first electrode, forming a first wiring on the first insulating layer after exposing the first surface of the first electrode, the first wiring being connected to the first electrode, and removing the support substrate to expose a second surface of the first electrode after forming the first wiring.
    Type: Application
    Filed: January 12, 2015
    Publication date: May 7, 2015
    Inventors: Kazuya ARAI, Shinpei IKEGAMI, Hitoshi SUZUKI, Kei FUKUI
  • Patent number: 9025341
    Abstract: A power module includes a power module body portion and a wiring board. The power module body portion includes P-side semiconductor elements and N-side semiconductor elements, and a P-side terminal connection portion, a U-phase terminal connection portion, and an N-side terminal connection portion which establish electrical connection with the wiring board on an upper surface of the power module body portion and into which a current flows from the wiring board and from which a current flows to the wiring board.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: May 5, 2015
    Assignee: Kabushiki Kaisha Yaskawa Denki
    Inventor: Yasuhiko Kawanami
  • Publication number: 20150115468
    Abstract: Provided is a semiconductor package including a wiring substrate having top and bottom surfaces facing each other. A first semiconductor chip is disposed on the wiring substrate in a flip-chip manner. The first semiconductor chip has a first surface facing the top surface of the wiring substrate and a second surface opposite to the first surface. First connection members are disposed between the wiring substrate and the first semiconductor chip. The first connection members include first and second contact members each including one or more magnetic materials. The first contact members include portions disposed in the second contact members. The one or more magnetic material of the first contact members have an opposite polar orientation to that of the second contact members.
    Type: Application
    Filed: August 12, 2014
    Publication date: April 30, 2015
    Inventors: Hyunsuk CHUN, SOOJAE PARK, SEUNGBAE LEE, SANGSU HA
  • Patent number: 9012559
    Abstract: Provided is a heat curable adhesive that can strongly bond a base material formed of a crystalline polyester resin, can freely regulate the thickness of an adhesive layer, has excellent chemical resistance, and, at the same time, has excellent storage stability. Furthermore, provided is a resin laminated-type IC card, in which a liquid heat curable adhesive of which use has been difficult in the past can be used, and the liquid heat curable adhesive can be coated with a good accuracy by a printing method without the need to perform molding into a hot-melt sheet to bond a base material formed of a crystalline polyester resin. Accordingly, the resin laminated-type IC card can have a high degree of freedom in design of the thickness of an IC card. The heat curable adhesive comprises (a) a hydroxyl group-containing non-crystalline polyester resin, (b) a resin containing a carboxylic acid anhydride, and (c) a solvent for dissolving (a) the hydroxyl group-containing non-crystalline polyester resin.
    Type: Grant
    Filed: June 10, 2009
    Date of Patent: April 21, 2015
    Assignee: Taiyo Holdings Co., Ltd.
    Inventors: Chihiro Funakoshi, Yoshitomo Aoyama
  • Patent number: 9012787
    Abstract: An electronic board includes conducting traces having an upper surface at least partially sunken with respect to a gluing surface of the board. A surface mount technology electronic device for mounting to the board includes insulating windows that define gluing sites within one or more pins. An electronic system is formed by one or more of such surface mount technology electronic devices mounted to electronic board. The devices are attached using a wave soldering technique that flows through channels formed by the sunken conductive traces.
    Type: Grant
    Filed: September 25, 2012
    Date of Patent: April 21, 2015
    Assignee: STMicroelectronics S.r.l.
    Inventors: Cristiano Gianluca Stella, Rosalba Cacciola
  • Publication number: 20150103479
    Abstract: The embodiments described herein describe technologies for memory systems. One implementation of a memory system includes a motherboard substrate with multiple module sockets, at least one of which is populated with a memory module. A first set of data lines is disposed on the motherboard substrate and coupled to the module sockets. The first set of data lines includes a first subset of point-to-point data lines coupled between a memory controller and a first socket and a second subset of point-to-point data lines coupled between the memory controller and a second socket. A second set of data lines is disposed on the motherboard substrate and coupled between the first socket and the second socket. The first and second sets of data lines can make up a memory channel.
    Type: Application
    Filed: October 15, 2014
    Publication date: April 16, 2015
    Inventors: Frederick A. Ware, Suresh Rajan
  • Patent number: 9001523
    Abstract: A method for patterning a layer stack with at least one ceramic layer includes providing the ceramic layer, which has at least one plated-through hole. An electrically conductive layer is applied above the ceramic layer, such that the electrically conductive layer is electrically coupled to the at least one plated-through hole. A further layer is deposited onto the electrically conductive layer in the region of the at least one plated-through hole, wherein the further layer includes nickel. The electrically conductive layer is removed outside the region of the at least one plated-through hole. A carrier device patterned in this way can be electrically and mechanically coupled to an electronic component.
    Type: Grant
    Filed: August 11, 2010
    Date of Patent: April 7, 2015
    Assignee: Epcos AG
    Inventors: Sebastian Brunner, Gerhard Fuchs, Annette Fischer, Manfred Fischer, Christian Faistauer, Guenter Pudmich, Edmund Payr, Stefan Leopold Hatzl
  • Publication number: 20150092378
    Abstract: A circuit board upon which to mount an integrated circuit chip may include a first interconnect zone on the surface of the circuit board having first contacts with a first pitch, and a second interconnect zone, surrounding the first zone, having second contacts or traces with a second pitch that is smaller than the first pitch. The first contacts may have a design rule (DR) for direct chip attachment (DCA) to an integrated circuit chip. The first contacts may be formed by bonding a sacrificial substrate having the first contacts to a surface of the board; or by laser scribing trenches where the conductor will be plated to create the first contacts. Such a board allows DCA of smaller footprint processor chips for devices, such as tablet computers, cell phones, smart phones, and value phone devices.
    Type: Application
    Filed: September 28, 2013
    Publication date: April 2, 2015
    Inventors: Mihir K. ROY, Mathew J. MANUSHAROW