Having Semiconductive Device Patents (Class 361/783)
  • Patent number: 11503731
    Abstract: The present disclosure provides an assembly structure for providing power for a chip and an electronic device using the same. The assembly structure includes: a circuit board, configured to provide a first electrical energy; a chip; a power converting module, configured to electrically connect the circuit board and the chip, convert the first electrical energy to a second electrical energy, and supply the second electrical energy to the chip, wherein the chip, the circuit board and the power converting module are stacked; and a connection component, configured to electrically connect the circuit board and the power converting module. The present disclosure assembles a power converting module with a circuit board and a chip in a stacking manner, which may shorten a current path between the power converting module and the chip, reduce current transmission losses, improve efficiency of a system, reduce space occupancy and save system resource.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: November 15, 2022
    Assignee: Delta Electronics Inc.
    Inventors: Haoyi Ye, Jianhong Zeng, Yu Zhang, Peiqing Hu, Ziying Zhou
  • Patent number: 11469164
    Abstract: A packaged half-bridge circuit includes a carrier having a dielectric core and a first layer of metallization formed on an upper surface of the carrier, first and second semiconductor chips, each including a first terminal, a second terminal, and a control terminal, and a conductive connector mounted on the upper surface of the carrier and electrically connected to the first layer of metallization. The first semiconductor chip is configured as a high-side switch of the half-bridge circuit. The second semiconductor chip is configured as a low-side switch of the half-bridge circuit. At least one of the first and second semiconductor chips is embedded within the dielectric core of the carrier. The conductive connector is electrically connected to one of the first and second terminals from one or both of the first and second semiconductor chips.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: October 11, 2022
    Assignee: Infineon Technologies AG
    Inventors: Robert Fehler, Eung San Cho, Danny Clavette, Petteri Palm
  • Patent number: 11410927
    Abstract: A semiconductor structure and a method for forming the semiconductor structure are disclosed. The method includes receiving a first integrated circuit component having a seal ring and a fuse structure, wherein the fuse structure is electrically connected to a ground through the seal ring; receiving a second integrated circuit component having an inductor; bonding the second integrated circuit component to the first integrated circuit component; electrically connecting the inductor to the fuse structure, wherein the inductor is electrically connected to the ground through the fuse structure; and blowing the fuse structure after a treatment.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: August 9, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jen-Yuan Chang, Chia-Ping Lai
  • Patent number: 11393786
    Abstract: A method for manufacturing electronic chips includes depositing, on a side of an upper face of a semiconductor substrate, in and on which a plurality of integrated circuits has been formed, a protective resin. The method includes forming, in the protective resin, at least one cavity per integrated circuit, in contact with an upper face of the integrated circuit. Metal connection pillars are formed by filling the cavities with metal. The integrated circuits are separated into individual chips by cutting the protective resin along cut lines extending between the metal connection pillars.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: July 19, 2022
    Assignee: STMicroelectronics (Tours) SAS
    Inventors: Ludovic Fallourd, Christophe Serre
  • Patent number: 11388820
    Abstract: A driving circuit board includes: a circuit connection board having a first surface and a second surface that is opposite to the first surface in a thickness direction of the circuit connection board; at least one driver integrated circuit (IC) disposed on the first surface of the circuit connection board; and a printed circuit board assembly (PCBA) bonded to the second surface of the circuit connection board.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: July 12, 2022
    Assignees: BEIJING BOE DISPLAY TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Junjie Guo, Zhihua Sun, Shulin Yao
  • Patent number: 11337012
    Abstract: Embodiments of the invention include a method of preventing ferrite migration in a hearing aid including an antenna stack and a battery stack wherein the antenna stack sits on the battery stack, the method comprising the steps of: conformally coating the top and sides of the antenna stack using a conformal coating material; and separately coating all the surfaces of the battery stack using a separate material.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: May 17, 2022
    Assignee: Earlens Corporation
    Inventors: Andy Atamaniuk, Lakshman Rathnam
  • Patent number: 11302670
    Abstract: A semiconductor device including: an insulating circuit substrate including a principal surface and a back surface; semiconductor chips each including an electrode on a principal surface and having a back surface on an opposite side to the principal surface, the back surface being fixed to the principal surface of the insulating circuit substrate; a wiring substrate facing the principal surface side of the insulating circuit substrate, separated from the semiconductor chip; a conductive post fixed to the electrode of the semiconductor chips and the wiring substrate; and a resin sealing body sealing the insulating circuit substrate, the semiconductor chips, the wiring substrate, and the conductive posts in such a manner as to expose the back surface of the insulating circuit substrate, wherein the semiconductor chips are respectively arranged on sides on which two short sides are located, and the conductive post has a recessed portion on its peripheral surface.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: April 12, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yoko Nakamura
  • Patent number: 11272617
    Abstract: The invention relates to an electronic module (40) comprising at least one printed circuit board of a first type (referred to as “printed circuit board A”), which is equipped in an overlapping manner with at least one printed circuit board of a second type (referred to as “printed circuit hoard B”), printed circuit board B being equipped with at least one electronic component with specific requirements (19), and the interconnected printed circuit boards A and B forming a stepped composite printed circuit board (100, 200, 300, 400, 500). The composite printed circuit board (100, 200, 300, 400, 500) is delimited at least in some regions by end regions (16) which are formed by sections of the at least one printed circuit board A, and the composite printed circuit board (100, 200, 300, 400, 500) is placed on a heat sink (20).
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: March 8, 2022
    Assignee: ZKW Group GmbH
    Inventors: Dietmar Kieslinger, Erik Edlinger, Markus Lahner, Wolfgang Manhart
  • Patent number: 11264307
    Abstract: Techniques that can assist with fabricating a package layer that includes a plurality of dual-damascene zero-misalignment-vias (dual-damascene ZMVs) and a trace between the dual-damascene ZMVs are described. The disclosed techniques allow for the dual-damascene ZMVs and their corresponding trace to be plated simultaneously in a single step or operation. As such, there is little or no misalignment between the dual-damascene ZMVs, the trace, and the metal pads connected to the ZMVs. In this way, one or more of the embodiments described herein can assist with reducing manufacturing costs, reducing development time of fabricating a package layer, and with increasing the I/O density in a semiconductor package.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: March 1, 2022
    Assignee: Intel Corporation
    Inventors: Aleksandar Aleksov, Hiroki Tanaka, Robert A. May, Kristof Darmawikarta, Changhua Liu, Chung Kwang Tan, Srinivas Pietambaram, Sri Ranga Sai Boyapati
  • Patent number: 11222882
    Abstract: Disclosed is a semiconductor package including a first semiconductor chip on a substrate, a second semiconductor chip on the substrate and laterally spaced apart from the first semiconductor chip, a dummy chip on the first semiconductor chip, and a dielectric layer between the first semiconductor chip and the dummy chip. A top surface of the first semiconductor chip may be lower than a top surface of the second semiconductor chip. The dielectric layer may include an inorganic dielectric material.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: January 11, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Younglyong Kim
  • Patent number: 11214660
    Abstract: The present invention relates to a prepreg including a fiber base material layer containing a fiber base material, a first resin layer formed on one surface of the fiber base material layer, and a second resin layer formed on the other surface of the fiber base material layer, wherein the first resin layer is a layer obtained through layer formation of a resin composition (I) containing, as a main component of resin components, an epoxy resin (A), and the second resin layer is a layer obtained through layer formation of a resin composition (II) containing, as a main component of resin components, an amine compound (B) having at least two primary amino groups in one molecule thereof and a maleimide compound (C) having at least two N-substituted maleimide groups in one molecule thereof; a laminated sheet obtained by using the prepreg; a printed wiring board; a coreless board; a semiconductor package; and a method of producing a coreless board.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: January 4, 2022
    Assignee: Showa Denko Materials Co., Ltd.
    Inventors: Yuma Yoshida, Yuichi Shimayama, Yukio Nakamura, Shinji Tsuchikawa, Katsuhiko Nawate, Shintaro Hashimoto
  • Patent number: 11201066
    Abstract: Described herein are methods of manufacturing dual-sided packaged electronic modules to control the distribution of an under-fill material between one or more components and a packaging substrate. The disclosed technologies include using a dam on a packaging substrate that is configured to prevent or limit the flow of a capillary under-fill material. This can prevent or limit the capillary under-fill material from flowing onto or contacting other components or elements on the packaging substrate, such as solder balls of a ball-grid array. Accordingly, the disclosed technologies control under-fill for dual-sided ball grid array packages using a dam on a packaging substrate.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: December 14, 2021
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Robert Francis Darveaux, Bruce Joseph Freyman, Yi Liu
  • Patent number: 11177141
    Abstract: A method for packaging a chip and a chip package structure are provided. The method is used to package the chip including an acoustic filter. The packaging substrate and the device wafer are welded together, wherein the edge of the device wafer is chamfered, the packaging substrate is provided with a groove, the chamfered portion of device wafer is aligned with the groove on the substrate, and then a mask is disposed. The surface of the mask facing the device wafer is an inclined surface, forming a wedge-shaped opening. A package resin material is printed, wherein the package resin material falls into the groove through the inclined surface of the mask, and a package resin film is formed between the groove and the chamfer. The mask is removed along the first surface toward the second surface. The package resin is cured in a position where the resin film is located.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: November 16, 2021
    Assignee: JWL (Zhejiang) Semiconductor Co., Ltd
    Inventor: Linping Li
  • Patent number: 11164891
    Abstract: Novel integrated circuits (SOI ICs), and methods for making and mounting the ICs are disclosed. In one embodiment, an IC comprises a first circuit layer of the IC formed from an active layer of an SOI wafer. The first circuit layer is coupled to a first surface of buffer layer, and a second surface of the buffer layer is coupled to a selected substrate comprising an insulating material. The selected substrate may be selected, without limitation, from the following types: sapphire, quartz, silicon dioxide glass, piezoelectric materials, and ceramics. A second circuit layer of the IC are formed, coupled to a second surface of the selected substrate. In one embodiment of a mounted IC, the first circuit layer is coupled to contact pads on a package substrate via solder bumps or copper pillars. The second circuit layer is coupled to contact pads on the package substrate via wire bonds.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: November 2, 2021
    Assignee: pSemi Corporation
    Inventors: James S. Cable, Anthony Mark Miscione, Ronald Eugene Reedy
  • Patent number: 11145768
    Abstract: Certain aspects of the present disclosure generally relate to a capacitive element. One example capacitive element generally includes a substrate, a plurality of trench capacitors, an electrically conductive via, a first electrically conductive contact, and a second electrically conductive contact. The trench capacitors intersect the substrate. The electrically conductive via intersects the substrate and is disposed adjacent to at least one of the trench capacitors. The first electrically conductive contact is disposed above the substrate, and the second electrically conductive contact is disposed below the substrate and electrically coupled to the plurality of trench capacitors through the electrically conductive via.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: October 12, 2021
    Assignee: Qualcomm Incorporated
    Inventors: Jonghae Kim, Periannan Chidambaram
  • Patent number: 11107744
    Abstract: An IGBT module includes a heat dissipation base plate. A first ceramic heat dissipation element is embedded in the heat dissipation base plate. A first wiring layer is provided on the surface of the heat dissipation base plate. The first side of an IGBT chip is mounted onto the first wiring layer. The second side of the IGBT chip is provided with a heat conductive metal plate. A first heat dissipation plate having a first through hole is provided on a side of the first wiring layer. The IGBT chip and the heat conductive metal plate are located in the first through hole. A second wiring layer is provided on a side of the first heat dissipation plate away from the IGBT chip. The second wiring layer is provided on a side of the heat conductive metal plate.
    Type: Grant
    Filed: January 22, 2017
    Date of Patent: August 31, 2021
    Assignee: RAYBEN TECHNOLOGIES (ZHUHAI) LIMITED
    Inventors: Shan Zhong, Weidong Gao, Qizhao Hu, Wai Kin Raymond Lam
  • Patent number: 11107760
    Abstract: According to the present invention, a semiconductor device includes an insulating substrate having an organic insulating layer and a circuit pattern provided on the organic insulating layer; and a semiconductor chip provided on an upper surface of the circuit pattern, wherein a thickness of the circuit pattern is not less than 1 mm and not more than 3 mm. According to the present invention, a method for manufacturing a semiconductor device includes forming a metal layer with a thickness not less than 1 mm and not more than 3 mm on an organic insulating layer; patterning the metal layer by machining processing to form a circuit pattern; and providing a semiconductor chip on an upper surface of the circuit pattern.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: August 31, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Daisuke Murata, Hiroshi Yoshida, Hidetoshi Ishibashi
  • Patent number: 11017292
    Abstract: Artificial neuron apparatus includes first and second resistive memory cells. The first resistive memory cell is connected in first circuitry having a first input and output. The second resistive memory cell is connected in second circuitry having a second input and output. The first and second circuitry are operable in alternating read and write phases to apply a programming current to their respective memory cells on receipt of excitatory and inhibitory neuron input signals, respectively. During the write phase, resistance of the respective cells is changed in response to successive excitatory and inhibitory neuron input signals. During the read phase, a read current is applied to their respective cells to produce first and second measurement signals, respectively. An output circuit connected to the first and second outputs produces a neuron output signal at a neuron output when a difference between the first and second measurement signals traverses a threshold.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: May 25, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Evangelos S. Eleftheriou, Lukas Kull, Manuel Le Gallo-Bourdeau, Angeliki Pantazi, Abu Sebastian, Tomas Tuma
  • Patent number: 10978366
    Abstract: An object is to provide a power module in which adhesion of a sealing resin is sufficient and which is highly reliable. The power module includes: an insulative board in which a pattern of a conductor layer is formed on a ceramic plate; power semiconductor elements placed on the insulative board; lead frames each in a plate shape connecting from electrodes of the power semiconductor elements to screw-fastening terminal portions; and a sealing resin portion that seals connection portions between the power semiconductor elements and the lead frames, and regions around the connection portions; wherein, in the lead frames, opening portions are formed at positions where each of the lead frames at least partly overlaps, in planar view, with a portion of the insulative board on which the conductor layer is not formed.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: April 13, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Junji Fujino, Yuji Imoto, Shohei Ogawa, Mikio Ishihara
  • Patent number: 10956764
    Abstract: An electronic device according to various embodiments of the present invention comprises: a display panel; a biometric sensor module disposed on the back surface of the display panel; a processor electrically connected to the display panel and the biometric sensor module, and configured to acquire biometric information by using the biometric sensor module; a first adhesive member filling the gap formed between the back surface of the display panel and the biometric sensor module; and a second adhesive member applied on the first adhesive member, wherein the biometric sensor module can be attached to the back surface of the display panel by using the second adhesive member. In addition, other embodiments are possible.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: March 23, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joo Han Kim, Jin Man Kim, Byung Kyu Kim, Jin Woo Park, Young Bae Sim, Yeun Wook Lim
  • Patent number: 10936780
    Abstract: A method of manufacturing an integrated circuit includes identifying a first cell of a layout, placing a first pair of conductive patterns on a first set of routing tracks, placing a second pair of conductive patterns on a second set of routing tracks, and forming, by a first mask, a first set of conductive structures based on the first pair or second pair of conductive patterns. The first cell abuts a second cell. The first cell has a first set of routing tracks. The second cell has a second set of routing tracks. The first and second cell have a same cell height that is a non-integer multiple of a minimum pitch. A top and bottom boundary of the first cell overlaps a pair of the first set of routing tracks. A top and bottom boundary of the second cell overlaps a pair of the second set of routing tracks.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: March 2, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Mahantesh Hanchinal, Chi Wei Hu, Min-Yuan Tsai, Shu-Yi Ying
  • Patent number: 10886254
    Abstract: A solution relating to electronic devices of flip-chip type is provided, which includes at least one chip carrier having a carrier surface, the carrier(s) including one or more contact elements of electrically conductive material on the carrier surface, at least one integrated circuit chip having a chip surface, the chip(s) including one or more terminals of electrically conductive material on the chip surface each one facing a corresponding contact element, solder material soldering each terminal to the corresponding contact element, and a restrain structure around the contact elements for restraining the solder material during a soldering of the terminals to the contact elements. The carrier includes one or more heat dissipation elements of thermally conductive material on the carrier surface facing the chip surface displaced from the terminals, the dissipation elements being free of any solder mask.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: January 5, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stefano Oggioni, Thomas Brunschwiler, Gerd Schlottig
  • Patent number: 10879157
    Abstract: An improved interconnect substrate having high density routings for a chip package assembly, a chip package assembly having a high density substrate, and methods for fabricating the same are provided that utilize substrates having a region of high density routings disposed over a region of low density routings. In one example, a method for fabricating an interconnect substrate is provided that includes forming a high density routing region by depositing a seed layer on a top surface of a low density routing region, patterning a mask layer on the seed layer, forming a plurality of conductive posts on the seed layer, removing the mask layer and the seed layer exposed between the conductive posts, and depositing a dielectric layer between the between the conductive posts, wherein at least some of the conductive posts are electrically coupled to conductive routing comprising the low density routing region.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: December 29, 2020
    Assignee: XILINX, INC.
    Inventor: Jaspreet Singh Gandhi
  • Patent number: 10861741
    Abstract: Electronic packages and related methods are disclosed. An example electronic package apparatus includes a substrate and an electronic component. A protective material is positioned on a first surface, a second surface and all side surfaces of the electronic component to encase the electronic component. An enclosure is coupled to the substrate to cover the protective material and the electronic component.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: December 8, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kurt Peter Wachtler, Anindya Poddar, Usman Mahmood Chaudhry
  • Patent number: 10847435
    Abstract: A method of fabricating a semiconductor package structure is provided. The structure is configured to include a base substrate, a die disposed on the base substrate, the die including a semiconductor device, a solder bump disposed on a surface of the die, and configured to discharge heat generated in the die to an outside; and a solder ball disposed on another surface, opposite to the surface, of the die, and configured to transmit a signal, which is produced by the semiconductor device of the die, to an external device.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: November 24, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Youngho Kim, Hwanpil Park
  • Patent number: 10818568
    Abstract: A charger comprises a housing, a first multi-layer printed circuit board (PCB), a second multi-layer PCB, and a third multi-layer PCB. The first PCB comprises at least a portion of a primary side circuit. The second PCB comprises at least a portion of a secondary side circuit. The third PCB is perpendicular to the first PCB and the second PCB. An isolation coupling element is disposed on the third PCB. The isolation coupling element comprises a multi-layer PCB. The first PCB comprises a high voltage (HV) semiconductor package. A surface of a die paddle of the HV semiconductor package is exposed from a molding encapsulation of the HV semiconductor package.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: October 27, 2020
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.
    Inventors: Pei-Lun Huang, Yu-Ming Chen, Tien-Chi Lin, Jung-Pei Cheng, Yueh-Ping Yu, Zhi-Qiang Niu, Xiaotian Zhang, Long-Ching Wang
  • Patent number: 10797020
    Abstract: A semiconductor device assembly is provided. The assembly comprises a package substrate, a first stack of semiconductor dies having a first set of planform dimensions disposed over a first location on the substrate, a second stack of semiconductor dies having a second set of planform dimensions different from the first set disposed over a second location on the substrate, and an encapsulant at least partially encapsulating the substrate, the first stack and the second stack. The first stack of semiconductor dies has a first planform area, the second stack of semiconductor dies has a second planform area, and a sum of the first and second planform areas can be at least 50%, 67%, 75%, or even more of an area of the package substrate.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: October 6, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Blaine J. Thurgood
  • Patent number: 10782318
    Abstract: A testing probe structure for wafer level testing semiconductor IC packaged devices under test (DUT). The structure includes a substrate, through substrate vias, a bump array formed on a first surface of the substrate for engaging a probe card, and at least one probing unit on a second surface of the substrate. The probing unit includes a conductive probe pad formed on one surface of the substrate and at least one microbump interconnected to the pad. The pads are electrically coupled to the bump array through the vias. Some embodiments include a plurality of microbumps associated with the pad which are configured to engage a mating array of microbumps on the DUT. In some embodiments, the DUT may be probed by applying test signals from a probe card through the bump and microbump arrays without direct probing of the DUT microbumps.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: September 22, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mill-Jer Wang, Ching-Fang Chen, Sandeep Kumar Goel, Chung-Sheng Yuan, Chao-Yang Yeh, Chin-Chou Liu, Yun-Han Lee, Hung-Chih Lin
  • Patent number: 10756012
    Abstract: A circuit assembly is provided. The circuit assembly includes: a first bus bar and a second bus bar that are part of a power circuit; and a control board to which a control circuit configured to control current flow in the power circuit is mounted, the circuit assembly including: a semiconductor switching element including a drain terminal and a source terminal that are connected to the first bus bar and the second bus bar, respectively, and a gate terminal configured to receive input of a control signal from the control circuit configured to control current flow in the power circuit; and a third bus bar configured to electrically connect the gate terminal and the control board.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: August 25, 2020
    Assignees: AutoNetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventors: Yuuichi Hattori, Yoshikazu Sasaki, Jun Ikeda
  • Patent number: 10716215
    Abstract: A display device includes a display substrate with a display area, a first peripheral area, and a second peripheral area, the display area having first and second sides extending in directions crossing each other, the first peripheral area adjacent to the first side, and the second peripheral area adjacent to the second side, a first driving substrate attached to the first peripheral area, the first driving substrate including a first driving circuit portion and a first link wire connected to the first driving circuit portion, a second driving substrate attached to the second peripheral area, the second driving substrate including a second driving circuit portion and a second link wire connected to the second driving circuit portion, and a flexible circuit board attached to the first driving substrate, the flexible circuit board including a third link wire connected to the first and second link wires.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: July 14, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventor: Sang Woo Kim
  • Patent number: 10535622
    Abstract: A substrate structure includes a first portion, a second portion, and an intermedia portion disposed between the first and the second portion and the electrically connected business. The first portion includes a first fine redistribution layer (RDL) and a first coarse RDL. The first coarse RDL includes a first coarse conductive pattern, electrically connected to the first fine conductive pattern, where a, the first coarse RDL includes a first coarse conductive pattern Layout density of the first fine conductive pattern is denser than that of the first coarse conductive pattern. The second portion includes at least one of a second fine RDL and a second coarse RDL. An electronic device including a substrate structure is also provided.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: January 14, 2020
    Inventor: Dyi-Chung Hu
  • Patent number: 10485111
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to via and skip via structures and methods of manufacture. The method includes: forming a first metallization layer with a first capping layer over the first metallization layer; forming a second metallization layer with a second capping layer over the second metallization layer; forming a partial skip via structure to the first metallization layer by removing a portion of the first capping layer and the second capping and depositing conductive material in an opening formed in the second metallization layer; forming a third capping layer over the filled partial skip via and the second capping layer; and forming a remaining portion of a skip via structure in alignment with the partial skip via structure by opening the third capping layer to expose the conductive material of the partial skip via.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: November 19, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Shao Beng Law, Nicholas V. LiCausi, Errol Todd Ryan, James McMahon, Ryan S. Smith, Xunyuan Zhang
  • Patent number: 10475764
    Abstract: A method includes bringing into contact respective first sides of a plurality of dies and a die attach film on a major surface of a carrier wafer, and simultaneously heating portions of the die attach film contacting the plurality of dies in order to simultaneously bond the plurality of dies to the die attach film.
    Type: Grant
    Filed: April 14, 2015
    Date of Patent: November 12, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Shing-Chao Chen, Chung-Shi Liu, Ming-Da Cheng
  • Patent number: 10477671
    Abstract: There is provided a laminated body capable of lowering thermal resistance and capable of suppressing peeling off after a cooling/heating cycle. The laminated body according to the present invention includes an insulating resin layer, a first metal material being a metal foil or a metal plate, and a second metal material being a metal foil or a metal plate, the first metal material is layered on a first surface of the insulating resin layer and the second metal material is layered on a second surface opposite to the first surface of the insulating resin layer, the thickness of the insulating resin layer is 200 ?m or less, the total thickness of the first metal material and the second metal material is 200 ?m or more, the ratio of the thickness of the first metal material to the thickness of the second metal material is 0.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: November 12, 2019
    Assignee: SEKISUI CHEMICAL CO., LTD.
    Inventors: Hiroshi Maenaka, Osamu Inui
  • Patent number: 10448513
    Abstract: A display device includes a display substrate with a display area, a first peripheral area, and a second peripheral area, the display area having first and second sides extending in directions crossing each other, the first peripheral area adjacent to the first side, and the second peripheral area adjacent to the second side, a first driving substrate attached to the first peripheral area, the first driving substrate including a first driving circuit portion and a first link wire connected to the first driving circuit portion, a second driving substrate attached to the second peripheral area, the second driving substrate including a second driving circuit portion and a second link wire connected to the second driving circuit portion, and a flexible circuit board attached to the first driving substrate, the flexible circuit board including a third link wire connected to the first and second link wires.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: October 15, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Sang Woo Kim
  • Patent number: 10423878
    Abstract: Artificial neuron apparatus includes first and second resistive memory cells. The first resistive memory cell is connected in first circuitry having a first input and output. The second resistive memory cell is connected in second circuitry having a second input and output. The first and second circuitry are operable in alternating read and write phases to apply a programming current to their respective memory cells on receipt of excitatory and inhibitory neuron input signals, respectively. During the write phase, resistance of the respective cells is changed in response to successive excitatory and inhibitory neuron input signals. During the read phase, a read current is applied to their respective cells to produce first and second measurement signals, respectively. An output circuit connected to the first and second outputs produces a neuron output signal at a neuron output when a difference between the first and second measurement signals traverses a threshold.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: September 24, 2019
    Assignee: International Business Machines Corporation
    Inventors: Evangelos S. Eleftheriou, Lukas Kull, Manuel Le Gallo-Bourdeau, Angeliki Pantazi, Abu Sebastian, Tomas Tuma
  • Patent number: 10423016
    Abstract: A modulator drive circuit, including: a first transistor having: a first output terminal connected to a first reference voltage, a second output terminal connected to a first output terminal of the modulator drive circuit, and a control terminal; and a second transistor having: a first output terminal connected to a second reference voltage different from the first reference voltage, a second output terminal connected to the first output terminal of the modulator drive circuit, and a control terminal.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: September 24, 2019
    Assignee: Rockley Photonics Limited
    Inventor: David Arlo Nelson
  • Patent number: 10418308
    Abstract: A system includes a heat sink, a semiconductor device, a layer of thermal interface material (TIM) disposed between the heat sink and the semiconductor device, and a fastener system that couples the semiconductor device, the layer of TIM, and the heat sink together. The TIM may facilitate dissipation of heat generated by the semiconductor device via the heat sink during operation of the semiconductor device. The fastener system includes a first Belleville-type washer configured to cooperate with the TIM, which flows when heated beyond a threshold temperature, to maintain a substantially constant coupling force between the semiconductor device and the heat sink during operation of the semiconductor device.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: September 17, 2019
    Assignee: Rockwell Automation Technologies, Inc.
    Inventors: Paul Jerome Grosskreuz, Rui Zhou, Kelly James Bronk, Jeremiah John Kopiness
  • Patent number: 10412830
    Abstract: According to an aspect of the present inventive concept there is provided a system comprising: a conductive textile including conductive fibers, an electronic circuit unit arranged on a first main surface of the conductive textile and including circuitry and a carrier supporting the circuitry, the carrier having a first main surface and a second main surface facing the first main surface of the textile and including a through-hole extending from the first main surface to the second main surface, a conductive pin including an leg segment arranged at least partly in the through-hole, and a grip segment arranged to grip about at least one fiber of the conductive textile. There is also provided a method for mounting an electronic circuit unit on a conductive textile.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: September 10, 2019
    Assignee: IMEC VZW
    Inventors: Riet Labie, Frederic Duflos
  • Patent number: 10276719
    Abstract: In a method of manufacturing a semiconductor device, an opening is formed in an interlayer dielectric layer such that a source/drain region is exposed in the opening. A first semiconductor layer is formed to fully cover the exposed source/drain region within the opening. A heating process is performed to make an upper surface of the first semiconductor layer substantially flat. A conductive contact layer is formed over the first semiconductor layer.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Blandine Duriez, Gerben Doornbos, Mark Van Dal, Martin Christopher Holland
  • Patent number: 10262946
    Abstract: A wiring substrate includes a first wiring structure and a second wiring structure having a higher wiring density. The second wiring structure includes a wiring layer formed on a first insulation layer of the first wiring structure. The wiring layer includes a first wiring pattern, the upper surface of which includes smooth and rough surfaces. A protective film, formed from a conductive material having a higher migration resistance than the wiring layer, covers only the smooth surface and includes a smooth upper surface. A second insulation layer stacked on the first insulation layer covers the wiring layer and the protective film. The smooth surface is continuous with and downwardly recessed from the smooth surface to expose a peripheral portion of the protective film. The second insulation layer covers upper, lower, and side surfaces of the peripheral portion.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: April 16, 2019
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Yusuke Gozu, Yuta Sakaguchi, Norikazu Nakamura, Noriyoshi Shimizu
  • Patent number: 10245682
    Abstract: A method of removing material from a surface, which includes the steps of providing a base layer, at least one layer attached to the base layer, an intermediate finish surface, and a bonding interface surface. The intermediate finish surface is formed by removing the at least one layer and a portion of the base layer during a material removal process. The bonding interface surface is formed by a polishing process applied to the intermediate finish surface. There is an oxidation layer which is part of the base layer, as well as a mold release layer and a contamination layer, both of which are part of the at least one layer. The material removal process involves laser etching the at least one layer to create the intermediate finish surface, and the polishing process includes applying a second laser etching to the intermediate finish surface, forming the bonding interface surface.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: April 2, 2019
    Assignee: Continental Automotive Systems, Inc.
    Inventors: Jared Yagoda, Dana Gradler
  • Patent number: 10147707
    Abstract: A semiconductor device includes a first and a second metal layer, the second provided on a same plane as the first layer, and first second and third terminals. A first metal wiring layer is electrically connected to the first terminal. A second metal wiring layer is electrically connected to the second terminal and the second metal layer and disposed over the first metal wiring layer. A third metal wiring layer is electrically connected to the third terminal and the first metal layer. A first semiconductor chip is provided between the first metal wiring layer and the first metal layer. A second semiconductor chip is provided between the third metal wiring layer and the second metal layer. The first chip has electrodes connected to the first metal wiring layer and the first metal layer. The second chip has electrodes connected to the third metal wiring layer and the second metal layer.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: December 4, 2018
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Tatsuo Tonedachi
  • Patent number: 10117335
    Abstract: A power module includes a power semiconductor device, and a chip component arranged on first and second circuit patterns that are electrically connected to the power semiconductor device, and arranged so as to bridge the first and second circuit patterns. The chip component is arranged so that first and second electrodes are respectively positioned on the first and second circuit patterns, and the first and second electrodes and the first and second circuit patterns are respectively joined with solder layers. Between a lower surface of the chip component and the first circuit pattern and between the lower surface of the chip component and the second circuit pattern, two spacers are provided in parallel with each other respectively at positions close to the first and second electrodes. The solder layers do not exist on an inner side of the two spacers in parallel with each other.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: October 30, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takuya Takahashi, Yasutaka Shimizu
  • Patent number: 10111333
    Abstract: An embodiment of a power-supply module includes a molded package, power-supply components disposed within the package, and an inductor disposed within the package and over the power-supply components. For example, for a given output-power rating, such a power-supply module may be smaller, more efficient, and more reliable than, and may run cooler than, a power-supply module having the inductor mounted outside of the package or side-by-side with other components. And for a given size, such a module may have a higher output-power rating than a module having the inductor mounted outside of the package or side-by-side with other components.
    Type: Grant
    Filed: March 7, 2011
    Date of Patent: October 23, 2018
    Assignee: INTERSIL AMERICAS INC.
    Inventors: Jian Yin, Matthew Harris
  • Patent number: 10077359
    Abstract: The embodiments relate to a polymerizable thermoset composition having improved flame retardant properties, a polymerized thermoset having improved flame retardant properties, a process for manufacturing the polymerized thermoset, and use of the polymerizable thermoset composition to produce lightweight construction components, preferably carbon fiber composites (CFRP), and a lightweight construction component, preferably carbon fiber composite (CFRP), containing the polymerized thermoset.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: September 18, 2018
    Assignee: AIRBUS DEFENCE AND SPACE GMBH
    Inventors: Christoph Meier, Patricia Parlevliet, Manfred Doering
  • Patent number: 10037981
    Abstract: A display system is disclosed. The display system comprises a light emitting diode (LED) device and a backplane (BP) device. The LED device comprises a plurality of LEDs having LED terminals. An LED bonding surface comprising a dielectric layer with LED bonding surface contact pads is coupled to diode terminals of the LEDs. The backplane (BP) device comprises a BP substrate having top and bottom surfaces. A plurality of system on chip (SoC) chips are bonded to chip pads disposed on a bottom surface of the BP device. The SoC chips are electrically coupled to the CMOS components of the BP device and LEDs of the LED device.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: July 31, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Srinivasa Banna, Sanjay Jha, Deepak Nayak, Ajey P. Jacob
  • Patent number: 10026720
    Abstract: An integrated circuit package including a substrate having a cavity and one or more semiconductor devices assembled within the cavity of the substrate. The one or more semiconductor devices electrically coupled using redistribution layers, wherein the cavity is a first cavity, the substrate includes the first cavity and a second cavity, the one or more semiconductor devices are fully embedded within the first cavity of the substrate, the one or more semiconductor devices are fully embedded between the substrate and a first redistribution layer of said redistribution layers, bumps are fully embedded within the second cavity of the substrate, the bumps are fully embedded between the substrate and the first redistribution layer of said redistribution layers, and the first redistribution layer is fully embedded between the substrate and a semiconductor interposer.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: July 17, 2018
    Assignee: BroadPak Corporation
    Inventor: Farhang Yazdani
  • Patent number: 9960133
    Abstract: An integrated circuit package includes a die. An electrically conductive layer comprises a redistribution layer (RDL) in the die, or a micro-bump layer above the die, or both. The micro bump layer comprises at least one micro-bump line. A filter comprises the electrically conductive layer. A capacitor comprises an electrode formed in the electrically conductive layer.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: May 1, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiao-Tsung Yen, Jhe-Ching Lu, Yu-Ling Lin, Chin-Wei Kuo, Min-Chie Jeng
  • Patent number: 9944766
    Abstract: A prepreg includes a fiber base material and a thermosetting resin composition impregnated into the fiber base material. The thermosetting resin composition contains a thermosetting resin including an epoxy resin; a curing agent; an inorganic filler; and an acrylic acid ester copolymer having a weight average molecular weight of 10×104 or more and less than 45×104. A content of the inorganic filler is 150 parts by mass or more relative to a total of 100 parts by mass of the thermosetting resin and the curing agent. A content of the acrylic acid ester copolymer is more than 30 parts by mass and 90 parts by mass or less relative to the total of 100 parts by mass of the thermosetting resin and the curing agent.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: April 17, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Masaaki Matsumoto, Takatoshi Mito, Tatuo Yonemoto