Abstract: Embodiments of an output driver comprising a switching module configured to multiplex a protection transistor between a protection mode and a current mirror mode are disclosed herein. The output driver may operate at high speed with voltages above a maximum threshold voltage specification for the output driver. Additional variants and embodiments may also be disclosed and claimed.

Abstract: A semiconductor power conversion apparatus capable of protecting an IGBT from an overvoltage by supplying a sufficient gate current to the gate of the IGBT. The IGBT is protected from the overvoltage by connecting clamping elements connected in series between a collector of the IGBT and the gate thereof, and by connecting a resistor to each of different junction points between the clamping elements connected in series.

Abstract: A semiconductor integrated circuit includes: an output pad from which an output signal is outputted; an output signal line connected with the output pad; a first pad configured to function as a ground terminal or a power supply terminal; a first wiring connected with the first pad; an output driver connected with the output pad and configured to generate the output signal; an ESD protection device connected with the output signal line and having a function to discharge surge applied to the output pad; and a first trigger MOS transistor used as a trigger device. The output driver includes: a first protection target device connected between the output signal line and the first interconnection; and a first resistance element connected between the first protection target device and the first interconnection.

Abstract: An LED lamp driven by alternating current includes at least a first constant-current supplying device, at least a second constant-current supplying device and at least an LED load. A terminal of the first constant-current supplying device is connected to the first connecting terminal of the AC power source. A terminal of the second constant-current supplying device is connected to the second connecting terminal of the AC power source. The LED load is connected between the first constant-current supplying device and the second constant-current supplying device in series. Through the current limiting function of the first constant-current supplying device and the second constant-current supplying device, the LED lamp may be protected.

Abstract: The invention relates to a circuit arrangement (10) for a control device, and a method for operating said circuit arrangement (10). The circuit arrangement (10) comprises a first field-effect transistor (12) actuating the control device, and a comparator, which compares the voltage provided for actuating the control device with a threshold voltage, and which actuates a timed operation of the first field-effect transistor (12) via a control unit (20) if the threshold voltage is exceeded.

Abstract: Arrangements (1) are provided with electrical elements (11,21) for, in a feeding mode, receiving feeding signals and, in a non-feeding mode, not receiving the feeding signals, and with circuits (12,22) for, in the feeding mode, detecting malfunctions of the electrical elements (11,21). The circuits (12,22) comprise active switches (13,23) for, in response to detection results, deactivating the electrical elements (11,21) in both modes, in other words in the feeding mode as well as the non-feeding mode. The electrical elements (11,21) for example comprise light emitting diodes, incandescent lights or loudspeakers etc. The active switches (13,23) for example comprise bistable micro-relays or semiconductor switches such as non-volatile power semiconductor switches such as one time programmable flash power MOSFETs etc. Preferably, the arrangements (1) are integrated arrangements.

Abstract: A spike suppression circuit for filtering out voltage oscillation produced by an inductive component and a conversion control circuit are disclosed. The spike suppression circuit includes an energy release path and a detection circuit. One end of the energy release path is coupled to a connection terminal of a circuit, and the other end thereof is coupled to a reference voltage. The detection circuit is coupled to the connection terminal. The detection circuit has a high-pass component for turning on the energy release path when the voltage on the connection terminal has a high-frequency signal.

Abstract: An integrated circuit, design structures and methods of forming the integrated circuit which includes a signal pad ESD coupled to an I/O signal pad and a power supply ESD coupled to a source VDD. The signal pad ESD and the power supply ESD are integrated in a single ESD structure.

Abstract: A lateral transient voltage suppressor with ultra low capacitance is disclosed. The suppressor comprises a first conductivity type substrate and at least one diode cascade structure arranged in the first conductivity type substrate. The cascade structure further comprises at least one second conductivity type lightly doped well and at least one first conductivity type lightly doped well, wherein there are two heavily doped areas arranged in the second conductivity type lightly doped well and the first conductivity type lightly doped well. The cascade structure neighbors a second conductivity type well, wherein there are three heavily doped areas arranged in the second conductivity type well. The suppressor further comprises a plurality of deep isolation trenches arranged in the first conductivity type substrate and having a depth greater than depths of the second conductivity type lightly doped well, the second conductivity type well and the first conductivity type lightly doped well.

Abstract: Methods and apparatus to clamp overvoltages for inductive power transfer systems are described herein. An example overvoltage protection circuit is described, including a first terminal configured to receive an alternating current signal for conversion to a second signal, a capacitor, a first switch configured to selectively electrically couple the capacitor to the first terminal based on an overvoltage detection signal to reduce an overvoltage on the second signal, and an overvoltage detector. The example overvoltage detector is configured to determine a signal level of the second signal and, in response to determining that the signal level of the second signal is greater than a threshold, to output the overvoltage detection signal to cause the switch to electrically couple the capacitor between the first terminal and a second terminal.

Abstract: A representative level-shifter comprises a dynamically biased current source circuit that receives a first voltage, a first and a second unidirectional current-conducting devices, a first and a second pull-down devices, and a pull-up device. The first and second unidirectional current-conducting devices are coupled to the dynamically biased current source circuit. A voltage output of the level-shifter is located at a first node that is located between the current-constant circuit and the second unidirectional current-conducting device. The first and second pull-down devices are coupled to the first and second unidirectional current-conducting devices, respectively. The pull-up device receives a second voltage and is coupled to the dynamically biased current source circuit and the first unidirectional current-conducting device.

Abstract: An integrated circuit 2 includes a receiver circuit 4 for receiving an input signal PAD and converting this to an output signal OUT. Conduction path circuitry 14 couples an input 10 to a first node 16. Buffer circuitry 18 is coupled between the first node 16 and an output 12 carrying the output signal Out. The conduction path circuitry comprises a first PMOS transistor 24 and a second PMOS transistor 26 connected between the input 10 and the first node 16. A first NMOS transistor 28 is connected between the input 10 and the first node 16. The gate of the second PMOS transistor 26 is coupled to the output 12 to directly receive the output signal and thereby achieve rapid cut off of the charging of the node 16 when the input voltage rises beyond a certain level which switches the buffer circuitry 18.

Abstract: In an embodiment, the circuit includes: a first switch serially connected to a first discharge resistor, the first switch and the first discharge resistor connected to a positive DC bus; a second switch serially connected to a second discharge resistor, the second switch and the second discharge resistor connected to a negative DC bus; and a capacitor bank for storing a positive and a negative DC voltage, the capacitor bank including a first capacitor in parallel with the first switch and the first discharge resistor, and a second capacitor in parallel with the second switch and the second discharge resistor, wherein the first switch operates independently from the second switch to discharge the positive DC voltage through the first discharge resistor and the second switch operates independently from the first switch to discharge the negative DC voltage through the second discharge resistor.

Abstract: Methods and devices of the invention include an electrostatic discharge (ESD) protection circuit. This circuit includes rise time dependent activation circuitry capable of detecting a slew rate of an input signal and capable of determining whether the slew rate of the input signal is greater than a threshold value. For an ESD event said activation circuitry generates a trigger signal. Additionally, the activation circuitry is coupled with the ESD dissipation duration control circuitry which is further coupled with an ESD dissipation circuit. This arrangement enabling the duration control circuit to be activated by the trigger signal which responds by producing an activation signal that activates the ESD dissipation circuitry and that controls the length of time the dissipation circuit remains active. The ESD dissipation circuitry includes a shunt that redirects the ESD energy away from the protected internal circuit.

Abstract: An ESD protection system providing extra headroom at an integrated circuit (IC) terminal pad. The system includes an ESD protection circuit having one or more first diodes coupled in series between the supply voltage and terminal pad, and a second diode coupled to ground. One or more third diodes are coupled in series between the terminal pad and second diode, and are configured to permit a voltage on the interconnection nodes between the one or more third diodes and second diode different from ground. The one or more third diodes include an n+ on an area of P-substrate. A deep N-well separates the area of P-substrate from a common area of P-substrate, which is coupled to ground. The allowable signal swing at the terminal pad is increased to greater than supply voltage plus 1.4 V. The ESD protection circuit is useful for, among other things, relatively low supply voltage ICs.

Abstract: A low forward voltage drop transient voltage suppressor utilizes a low-reverse-voltage-rated PN diode electrically connected in parallel to a high-reverse-voltage-rated Schottky rectifier in a single integrated circuit device. The transient voltage suppressor is ideally suited to fix the problem of high forward voltage drop of PN diodes and high leakage of low reverse breakdown of Schottky rectifiers. The low-reverse-voltage PN rectifier can be fabricated through methods such as 1) double layers of epi (with higher concentration layer epi in the bottom) or 2) punch through design of PN diode by base with compression.

Abstract: A semiconductor device for electrostatic discharge (ESD) protection includes a silicon controlled rectifier (SCR) including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, a first p-type region formed in the first well to serve as an anode, and a first n-type region partially formed in the second well to serve as a cathode, a p-type metal-oxide-semiconductor (PMOS) transistor formed in the first well including a gate, a first diffused region and a second diffused region separated apart from the first diffused region, a second n-type region formed in the first well electrically connected to the first diffused region of the PMOS transistor, and a second p-type region formed in the substrate electrically connected to the second diffused region of the PMOS transistor.

Abstract: An electronic device includes an electronic component and a protection circuit configured to protect the component from overvoltages. A control circuit is configured to inhibit a part of the protection circuit in the presence of a test voltage across terminals of the component.

Abstract: A voltage measuring circuit includes an under-voltage measuring circuit and an over-voltage measuring circuit. The under-voltage measuring circuit includes a first voltage comparator, a first zener diode, and a first light emitting diode. An inverting input of the first voltage comparator is connected to a cathode of the first zener diode. An output of the first voltage comparator is connected to a cathode of the first light emitting diode. The over-voltage measuring circuit includes a second voltage comparator, a second zener diode, and a second light emitting diode. A non-inverting input of the second voltage comparator is connected to the cathode of the second zener diode. An output of the second voltage comparator is connected to a cathode of the second light emitting diode.

Abstract: An ESD protection circuit includes a first voltage clamp, connected between a first voltage supply node and a second voltage supply node of the circuit, and a second voltage clamp, connected between the second voltage supply node and a voltage return of the circuit. The first voltage supply node is adapted to receive a first voltage which is greater than a prescribed gate oxide reliability potential of the circuit. The second voltage supply node is operative to receive a second voltage which is less than the first voltage. The first voltage clamp is operative to clamp the first voltage on the first voltage supply node to a first value during an ESD event between the first and second voltage supply nodes, and the second voltage clamp is operative to clamp the second voltage on the second voltage supply node to a second value during an ESD event between the second voltage supply node and the voltage return.

Abstract: An embedded bridge rectifier is disclosed. By reconfiguring and reconnecting internal ESD protection circuits originally installed at two bonding pads of integrated circuits, the invention not only saves hardware cost of conventional external bridge rectifiers, but also reduces the space of print circuit boards.

Abstract: Included are: a circuit-specific printed circuit board to be a circuit board that generates a power supply voltage; a first diode that is connected in antiparallel with the transistor and is configured so as to be capable of passing a current through a path to circumvent the transistor; a second diode that is connected in series to the transistor and prevents a current flow through a parasitic diode formed on the transistor; a protection circuit that is connected in parallel with the second diode to protect the second diode from a high voltage breakdown, and is formed on a substrate different from the circuit-specific printed circuit board; and a cooling unit that is joined to the protection circuit outside the circuit-specific printed circuit board and cools the protection circuit.

Abstract: A semiconductor device, which is connected to a protected device and protects a protected device, includes a semiconductor layer provided on an insulating film; a plurality of source layers which is formed in the semiconductor layer and extends in a first direction; a plurality of drain layers which is formed in the semiconductor layer and extends along with the source layers; a plurality of body regions which is provided between the source layers and the drain layers in the semiconductor layer and extends in the first direction; and at least one body connecting part connecting the plurality of body regions, wherein a first width between the source layer and the drain layer at a first position is larger than a second width between the source layer and the drain layer at a second position, the second position is closer to the body connecting part than the first position.

Abstract: A circuit for protecting an electronic device from excessive voltages applied to an input or output terminal includes a solid state relay coupling the electronic device to the terminal. The solid state relay may include an opto-transistor coupled between the electronic device and the terminal and a light emitting diode optically coupled to the opto-transistor. The solid state relay is coupled in series with a current limiting device, such as one or more enhancement mode field effect transistors. A voltage detector coupled to the terminal detects a voltage larger than a specific value and causes current to flow thorough the light emitting diode, thereby interrupting the coupling between the terminal and the electronic device. The voltage detector may be coupled between two spaced-apart connections to the coupling path between the terminal to the electronic device so that the voltage detector avoids diverting current from the coupling path.

Abstract: A system for power amplifier over-voltage protection includes a power amplifier configured to receive a system voltage, a bias circuit configured to provide a bias signal to the power amplifier, and a power amplifier over-voltage circuit configured to interrupt the bias signal when the system voltage exceeds a predetermined value, while the system voltage remains coupled to the power amplifier.

Abstract: An overvoltage protector having a housing and at least one overvoltage limiter arranged in the housing, especially a gas-filled surge arrester (1), a suppressor diode (2) or a varistor. The functional ability and the state of the overvoltage protector can be controlled during operation by associating a monitoring component with the overvoltage limiter which detects a current (i) flowing over the overvoltage limiter component, and by providing an evaluation unit that evaluates the signal of the monitoring component.

Abstract: The invention relates to a speed controller comprising: at the input, a rectifier module (12) in order to generate, on a power bus (10, 11), a direct voltage from an alternating voltage available on an electrical supply network (A), a bus capacitor (Cb) connected between a positive line and a negative line of the power bus, an inverter module (13) supplied by the power bus and controlled to deliver an alternating voltage to an electric load (2), a device (14) for protecting the controller consisting of a first electronic switch of the JFET transistor type (T1) and a second electronic switch (T2) mounted on the power bus, in parallel with the JFET transistor (T1).

Abstract: A fan system is electrically connected to a power source, and the fan system includes a power reverse protection apparatus, a voltage regulator, a driver, and a fan. The power reverse protection apparatus, electrically connected to the power source, includes a voltage regulator switch and an activating device. The voltage regulator switch receives an input signal and outputs a first output signal according to the input signal. The activating device is electrically connected to the power source and the voltage regulator switch for receiving the input signal and the first output signal, respectively. The activating device outputs a second output signal to the fan according to the first output signal. The voltage regulator is electrically connected to the power source for receiving the input signal from the power source and outputting a regulating signal according to the input signal.

Abstract: An over-voltage protection system is connected between a power supply and two working circuits of an electronic device, and includes a first over-voltage protection circuit, a second over-voltage protection circuit, and a voltage load circuit. The over-voltage protection system detects voltage of the power supply, isolates the power supply from a first working circuit when the power supply exceeds a first predetermined voltage value, and isolates the power supply from a second working circuit when the voltage of the power supply exceeds a second predetermined voltage value and is lower than the first predetermined voltage value. The voltage load circuit bears partial voltage of the power supply to provide necessary power to the second working circuit when the voltage of the power supply exceeds a second predetermined voltage value and is lower than the first predetermined voltage value.

Abstract: A low forward voltage drop transient voltage suppressor utilizes a low-reverse-voltage-rated PN diode electrically connected in parallel to a high-reverse-voltage-rated Schottky rectifier in a single integrated circuit device. The transient voltage suppressor is ideally suited to fix the problem of high forward voltage drop of PN diodes and high leakage of low reverse breakdown of Schottky rectifiers. The low-reverse-voltage PN rectifier can be fabricated through methods such as 1) double layers of epi (with higher concentration layer epi in the bottom) or 2) punch through design of PN diode by base with compression.

Abstract: A driver circuit includes a driver module having a first transistor for receiving a driver voltage signal. In response to the driver voltage signal, the first transistor conducts current through an electronic device. A protection module includes a second transistor in electrical communication with the first transistor for receiving a logic voltage signal and for inhibiting current flow through the first transistor in response to receiving the logic voltage signal. The protection module further includes a digital logic gate having at least one input in electrical communication with the first transistor for detecting a short-circuit voltage signal. At least one output of the digital logic gate is in electrical communication with the second transistor for outputting the logic voltage signal in response to receiving the short-circuit voltage signal.

Abstract: An integrated electrostatic discharge (ESD) protection circuitry for a signal electrode. Coupled in shunt between the signal electrode and the positive and negative power supply electrodes are opposing sets of multiple diodes coupled in series. Each set includes a diode across which is applied a nominal reverse bias voltage. These opposing reverse bias voltages are maintained at substantially constant predetermined nominal magnitudes in relation to the voltage at the signal electrode, thereby ensuring minimal leakage current via the signal electrode over the full dynamic range of the signal.

Abstract: A semiconductor device which can achieve high breakdown voltage and high ESD tolerance of a current drive output terminal at the same time, and can quicken the response speed of a current flowing through the current drive output terminal. The inventive semiconductor device is provided, between the current drive output terminal and a first transistor or a low breakdown voltage element, with a second transistor having a breakdown voltage higher than that of the first transistor or that of the low breakdown voltage element. Furthermore, the inventive semiconductor device is provided with a diode having an anode connected with a path between the first transistor or the low breakdown voltage element and the second transistor, and a cathode connected with an ESD protection circuit.

Abstract: An embodiment of the invention relates to a switch-mode power converter including an inductor and an external rectifying diode. A series arrangement of a resistor and a switch are coupled in parallel with the external rectifying diode. The resistor and the switch enable continuous conduction mode, even at substantially no output current. A comparator senses a current level in the resistor. When the current level crosses a threshold level, the power converter is shut down. The current level is sensed with a second resistor coupled to a current source to produce a current sensing arrangement dependent on a ratio of resistances. Advantageously, the current level is sensed with clamp circuits coupled to the comparator, each clamp circuit including a series circuit arrangement of a field-effect transistor with a gate coupled to a voltage source.

Abstract: Embodiments of an output driver comprising a switching module configured to multiplex a protection transistor between a protection mode and a current mirror mode are disclosed herein. The output driver may operate at high speed with voltages above a maximum threshold voltage specification for the output driver. Additional variants and embodiments may also be disclosed and claimed.

Abstract: A high voltage tolerance circuit includes a first transistor, a second transistor, a third transistor, and a latch-up device. The first transistor and the second transistor are controlled by a control signal. The gate of the third transistor is coupled to a ground through the first transistor. The gate of the third transistor is coupled to an I/O pad through the second transistor. The third transistor is coupled between a power supply and a node. The latch-up device is coupled between the node and the I/O pad.

Abstract: A modified CMOS switch, composed of parallel N-channel and P-channel transistors, is placed between the pad and the input buffer and/or output devices. The applied pad voltage relative to VDD determines the configuration of the switch, and also, the P-channel floating-well bias-voltage. For the applied pad voltage above VDD, only the N-channel device is on and the P-channel device is off. In this configuration the N-channel limits the input voltage on the buffer side to (VDD?VTN), and therefore, acts as the over-voltage protection device. For pad voltages at and below VDD, both the N-channel and the P-channel devices are on, and the voltage-levels on both sides of the protection structure are the same.

Abstract: A DC-DC converter including: a switch, having a control terminal receiving a control signal, and a conduction terminal supplying a current; a load, coupled to the conduction terminal of the switch and selectively receiving the current; a control circuit, receiving a clock signal and generating the control signal in synchronism with the clock signal; an overcurrent sensor, coupled to the switch so as to monitor an electrical quantity correlated to the current and to output a protection signal in presence of overcurrent; moreover including overcurrent-protection circuitry, receiving the protection signal and the clock signal and generating a disabling signal for the control circuit if delay between an overcurrent detection and the clock signal is shorter than a detection time.

Abstract: A motor sensing circuit with transient voltage suppression includes a sensing unit and an impulse absorber. The sensing unit has an electrical switch generating a pulse sensing signal when switching and a signal output terminal electrically connecting to the electrical switch and outputting said pulse sensing signal. The impulse absorber has a first terminal connecting to the signal output terminal of the sensing unit and a second terminal being grounded. Consequently, the impulse absorber is able to provide a route for a transient current to be drained away, with the transient current being generated by an impulse inputted the motor sensing circuit through the signal output terminal.

Abstract: An overvoltage protection circuit is provided for protecting a load against overload damage, including a gross protection device for dissipating the major portion of the energy of the trouble event, a plurality of fine protection devices for limiting the remaining portion of the trouble energy to a safe value, and a diagnostic arrangement for determining the operating condition of the destructible gross and fine protection devices. A trouble event identifying arrangement compares with a reference voltage standard the residual output voltage existing between a pair of output terminals of the circuit, and a display arrangement indicates whether or not this residual output voltage meets the reference voltage standard.

Abstract: A main transistor and a reverse current prevention transistor are provided in series between an input terminal and an output terminal. An input diode is provided between a connection point of the reverse current prevention transistor and the main transistor and a reference voltage terminal in such a direction that the anode becomes the reference voltage terminal side. A control unit controls the gate voltage of the main transistor according to a DC voltage. The reverse current prevention transistor is arranged in such a direction that the anode of its body diode becomes the input terminal side. The reverse current prevention transistor is biased to be turned on in a normal state that the input terminal becomes high potential and the reference voltage terminal becomes low potential.

Abstract: A bi-directional over-voltage protection circuit and a method for blocking current flow therein. The bi-directional over-voltage protection circuit comprises a regulator coupled to a lockout circuit, wherein the regulator and the lockout circuit are coupled for receiving an input signal and are coupled to a charging control circuit. A reverse path control circuit has an input coupled for receiving a control signal and an output coupled to the charging control circuit. A multi-transistor switching circuit is coupled to the forward control circuit. Preferably, the gate of each n-channel MOSFET is coupled to the charging control circuit, the drains are coupled together, and the source of one of the n-channel MOSFETS is coupled to an input and the source of the other n-channel MOSFET is coupled to an output of the bi-directional over-voltage protection circuit.

Abstract: Circuit nodes are identified which, in unpowered mode, can be charged with positive or negative charges but cannot be discharged. Then protective elements are added to allow the discharge of these nodes. These elements do not affect the operation of the circuit in powered mode. Discharges of the two polarities are handled, positive and negative. The circuit is thus more resistant to ESD and passes CDM tests.

Abstract: An overvoltage protection circuit is provided for protecting a load against overload damage, including a coarse protection device for dissipating the major portion of the energy of the trouble event, a plurality of fine protection devices for limiting the remaining portion of the trouble energy to a safe value, a diagnostic arrangement for determining the operating condition of the destructible fine protection devices, and a disconnect arrangement for disconnecting from the protection circuit at least one of the fine protection devices that has been determined to be faulty. A trouble event identifying arrangement compares with a reference voltage standard a measured voltage existing at a measuring junction between the fine protection devices, and generates a fault signal in the event of destruction of a fine protection device. A display arrangement indicates whether or not a fine protection device has been determined to be faulty.

Abstract: Provided is a semiconductor apparatus which includes a power transistor that is placed between an input terminal and an output terminal, a temperature detection diode that has a cathode connected to the input terminal and an anode connected to the output terminal, a current amplifier that outputs a detection current generated by amplifying a backward leakage current flowing from the cathode to the anode of the temperature detection diode, a first conversion resistor that outputs an overheat detection signal generated by converting the detection current into a voltage, a gating circuit that performs gating of a control signal according to the overheat detection signal, and a driver circuit that outputs a drive signal to a control terminal of the power transistor based on an output signal of the gating circuit.

Abstract: A semiconductor power conversion apparatus capable of protecting an IGBT from an overvoltage by supplying a sufficient gate current to the gate of the IGBT. The IGBT is protected from the overvoltage by connecting clamping elements connected in series between a collector of the IGBT and the gate thereof, and by connecting a resistor to each of different junction points between the clamping elements connected in series.

Abstract: An I/O regulating circuitry is provided. The I/O regulating circuitry omits the ESD device in a CMOS process with a minimized critical dimension to reduce chip size while still maintaining electrostatic discharge immunity. The I/O regulating circuitry is applied in MLC flash memory applications and the flash controller thereof.

Abstract: When a malfunction of an ungrounded drive electric system including first and second ungrounded power supplies, an inverter, and a motor which is energized by the first and second ungrounded power supplies through the inverter, i.e., an erroneous opening of switches of a battery, is detected, switches of an insulation resistance detector are opened to insolate the insulation resistance detector from the ungrounded drive electric system.

Abstract: A power integrated circuit with internal over-voltage protection includes a power transistor monolithically integrated with a sense element and a control circuit. The power transistor is connected to an output terminal that is connected (or is connectable) to an external load. The sense element is connected to the output terminal in parallel with the power transistor. The sense element is constructed to be similar to the power transistor except that the sense element has a lower breakdown voltage. When the voltage of the output terminal exceeds the breakdown voltage of the sense element a breakdown current flows from the gate of the sense element to the control circuit. Inside the control circuit, a comparator or other over-voltage protection circuit monitors this feedback and controls the power transistor accordingly to protect the power integrated circuit from damage.

Abstract: An electric connection box 10 comprises an FET 32 for connection with a power supply B, a substrate side conduction path 18 connected with the FET 32 and connecting the FET 32 with a load L, a diode element D connected with the substrate side conduction path 18 electrically and to transfer heat and having a PN junction, and a CPU 19 for judging whether the voltage drop value between the input/output terminals 25 and 26 of the diode element D is larger than a threshold or not and delivering an off-command signal to the FET 32 if a judgment is made that the voltage drop value is smaller than the threshold.