Abstract: In one embodiment, a protection circuit includes a linear regulator remains enabled during a portion of a time while limiting an output voltage of the linear regulator to a first value.

Abstract: Device for protecting an integrated circuit, comprising a device for detecting a latch-up condition, and a supply voltage control device for controlling a supply voltage of the integrated circuit, to modify a parameter of the supply voltage of the integrated circuit in order to prevent the latch-up from becoming permanently established.

Abstract: A system and method for efficient input/output (I/O) port overvoltage protection of a high-speed port. An interfacing system for connecting peripheral devices to a computing system comprises ports for conveying serial communications bidirectional signals and an overvoltage protection circuit. The protection circuit prevents an overvoltage condition on one port in response to an overvoltage event on a corresponding second port. In one embodiment, the interfacing system connects USB peripheral devices to an automotive infotainment system comprising an automotive battery potiential greater than a USB power supply. In addition, the overvoltage protection circuit is able to transmit signals between the two ports without signal attenuation defined by an industry standard specification such as Universal Serial Bus (USB) Implementers Forum (IF) eye pattern diagram test.

Abstract: Even when one of IGBTs fails in a semiconductor power converter apparatus in which a plurality of semiconductor elements are connected in parallel, the remaining IGBT(s) is prevented from failing with a simple circuit configuration. The semiconductor power converter apparatus includes: a semiconductor power conversion circuit in which a first IGBT having a temperature sensing unit and a second IGBT having a current sensing unit are connected in parallel, for causing the first and second semiconductor elements to perform switching operations; an overheat protection circuit for performing overheat protection for the first and second IGBTs based on temperature information obtained from the temperature sensing unit of the first IGBT; and an overcurrent protection circuit for performing overcurrent protection for the first and second IGBTs based on current information obtained from the current sensing unit of the second IGBT.

Abstract: The present patent application describes an approach to the protection of voltage sensitive instruments using a protection circuit that may be easily integrated in a three-terminal device, and which overcomes the drawbacks of previous approaches. The protection circuit of the invention performs very fast against overvoltages (in a few nanoseconds), automatically switching to a low impedance conduction state as soon as the overvoltage situation ends. It also minimizes insertion losses, shows a very low level of thermal noise and allows for obtaining broad bandwidths due to its low serial impedance in the conduction state. Furthermore, it does not require any power source or control signal.

Abstract: An IC power protection circuit functions as a surge protection circuit and reverse connection protection circuit. The IC power protection circuit includes an error amplification circuit, positioned and integrated within an integrated circuit and a transistor positioned as a stand-alone element that is separate from the integrated circuit. The integrated circuit includes a sensor signal processing circuit that processes a signal of a sensor. A transistor protects the integrated circuit against a surge voltage from a battery terminal. A resistor is positioned between an output terminal of an error amplifier and a base terminal of the transistor to provide reverse connection protection. Another resistor is connected between a ground and a connection point between the above resistor and the output terminal to provide overvoltage protection for the integrated circuit. A starting resistor is connected between a collector and base of the transistor.

Abstract: A semiconductor device capable of preventing an electrostatic surge without increasing a leak current. In the semiconductor device, a protection circuit for protecting an internal circuit is provided between a source line and a ground line. The protection circuit has a protection transistor of which the drain is connected to the source line and the source and gate are connected to the ground line. The protection transistor is configured by integrally forming two types of transistor structural portions. The latter of the transistor structural portions is longer than the former thereof in gate length. In addition, the sum of gate widths of the latter transistor structural portions is larger than the sum of gate widths of the former transistor structural portions.

Abstract: Various embodiments of an input protection circuitry may be configured with a variable tripping threshold and low parasitic elements, which may prevent a signal from propagating into the protected equipment/device if the voltage of the input signal exceeds a certain limit. The input protection circuit may operate to protect a measurement instrument, which may be an oscilloscope, early in the signal path leading into to the instrument, to avoid exposing sensitive circuitry to damaging voltage levels, and without introducing significant parasitic elements that would degrade the performance of the instrument. The protection circuit may be configured to include clamping to provide protection during the circuit response delay time. The input protection threshold of the protection circuit may be adaptive to a selected voltage range on the instrument without trading-off instrument performance and features.

Abstract: In a dual direction ESD protection structure, first and second NMOS devices are serially connected back-to-back by connecting their drains or their sources using a common floating interconnect, while ensuring that the devices remain isolated from each other.

Abstract: An over-voltage protection circuit assembly includes a connector and an over-voltage protection circuit. The connector includes a power terminal. The over-voltage protection circuit includes a voltage input terminal, and a voltage output terminal. The voltage output terminal connected to the voltage input terminal via a resistor. A relay includes an inductance coil and a switch. The inductance coil is connected between the voltage input terminal and ground. A warning unit is connected in series with the switch of the relay between the voltage input terminal and ground. A voltage regulating diode is connected between the voltage output terminal and ground. The anode of the voltage regulating diode is connected to ground, and the cathode of the voltage regulating diode is connected to the voltage output terminal.

Abstract: A current protection circuit that uses a sequence of bipolar transistors to provide or draw current from a protected circuit node. An initial bipolar transistor has its emitter terminal coupled to the protected circuit node, with its collector terminal coupled to a current source or sink. One or more additional intermediary bipolar transistors are also provided in the sequence. Each additional intermediary bipolar transistor has its emitter terminal coupled to the base terminal of the previous bipolar transistor in the sequence, and has its collector terminal coupled to the current source or sink. To complete the sequence, a reverse-biased diode is coupled between the base terminal of the final intermediary bipolar transistor and the current source or sink. This allows for effective triggering of current protection for a protected circuit node without requiring a zener diode.

Abstract: An ESD protection system providing extra headroom at an integrated circuit (IC) terminal pad. The system includes an ESD protection circuit having one or more first diodes coupled in series between the supply voltage and terminal pad, and a second diode coupled to ground. One or more third diodes are coupled in series between the terminal pad and second diode, and are configured to permit a voltage on the interconnection nodes between the one or more third diodes and second diode different from ground. The one or more third diodes include an n+ on an area of P-substrate. A deep N-well separates the area of P-substrate from a common area of P-substrate, which is coupled to ground. The allowable signal swing at the terminal pad is increased to greater than supply voltage plus 1.4 V. The ESD protection circuit is useful for, among other things, relatively low supply voltage ICs.

Abstract: A protection device detects a temperature in a predetermined monitoring place in an electronic apparatus 3 to protect the electronic apparatus 3, and includes an oscillating circuit 20 for generating a clock signal Vck having a predetermined cycle and a predetermined ON time, and a temperature detection circuit 16 for detecting the temperature in the monitoring place during the ON time of the clock signal Vck. The protection device shuts off supply of electric power to the electronic apparatus 3, when the temperature in the monitoring place exceeds a predetermined temperature.

Abstract: An electronic device under test (DUT) may be incorporated into a circuit having a voltage limiter connected in parallel with the DUT. The circuit includes a controlled current source having an output current connected in series with the DUT. The voltage limiter is characterized in that, when the output current is such that the voltage across the DUT (Vdut) would exceed a particular maximum voltage Vmax, without the voltage limiter in place, at least a portion of the output current flows through the voltage limiter, so as to limit Vdut to be less than or equal to Vmax. When the output current is such that Vdut would be less than or equal to Vmax, current does not flow through the voltage limiter. The circuit may include a plurality of DUTs, each DUT connected in series with the output current of a controlled current source, with a voltage limiter connected in parallel with each DUT.

Abstract: The present invention provides a protection circuit coupled to a tip lead and a ring lead in a subscriber line interface circuit formed on a silicon substrate. The protection circuit includes first and second diodes formed on the silicon substrate and coupled to the tip lead and the ring lead, respectively. The first and second diodes are configured to provide a path from the tip lead or the ring lead to ground in response to a positive voltage at the tip lead or the ring lead. The protection circuit also includes a silicon-controlled rectifier formed on the silicon substrate and configured to provide, in response to a negative voltage at the tip lead or the ring lead, a path from the tip lead or the ring lead to ground via the silicon-controlled rectifier.

Abstract: A protection circuit and a photoelectric conversion device are provided, each of which includes a first wiring, a second wiring, a first switch, a second switch, a capacitor, and a comparing circuit configured to generate a signal corresponding to a potential of the first wiring and a potential of the second wiring, and supply the signal to the first switch and the second switch. The first wiring is electrically connected to a first terminal of the first switch, and the second wiring is electrically connected to a first terminal of the second switch. A second terminal of the first switch is electrically connected to a first electrode of the capacitor, and a second terminal of the second switch is electrically connected to a second electrode of the capacitor.

Abstract: The invention relates to a speed controller comprising: at the input, a rectifier module (12) in order to generate, on a power bus (10, 11), a direct voltage from an alternating voltage available on an electrical supply network (A), a bus capacitor (Cb) connected between a positive line and a negative line of the power bus, an inverter module (13) supplied by the power bus and controlled to deliver an alternating voltage to an electric load (2), a device (14) for protecting the controller consisting of a first electronic switch of the JFET transistor type (T1) and a second electronic switch (T2) mounted on the power bus, in parallel with the JFET transistor (T1).

Abstract: In one embodiment, a protection device is used to protect a circuit. The protection device has a maximum rated power dissipation that is less than a maximum rated power dissipation of the circuit that is being protected.

Abstract: An integrated circuit includes a first RF port and a second RF port. A limiter section is disposed between the first RF port and the second RF port and a detector section coupled to an RF signal path between the first RF port and the second RF port configured to detect a power level of an input signal, and coupled to the limiter section.

Abstract: A process control system (1) comprises at least one process control computer (2) and field units (4) connected thereto via a bus system. An, in particular, intrinsically safe data transmission device (5) is connected between the process control computer and the assigned field units. This data transmission device comprises a data adaptation device (6) and a data distributing device (7). In order to be able to connect more field units per data adaptation device while simultaneously reducing the costs per field unit, the data adaptation device (6) and its assigned supply devices (8) have an explosion-proof design, and each supply device is connected to the data distributing devices via an explosion-proof line, whereby these data distributing devices or field units connected thereto have a barrier device for limiting the applied power.

Abstract: A voltage control circuit includes first, second and third transistors, a relay, and first, second, and third resistors. The emitter of the first transistor is connected to a first power supply, the collector of the first transistor is connected to a first contact of the relay, a second contact of the relay is grounded; the collector of the third transistor is connected to the first power supply via the third resistor, and the emitter of the third transistor is grounded. The first and second resistors are connected in series between the positive electrode of the second power supply; the base of the second transistor is connected to a node between the first and second resistors, the collector of the second transistor is connected to the base of the third transistor, and the emitter of the second transistor is connected to the first power supply.

Abstract: A thin film circuit substrate is provided with a voice-output-section driving section, formed of a thin film layer on an insulative substrate, for driving a voice output section. An antisurge section, provided on a wiring between the voice-output-section driving section and an output terminal section thereof, includes an antisurge element. When a surge voltage is applied to the wiring, the antisurge element, monolithically formed on the thin film circuit substrate, connects the wiring to the ground so as to pass a current (surge current), generated by the surge voltage applied to the wiring, to the ground. This makes it possible to provide a thin film circuit substrate which is monolithically provided with a function which can protect a circuit section when a voltage exceeding a predetermined range is applied to the wiring linking the circuit section with an input terminal section or an output terminal section.

Abstract: A current shut-off overload protection circuit useful for fluorescent lamp ballast protection and the like has at least one power transistor for supplying a load current to a circuit load, a protection circuit comprising a current sensing resistance connected for developing a voltage drop related to the circuit load, and a switching diode having a control input operative for turning off the power transistor by removing a bias level, as by grounding the transistor base, responsive to a preset level of the voltage drop such that the load current to the load is switched off upon the load current exceeding a maximum acceptable load current represented by a preset level of the voltage drop.

Abstract: An electronic circuit configuration for connecting an active rotary speed sensor.

Abstract: Methods and apparatus for over-voltage protection of device inputs are disclosed. An example apparatus to protect a device from an over-voltage condition disclosed herein comprises a switch coupled between a device input and at least one component of the device, and a voltage compensator to pull a control input of the switch to a voltage associated with the device input to open the switch to protect the device component from the over-voltage condition.

Abstract: A precise over-voltage comparator exhibits zero-waiting-current characteristics during normal working conditions. An NMOS transistor is used in conjunction with other circuit elements to regulate the over-voltage comparator. For normal power supply voltages, the comparator stays in standby status and does not consume quiescent current.

Abstract: A width and a length of the electrostatic discharge (ESD) protection circuit are reduced by changing a connection structure of the electrostatic discharge protection circuit. The ESD protection circuit includes a plurality of gate electrodes disposed between odd signal lines and even signal lines adjacent to the odd signal lines among the signal lines; source/drain electrode pairs each disposed on a respective one of the gate electrodes to form a plurality of transistors; and connection nodes parallel to the source/drain electrode pairs, each connection node adjacent to a respective one of the source/drain electrodes pairs and on a respective one of the gate electrodes, wherein each of the connection nodes is directly connected to the source/drain electrode pair of an adjacent transistor and the gate electrode formed below the source/drain electrode through a contact part.

Abstract: A main transistor and a reverse current prevention transistor are provided in series between an input terminal and an output terminal. An input diode is provided between a connection point of the reverse current prevention transistor and the main transistor and a reference voltage terminal in such a direction that the anode becomes the reference voltage terminal side. A control unit controls the gate voltage of the main transistor according to a DC voltage. The reverse current prevention transistor is arranged in such a direction that the anode of its body diode becomes the input terminal side. The reverse current prevention transistor is biased to be turned on in a normal state that the input terminal becomes high potential and the reference voltage terminal becomes low potential.

Abstract: An ESD protection circuit for over-voltage signal bus is disclosed that includes a diode circuit that is electrically connected to a pseudo power supply circuit. The pseudo power supply circuit includes a pseudo first power supply line coupling to an actual first power supply line having a first voltage supply level and a pseudo second power supply line coupling to an actual second power supply line having a second voltage supply level. The pseudo first power supply line and the pseudo second power supply line are clamped by an ESD clamping circuit such that the ESD protection circuit discharges voltage when an ESD event occurs, and does not interfere with the internal circuit when an over-voltage occurs.

Abstract: An over-voltage protection circuit assembly includes a connector and an over-voltage protection circuit. The connector includes a power terminal. The over-voltage protection circuit includes a voltage input terminal, and a voltage output terminal. The voltage output terminal connected to the voltage input terminal via a resistor. A relay includes an inductance coil and a switch. The inductance coil is connected between the voltage input terminal and ground. A warning unit is connected in series with the switch of the relay between the voltage input terminal and ground. A voltage regulating diode is connected between the voltage output terminal and ground. The anode of the voltage regulating diode is connected to ground, and the cathode of the voltage regulating diode is connected to the voltage output terminal.

Abstract: A protective circuit for protecting an electronic circuit from transient excess voltages, in particular, a series connection of at least two voltage-limiting circuit components being provided between a first connection terminal and a second connection terminal of an input of the protective circuit, each of the two voltage-limiting circuit components having at least one semiconductor element. At least one output terminal is provided at an output for connecting the electronic circuit to be protected to the protective circuit, the output terminal being connected to a circuit node disposed between the two voltage-limiting circuit components.

Abstract: The present invention provides an ESD protection device having at least one diode in a well of first conductivity type formed in a substrate of second conductivity type. The circuit further includes a guard band of the first conductivity surrounding at least a portion of the diode, thus forming an NPN transistor between diode cathode, the substrate and the guard-band.

Abstract: An overvoltage protection circuit for protecting low voltage, high speed digital communication lines. The circuit is integrated into a semiconductor chip and includes a diode bridge, a transient voltage suppressor (TVS) device and resistors through which a bias voltage can be applied to the TVS device to reduce the capacitance hereof.

Abstract: A high-voltage detecting circuit for saving power in a standby mode is provided. The high-voltage detecting circuit includes a high-voltage detecting module, a switch module and a control module. The high-voltage detecting module is composed of several resistors for detecting a high-voltage power supply. A control terminal of the control module is controlled by the power supply to switch off the switch module when the power supply stays at the standby mode, ensuring that the power loss of the high-voltage detecting module is eliminated.

Abstract: A modular protection circuit can protect a first terminal and a second terminal of a first device. The circuit comprises a load device which has a third terminal and a fourth terminal with the third terminal for connection to a first voltage. A first diode is provided, with the first diode having a first cathode and a first anode with the first cathode connected to the fourth terminal and the first anode connected to the first terminal. A second diode is provided with the second diode having a second cathode and a second anode with the second cathode connected to the fourth terminal and the second anode connected to the second terminal. A third diode is provided with the third diode having a third cathode and a third anode with the third cathode connected to the first terminal and the third anode connected to a second voltage.

Abstract: A transient voltage suppressing (TVS) circuit with uni-directional blocking and symmetric bi-directional blocking capabilities integrated with an electromagnetic interference (EMI) filter supported on a semiconductor substrate of a first conductivity type. The TVS circuit integrated with the EMI filter further includes a ground terminal disposed on the surface for the symmetric bi-directional blocking structure and at the bottom of the semiconductor substrate for the uni-directional blocking structure and an input and an output terminal disposed on a top surface with at least a Zener diode and a plurality of capacitors disposed in the semiconductor substrate to couple the ground terminal to the input and output terminals with a direct capacitive coupling without an intermediate floating body region.

Abstract: A method and a circuit for protecting a transistor that controls the supply of an at least partially inductive load, including lowering the demagnetization voltage of the inductive load with respect to a demagnetization voltage set by a break-over component connected between a conduction terminal and the control terminal of the transistor.

Abstract: A current dissipation circuit that dissipates excess current to or from a circuit node when that monitored circuit node experiences abnormal voltage conditions, rather than having that excess current being dissipated through other protected circuitry. The current dissipation circuit may use single well technology, and may even provide reverse voltage protection without necessarily triggering more significant current dissipation. In another embodiment, the current dissipation circuit is provided by a series connection of at least five alternating p-type and n-type regions provided between the monitored circuit node and a current source or sink.

Abstract: An IC having inputs and outputs for a plurality of frequency bands from a high frequency band to a low frequency band is protected from electrostatic damage. A high-frequency section of the IC is provided with a protection circuit including diode-connected transistors connected by multiple stages. In addition, there are applied the transistors in which elements thereof are isolated by insulator that can prevent thyristor operation.

Abstract: MOSFETs are provided to connect the sensor input terminals of a ratiometric output sensor to a pair of power terminals, and the gate of each MOSFET is coupled to the opposite power terminal so that both MOSFETs are rendered conducting to power the sensor when a supply voltage of a predetermined polarity is connected across the power terminals but one of the MOSFETs is rendered non-conducting when a voltage of the opposite polarity is so applied. The MOSFET that is rendered non-conducting is oriented so that any internal source-drain diode does not bypass current around the MOSFET when voltage of the opposite polarity is applied. Optionally, over-voltage protection is provided by an input voltage sensor controlling the other MOSFET through a third MOSFET.

Abstract: A method for protecting against over voltage in a power supply comprises monitoring current amplitude and direction on an output connection of a power source that combines power from a plurality of power sources, and determining occurrence of a fault condition of the monitored power source based on the current amplitude and direction. In a fault condition of the monitored power source, operation of the monitored power source subject to the fault condition is terminated while continuing operation of the plurality of power sources exclusive of the monitored power source.

Abstract: An electrostatic discharge protection circuit device includes a discharge circuit, a trigger circuit and a trigger control circuit. The discharge circuit is connected to a predetermined circuit node of a semiconductor device, and makes discharge when surge voltage is applied to the circuit node. The trigger circuit triggers the discharge circuit to start a discharge operation by the discharge circuit. The trigger control circuit controls a trigger voltage at which the trigger circuit starts a discharge operation by the discharge circuit.

Abstract: A semiconductor device formed in a semiconductor substrate for dissipating electrostatic discharge and/or accumulated charge in an integrated circuit is provided. In one embodiment, the device comprises a semiconductor substrate; a plurality of layers of metal lines formed overlying the substrate; a plurality of via plugs through intermetal dielectric layers between the layers of metal lines and wherein the via plugs interconnect the metal lines; and a dummy pad formed over the plurality of layers of metal lines, the dummy pad having a diode connected thereto and to ground for providing a discharge path for the electrostatic discharge and/or accumulated charge.

Abstract: A lateral bipolar transistor is used to protect a passive radio frequency (RF) microelectronic circuit during electrostatic discharge (ESD) events. The microelectronic circuit receives a high frequency differential input signal across first and second pads. The lateral bipolar transistor includes an n-type emitter coupled to the first pad and an n-type collector coupled to the second pad. The emitter and collector are located in a p-well, which forms the base of the transistor. The p-well is located in an isolating n-well, which in turn, is located in a p-type substrate. The n-well is coupled to receive the VDD supply voltage and the p-substrate is coupled to a VSS reference voltage. A dielectric region can be located between the emitter and collector (in the p-well).

Abstract: An over-voltage protection arrangement (1) for protecting an electric device from over-voltages, the arrangement comprising an input voltage terminal (2), to be connected to a voltage feed, and an output voltage terminal (3), to be connected to the electric device to be protected, whereby the arrangement (1) is adapted to protect the electric device from voltages on the voltage feed deviating from a predefined threshold range, the arrangement further comprising a field effect transistor (4) connected in between the input terminal (2) and the output terminal (3) so as to enable an electric connection between said terminals (2, 3). The arrangement (1) is distinguished by: at least one trigger circuit (6a, 6b) being adapted to respond to a trigger voltage, a voltage on the voltage feed deviating from the threshold range, by controlling the field effect transistor (4) to throttle the electric connection between the input (2) and output (3) terminals.

Abstract: An apparatus for protecting a device against an over-voltage condition that is in excess of its breakdown voltage includes a detector for detecting the over-voltage condition and a protection circuit for protecting the device in response to detection of the over-voltage condition. The protection circuit may include a transmission gate and a PMOS transistor for producing a protection signal. The protection signal may be applied to a gate and/or a drain and/or a source and/or a well of the device such that a voltage across the device does not exceed the breakdown voltage. The protection signal may be derived from the over-voltage condition independent of whether a supply of power to the device is present.

Abstract: A current protection circuit that uses a sequence of bipolar transistors to provide or draw current from a protected circuit node. An initial bipolar transistor has its emitter terminal coupled to the protected circuit node, with its collector terminal coupled to a current source or sink. One or more additional intermediary bipolar transistors are also provided in the sequence. Each additional intermediary bipolar transistor has its emitter terminal coupled to the base terminal of the previous bipolar transistor in the sequence, and has its collector terminal coupled to the current source or sink. To complete the sequence, a reverse-biased diode is coupled between the base terminal of the final intermediary bipolar transistor and the current source or sink. This allows for effective triggering of current protection for a protected circuit node without requiring a zener diode.

Abstract: An ESD protection circuit is implemented for a semiconductor device having a first circuit system operating with a first power supply voltage and a first complementary power supply voltage, and a second circuit system operating with a second power supply voltage and a second complementary power supply voltage. The ESD protection circuit includes a first diode having an anode coupled to the first power supply voltage and a cathode coupled to a first node connecting the first circuit system and the second circuit system for preventing a crosstalk of current between the first power supply voltage and the second complementary power supply voltage. A first MOS transistor module is coupled between the first node and the first complementary power supply for selectively creating a current path from the first node to the first complementary supply voltage for dissipating an ESD current during an ESD event.

Abstract: A circuit is described that protects an integrated circuit from electrostatic discharges or electrical over-stress. The circuit arrangement has first and second protective elements connected in series between a connection of the integrated circuit and a supply voltage. When electrostatic discharges or electrical over-stress occurs, current flows through the conductive path formed through the first and second protective elements. A current path that contains a circuit element limits current through the first protective element is connected in parallel with the first protective element. The first protective element has blocking behavior when no electrostatic discharges or electrical over-stress occurs, a limited current flows through the current path and the second protective element.

Abstract: A low voltage detect circuit is provided herein for detecting when an external voltage (Vext) drops below a predetermined minimum voltage. In general, the low voltage detect circuit described herein may be configured to detect a low voltage condition based on a threshold voltage difference between a non-zero threshold transistor having a substantially non-zero threshold voltage, and a zero threshold transistor having a threshold voltage relatively close to zero. According to a particularly advantageous aspect of the invention, the low voltage detect circuit described herein comprises substantially no resistors or reference voltage generation circuits, and therefore, provides significant savings in both current and die area consumption without sacrificing accuracy. The low voltage detect circuit of the present invention is particularly useful in power regulators, such as those used in memory systems or devices.