Flip-flop (electrical) Patents (Class 365/154)
-
Patent number: 12225704Abstract: A semiconductor device including: a first level including at least four independently controlled first memory arrays, where the first level includes first transistors; a second level disposed on top of the first level, where the second level includes second memory arrays; and a third level disposed on top of the second level, where the third level includes third transistors and a plurality of third metal layers, where the third level is bonded to the second level, where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, where the first level includes first filled holes, where the second level includes second filled holes, where the second filled holes are aligned to the first filled holes with a more than 1 nm but less than 40 nm alignment error, and where the third level includes at least one SRAM memory array.Type: GrantFiled: June 2, 2024Date of Patent: February 11, 2025Assignee: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Jin-Woo Han, Brian Cronquist
-
Patent number: 12204782Abstract: According to an embodiment, a method for testing and repairing local memory in a hardware accelerator from a one-time programmable memory (OTP) is provided. The method includes asserting a grant signal, a loading of a first repair data for a sub-set of the local memory associated with a main-controller from a first partition of the OTP memory, communicating a status signal after completion of the loading indicating a completion of the loading, and de-asserting the grant signal in response to receiving the status signal.Type: GrantFiled: June 20, 2023Date of Patent: January 21, 2025Assignee: STMicroelectronics International N.V.Inventors: Urmishkumar Karsanbhai Patel, Danish Hasan Syed, Prateek Singh
-
Patent number: 12193205Abstract: A static random access memory device is provided and includes a first gate of a first pass-gate transistor extending to cross a first number of fins in a first threshold voltage region of a substrate and a second gate of a second pass-gate transistor extending to cross a second number of fins in a second threshold voltage region of a substrate. A boundary of the first threshold voltage region between the first and second gates is arranged closer to one, which crosses a smaller number of fins, of the first and second gates.Type: GrantFiled: May 5, 2023Date of Patent: January 7, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-Hung Lo, Feng-Ming Chang, Ying-Hsiu Kuo
-
Patent number: 12166870Abstract: In some implementations, a memory device may generate a physical unclonable function (PUF) value. The memory device may access a PUF protection key stored in a non-host-addressable memory region. The memory device may encrypt the PUF value, using the PUF protection key, to generate an encrypted PUF value. The memory device may store the encrypted PUF value in scattered memory locations in the non-host-addressable memory region.Type: GrantFiled: April 20, 2022Date of Patent: December 10, 2024Assignee: Micron Technology, Inc.Inventors: Sourin Sarkar, Vamshikrishna Komuravelli
-
Patent number: 12165737Abstract: Various implementations described herein are directed to a device having a multi-bitcell structure with multiple bitcells. The multiple bitcells may include first port transistors and second port transistors. The first port transistors may be arranged in a P-over-N stack configuration, and the second port transistors may be arranged in an N-over-N stack configuration.Type: GrantFiled: March 2, 2022Date of Patent: December 10, 2024Assignee: Arm LimitedInventor: Amit Chhabra
-
Patent number: 12165698Abstract: A static random access memory (SRAM) device disclosed herein includes an array of SRAM cells powered between first and second voltages. A reference voltage generator generates a reference voltage that is proportional to absolute temperature, with a magnitude curve of the reference voltage being based upon a control word. A low dropout amplifier sets and maintains the second voltage as being equal to the reference voltage. Control circuitry generates the control word based upon process variation information about the SRAM device. In one instance, the control circuitry monitors a canary bit-cell and increments the control word, to thereby increase the magnitude curve of the reference voltage, until the canary bit-cell fails. In another instance, the control circuitry measures the oscillation frequency of a ring oscillator, and selects the control word based upon the measured oscillation frequency.Type: GrantFiled: September 23, 2021Date of Patent: December 10, 2024Assignee: STMicroelectronics International N.V.Inventor: Kedar Janardan Dhori
-
Patent number: 12148465Abstract: An integrated circuit includes a first memory cell array and a controller. The first memory cell array includes a first array of volatile memory cells having a first retention data time. The controller is coupled to the first memory cell array. The controller is configured to write data to each memory cell in the first memory cell array in response to the integrated circuit being successfully logged into, read data from each memory cell in the first memory cell array in response to the integrated circuit being powered on, and determine whether to allow an authentication operation of the integrated circuit in response to reading data from each memory cell in the first memory cell array.Type: GrantFiled: April 3, 2023Date of Patent: November 19, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Shih-Lien Linus Lu
-
Patent number: 12136451Abstract: A memory system includes a non-volatile memory provided with a plurality of physical blocks, and a controller configured to execute a refresh for the plurality of blocks of the non-volatile memory to rewrite data of a first plurality of blocks to a second plurality of blocks provided in the plurality of blocks. In a first time period from a previous writing to each block provided in the first plurality of blocks to completion of the refresh for each block, the controller is capable of dynamically controlling a time at which the refresh for each block is started.Type: GrantFiled: August 29, 2022Date of Patent: November 5, 2024Assignee: KIOXIA CORPORATIONInventor: Rei Kasedo
-
Patent number: 12125525Abstract: A memory device and a method of operating the memory device are disclosed. In one aspect, the memory device includes a word line driver connected to a word line, a row of memory cells connected to the word line, each memory cell powered by a first supply voltage, and a power circuit. The power circuit is configured to provide the first supply voltage to the word line driver when a read condition is satisfied, and a second supply voltage to the word line driver when the read condition is not satisfied, the second supply voltage being less than the first supply voltage.Type: GrantFiled: February 11, 2022Date of Patent: October 22, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsung-Hsien Huang, Wei-jer Hsieh, Tsung-Yuan Huang, Yu-Hao Hsu
-
Patent number: 12119081Abstract: A semiconductor storage device includes: a storage element that holds data; a bit line that is coupled to the storage element and in which step-down to reference voltage causes data held in the storage element to be inverted, a first step-down circuit that steps down bit line voltage to a first predetermined value equal to or below the reference voltage, the bit line voltage being voltage applied to the bit line; and a control circuit that detects a first voltage change based on a first output from a first inverter which has a voltage dependence of an occurring delay and a second output from a second inverter in which a voltage dependence of an occurring delay is larger than that of the first inverter, and that controls a step-down amount of the bit line voltage by the first step-down circuit depending on an amount of the detected first voltage change.Type: GrantFiled: January 9, 2023Date of Patent: October 15, 2024Assignee: FUJITSU LIMITEDInventor: Hiroshi Nakadai
-
Patent number: 12094527Abstract: An apparatus includes a memory array. The array in turn includes a plurality of word lines, a plurality of bit line pairs intersecting the plurality of word lines at a plurality of cell locations, and a plurality of memory cells, coupled to the plurality of word lines and the plurality of bit line pairs, and located at the plurality of cell locations. A plurality of word line drivers are coupled to the plurality of word lines, a dynamic voltage boost is coupled to the memory array, and a controller is coupled to the plurality of word line drivers and the dynamic voltage boost. The controller is configured to cause the dynamic voltage boost to boost the cells during a multiply accumulate operation.Type: GrantFiled: March 31, 2022Date of Patent: September 17, 2024Assignee: International Business Machines CorporationInventors: Rajiv Joshi, Sudipto Chakraborty
-
Patent number: 12087381Abstract: An electronic circuit system includes a main device that generates first and second strobe signals and a clock signal, a first peripheral device that uses the first strobe signal to generate a first output signal in a first lane in response to the clock signal, and a second peripheral device that uses the second strobe signal to generate a second output signal in a second lane in response to the clock signal. The main device determines if the first peripheral device is coupled to the main device through the first lane based on the first output signal. The main device determines if the second peripheral device is coupled to the main device through the second lane based on the second output signal. The main device also has the ability to detect if a peripheral device is faulty and to select a valid configuration of peripheral devices.Type: GrantFiled: June 24, 2021Date of Patent: September 10, 2024Assignee: Altera CorporationInventors: Marian Cretu, Musaravakkam S. Krishnan
-
Patent number: 12073919Abstract: An apparatus and method for providing efficient floor planning, power, and performance tradeoffs of memory accesses. A dual read port and single write port memory bit cell uses two asymmetrical read access circuits for conveying stored data on two read bit lines. The two read bit lines are pre-charged to different voltage reference levels. The layout of the memory bit cell places the two read bit lines on an opposed edge from the single write bit line. The layout uses a dummy gate placed over both p-type diffusion and n-type diffusion between the edges. The layout has a same number of p-type transistors as n-type transistors despite using asymmetrical read access circuits. The layout also has a contacted gate pitch that is one more than the number of p-type transistors.Type: GrantFiled: June 25, 2021Date of Patent: August 27, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Arijit Banerjee, John J. Wuu, Russell Schreiber
-
Patent number: 12068025Abstract: Various implementations described herein are directed to a device having memory with banks of bitcells with each bank having a bitcell array. The device may have header circuitry that powers-up a selected bank and powers-down unselected banks during a wake-up mode of operation. In some instances, only the selected bank of the memory is powered-up with the header circuitry during the wake-up mode of operation.Type: GrantFiled: July 1, 2022Date of Patent: August 20, 2024Assignee: Arm LimitedInventors: Rahul Mathur, Edward Martin McCombs, Jr., Hsin-Yu Chen
-
Patent number: 12057505Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a first well region and a second well region and a first fin structure formed in a first region of the first well region. The semiconductor device structure also includes a second fin structure formed in a second region of the first well region. In addition, the second fin structure is narrower than the first fin structure. The semiconductor device structure also includes a third fin structure formed in a first region of the second well region. In addition, a sidewall of the first fin structure is substantially aligned with a sidewall of the third fin structure.Type: GrantFiled: July 5, 2021Date of Patent: August 6, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Kuan Lin, Chang-Ta Yang, Ping-Wei Wang
-
Patent number: 12046276Abstract: One aspect of this description relates to a memory cell. In some embodiments, the memory cell includes a first gate structure, a second gate structure, a third gate structure, a fourth gate structure, and a fifth gate structure that each extend along a first lateral direction, a first active structure extending along a second lateral direction and overlaid by respective first portions of the first to fourth gate structures, a second active structure extending along the second lateral direction and overlaid by respective second portions of the first to fourth gate structures, and a third active structure extending along the second lateral direction and overlaid by respective third portions of the third and fifth gate structures. In some embodiments, the first and second gate structures are aligned with each other, with the fourth and fifth gate structures aligned with a first segment and a second segment of the third gate structure, respectively.Type: GrantFiled: April 25, 2023Date of Patent: July 23, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Chuan Yang, Feng-Ming Chang, Kuo-Hsiu Hsu, Ping-Wei Wang
-
Patent number: 12048133Abstract: Semiconductor structures is provided. The semiconductor structure includes a semiconductor substrate having at least one first region, a plurality of second regions and a plurality of third regions; at least one second fin formed on one second region of the plurality of second region; at least one third fin formed on one third region of the plurality of third regions; a first epitaxial layer formed in the at least one first fin; and a second epitaxial layer formed in the at least one second fin and the at least one third fin.Type: GrantFiled: May 17, 2022Date of Patent: July 23, 2024Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventor: Nan Wang
-
Patent number: 12046278Abstract: New CMOS harvesting circuits are proposed that improve 2-port/multiport Register File Array circuit speed and substantially lower the energy cost of moving data along local and global bitpaths when engaging harvested data to self-limit energy dissipation. The uncertainty in BL signal development due to statistical variations in cell read current is eliminated by self-disabling action in the selected cell when the electric potential of harvested data matches the BL voltage from signal development while demanding fewer peripheral circuit transistors per column than conventional sensing schemes. Proposed bit path circuits engage harvested charge to provide immunity to disturb current noise during concurrent Read and Write access along a WL-eliminating the performance, area and energy overheads of BL keeper circuits typically required in conventional Register File arrays.Type: GrantFiled: January 19, 2022Date of Patent: July 23, 2024Assignee: Metis Microsystems, LLCInventor: Azeez Bhavnagarwala
-
Patent number: 12041787Abstract: A memory device includes a cross-point array of magnetoresistive memory cells. Each magnetoresistive memory cell includes a vertical stack of a selector-containing pillar structure and a magnetic tunnel junction pillar structure. The lateral spacing between neighboring pairs of magnetoresistive memory cells may be smaller along a first horizontal direction than along a second horizontal direction, and a dielectric spacer or a tapered etch process may be used to provide a pattern of an etch mask for patterning first electrically conductive lines underneath the magnetoresistive memory cells. Alternatively, a resist layer may be employed to pattern first electrically conductive lines underneath the cross-point array. Alternatively, a protective dielectric liner may be provided to protect selector-containing pillar structures during formation of the magnetic tunnel junction pillar structures.Type: GrantFiled: March 14, 2022Date of Patent: July 16, 2024Assignee: SANDISK TECHNOLOGIES LLCInventors: Lei Wan, Jordan Katine
-
Patent number: 12033721Abstract: An apparatus and method for providing efficient floor planning, power, and performance tradeoffs of memory accesses. Adjacent bit cells in a column of an array use a split read port such that the bit cells do not share a read bit line while sharing a write bit line. The adjacent bit cells include asymmetrical read access circuits that convey data stored by latch circuitry of a corresponding bit cell to a corresponding read bit line. The layout of adjacent bit cells provides a number of contacted gate pitches per bit cell that is less than a sum of the maximum number of metal gates in layout of each of the adjacent bit cells divided by the number of adjacent bit cells.Type: GrantFiled: June 25, 2021Date of Patent: July 9, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Arijit Banerjee, John J. Wuu, Russell Schreiber
-
Patent number: 12020884Abstract: Fuse programming circuits, devices and methods. In some embodiments, a fuse circuit can include a fuse pad configured to receive a voltage, a fuse having a first end coupled to the fuse pad and a second end coupled to a switching element configured to enable a current to pass from the fuse pad to a ground potential.Type: GrantFiled: August 15, 2023Date of Patent: June 25, 2024Assignee: Skyworks Solutions, Inc.Inventor: Bo Zhou
-
Patent number: 12004356Abstract: A memory device includes a cross-point array of magnetoresistive memory cells. Each magnetoresistive memory cell includes a vertical stack of a selector-containing pillar structure and a magnetic tunnel junction pillar structure. The lateral spacing between neighboring pairs of magnetoresistive memory cells may be smaller along a first horizontal direction than along a second horizontal direction, and a dielectric spacer or a tapered etch process may be used to provide a pattern of an etch mask for patterning first electrically conductive lines underneath the magnetoresistive memory cells. Alternatively, a resist layer may be employed to pattern first electrically conductive lines underneath the cross-point array. Alternatively, a protective dielectric liner may be provided to protect selector-containing pillar structures during formation of the magnetic tunnel junction pillar structures.Type: GrantFiled: March 14, 2022Date of Patent: June 4, 2024Assignee: SANDISK TECHNOLOGIES LLCInventors: Lei Wan, Jordan Katine, Tsai-Wei Wu
-
Patent number: 12004357Abstract: A memory device includes a cross-point array of magnetoresistive memory cells. Each magnetoresistive memory cell includes a vertical stack of a selector-containing pillar structure and a magnetic tunnel junction pillar structure. The lateral spacing between neighboring pairs of magnetoresistive memory cells may be smaller along a first horizontal direction than along a second horizontal direction, and a dielectric spacer or a tapered etch process may be used to provide a pattern of an etch mask for patterning first electrically conductive lines underneath the magnetoresistive memory cells. Alternatively, a resist layer may be employed to pattern first electrically conductive lines underneath the cross-point array. Alternatively, a protective dielectric liner may be provided to protect selector-containing pillar structures during formation of the magnetic tunnel junction pillar structures.Type: GrantFiled: March 14, 2022Date of Patent: June 4, 2024Assignee: SANDISK TECHNOLOGIES LLCInventors: Lei Wan, Jordan Katine, Tsai-Wei Wu, Chu-Chen Fu
-
Patent number: 11996144Abstract: A non-volatile memory (NVM) is formed of memory cells each having multiple ferroelectric memory elements (FMEs). Each FME stores data in relation to an electrical polarity of a recording layer formed of ferroelectric or anti-ferroelectric material. Each multi-FME memory cell is coupled to a set of external control lines activated by a control circuit in a selected order to perform program and/or read operations upon the FMEs. The FMEs may share a nominally identical construction or may have different constructions. Data are programmed and written responsive to the respective program/read responses of the FMEs. Constructions can include ferroelectric tunneling junctions (FTJs), ferroelectric random access memory (FeRAM), and ferroelectric field effect transistors (FeFETs). The NVM may form a portion of a data storage device, such as a solid-state drive (SSD).Type: GrantFiled: June 15, 2022Date of Patent: May 28, 2024Assignee: SEAGATE TECHNOLOGY LLCInventors: Jon D. Trantham, Praveen Viraraghavan, John W. Dykes, Ian J. Gilbert, Sangita Shreedharan Kalarickal, Matthew J. Totin, Mohamad El-Batal, Darshana H. Mehta
-
Patent number: 11989498Abstract: A method of designing a circuit is provided. The method includes: providing a circuit; selecting a first NMOS fin field-effect transistor (FinFET) in the circuit; and replacing the first NMOS FinFET having a first fin number with a second NMOS FinFET having a second fin number and a third NMOS FinFET having a third fin number, wherein the sum of the second fin number and the third fin number is equal to the first fin number.Type: GrantFiled: January 30, 2023Date of Patent: May 21, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi-Tzu Chen, Hau-Tai Shieh, Che-Ju Yeh
-
Patent number: 11929113Abstract: A memory device includes an array of memory cells, a bit line connected to the memory cells, and a power supply voltage input terminal configured to receive a power supply voltage at a first voltage level to operate the memory cells at the first voltage level. A bit line precharge circuit has an input terminal configured to receive the power supply voltage at the first voltage level, and the bit line precharge circuit is configured to precharge the bit lines to a second voltage level lower than the first voltage level.Type: GrantFiled: December 2, 2022Date of Patent: March 12, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Atul Katoch, Adrian Earle
-
Patent number: 11930672Abstract: A display device includes a substrate including a display area and a non-display area, the display area including pixels; data lines extending into the display area and connected to pixels; a first input pad in the non-display area and connected to the data lines; a switching transistor located in the non-display area between the first input pad and one side of the substrate and connected to the first input pad; and a second input pad in the non-display area and connected to a gate electrode of the switching transistor through a switching line.Type: GrantFiled: December 22, 2020Date of Patent: March 12, 2024Assignee: LG DISPLAY CO., LTD.Inventor: Yeong-Yun Yang
-
Patent number: 11929685Abstract: A voltage source converter has a half bridge (18) with two current valves (19, 20) connected in series and an arrangement configured to carry out voltage measurements for determining a value of the DC voltage between opposite poles (21, 22) of a DC side of the converter. Each current valve comprises a semiconductor device (23, 24) controlled by an associated gate drive member (29, 30), each forming gate drive parts of one gate drive unit (28) in common to both current valves. The gate drive unit (28) comprises an isolated two-way communication link (33) between the gate drive members. The arrangement is included in the gate drive unit and configured to measure the entire DC voltage between said opposite poles (21, 22). A converter control device (31) calculates and sends control signals to the gate drive unit based on the result of the voltage measurement.Type: GrantFiled: November 7, 2019Date of Patent: March 12, 2024Assignee: BOMBARDIER TRANSPORTATION GMBHInventors: Andreas Löfgren, Johan Dahlke, Stefan Roth
-
Patent number: 11915743Abstract: A latch formed from a memory cell includes a clock input terminal configured to receive a clock signal, complementary first and second data terminals, and a latch circuit. The latch circuit has first and second inverters. The first inverter has an input terminal coupled to the first data terminal, and the second inverter has an input terminal coupled to the second data terminal. A first pass gate transistor is coupled between an output terminal of the second inverter and the first data terminal. A second pass gate transistor is coupled between an output terminal of the first inverter and the second data terminal. The first and second pass gate transistors each have a gate terminal coupled to the clock input terminal. The input terminal of the first inverter is not directly connected to the output terminal of the second inverter, and the input terminal of the second inverter is not directly connected to the output terminal of the first inverter.Type: GrantFiled: March 15, 2021Date of Patent: February 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hua-Hsin Yu, Cheng Hung Lee, Hung-Jen Liao, Hau-Tai Shieh
-
Patent number: 11910585Abstract: Well pick-up (WPU) regions are disclosed herein for improving performance of memory arrays, such as static random access memory arrays. An exemplary integrated circuit (IC) device includes a circuit region, a WPU region, a first well extending lengthwise along a first direction through the circuit region and into the WPU region, a second well extending lengthwise along the first direction through the circuit region and into the WPU region, and a third well physically connecting a portion of the first well in the WPU region and a portion of the second well in the WPU region.Type: GrantFiled: July 26, 2022Date of Patent: February 20, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Chuan Yang, Chang-Ta Yang, Ping-Wei Wang
-
Patent number: 11894049Abstract: A memory cell comprises a pair of cross-coupled inverters as a storage element, a first inverter in the pair of cross-coupled inverters having a first output at a first node, a second inverter in the pair of cross-coupled inverters having a second output at a second node. A first complementary transmission gate includes a first nMOS pass gate and a first pMOS pass gate, connected between the first node and a first bit line. A second complementary transmission gate includes a second nMOS pass gate and a second pMOS pass gate, connected between the second node and a second bit line. A first word line is connected to gate conductors of the first and second nMOS pass gates in the first and second complementary transmission gates. A second word line is connected to gate conductors of the first and second pMOS pass gates in the first and second transmission gates.Type: GrantFiled: December 2, 2021Date of Patent: February 6, 2024Assignee: Synopsys, Inc.Inventors: Plamen Asenov, Victor Moroz
-
Patent number: 11894095Abstract: A semiconductor memory device includes a plurality of data latch circuits that are used for input and output of data between a sense amplifier circuit and an input/output circuit, and a data bus that is connected to the plurality of data latch circuits. Each of the data latch circuits includes an inverter circuit that temporarily stores data input and output between the sense amplifier circuit and the input/output circuit, and at least three MOS transistors between the inverter circuit and the data bus. The at least three MOS transistors may be multiple N-channel type MOS transistors and at least one P-channel type MOS transistor connected in parallel between the inverter circuit and the data bus, or at least one N-channel type MOS transistor and multiple P-channel type MOS transistors connected in parallel between the inverter circuit and the data bus.Type: GrantFiled: March 2, 2022Date of Patent: February 6, 2024Assignee: Kioxia CorporationInventors: Yuji Satoh, Hiromitsu Komai
-
Patent number: 11889673Abstract: An integrated circuit includes: a dual port Static Random Access Memory (SRAM) cell including a plurality of transistors; a bit line pair connected to the dual port SRAM cell, the bit line pair including a first bit line and a second bit line spaced apart from each other in a first direction and extending in a second direction perpendicular to the first direction; a power line group including a plurality of power lines spaced apart from each other in the first direction, spaced apart from the bit line pair placed in the first direction, and extending in the second direction, the power line group being configured to apply a voltage to the dual-port SRAM cell; and a first word line provided between the first bit line and the second bit line and connected to the dual port SRAM cell.Type: GrantFiled: March 18, 2022Date of Patent: January 30, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sangshin Han, Taehyung Kim
-
Patent number: 11830544Abstract: A semiconductor memory device includes an array of memory cells arranged in a plurality of rows and columns, with each memory cell including a plurality of bit cell transistors. The semiconductor memory device further includes a plurality of write assist circuits, including one or more write assist circuits within each column of the array of memory cells, each write assist circuit configured to provide a core voltage to memory cells within the same column and to reduce the core voltage during a write operation. The array of memory cells and the plurality of write assist circuits have a common semiconductor layout.Type: GrantFiled: July 15, 2022Date of Patent: November 28, 2023Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Sahil Preet Singh, Yen-Huei Chen, Hung-Jen Liao
-
Patent number: 11823765Abstract: The present application provides a storage system including a data port. The data port includes a data output unit. The data output unit includes: a pull-up unit having a control terminal, a first terminal and a second terminal, a first input signal being inputted to the control terminal, the first terminal being electrically connected to a power supply, the second terminal being connected to an output terminal of the data output unit, and the pull-up unit being a first NMOS transistor; and a pull-down unit having a control terminal, a first terminal and a second terminal, a second input signal being inputted to the control terminal, the first terminal being electrically connected to a ground terminal, and the second terminal being connected to the output terminal of the data output unit.Type: GrantFiled: February 5, 2021Date of Patent: November 21, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Shuliang Ning
-
Patent number: 11778803Abstract: A system and method for efficiently creating layout for memory bit cells are described. In various implementations, a memory bit cell uses Cross field effect transistors (FETs) that include vertically stacked gate all around (GAA) transistors with conducting channels oriented in an orthogonal direction between them. The channels of the vertically stacked transistors use opposite doping polarities. The memory bit cell includes one of a read bit line and a write word line routed in no other metal layer other than a local interconnect layer. In addition, a six transistor (6T) random access data storage of the given memory bit cell consumes a planar area above a silicon substrate of four transistors.Type: GrantFiled: September 29, 2021Date of Patent: October 3, 2023Assignee: Advanced Micro Devices, Inc.Inventor: Richard T. Schultz
-
Patent number: 11776949Abstract: An IC device includes a first active area extending away from a first endpoint in a first direction, a second active area extending away from a second endpoint in the first direction, a third active area positioned between the first and second active areas, and a gate structure perpendicular to the first through third active areas. The gate structure overlies each of the first and second endpoints and the third active area, and the third active area extends away from the gate structure in a second direction opposite the first direction.Type: GrantFiled: May 9, 2022Date of Patent: October 3, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chien-Ying Chen, Lee-Chung Lu, Li-Chun Tien, Ta-Pen Guo
-
Patent number: 11776621Abstract: A memory device and an operation method thereof is disclosed. The memory device includes a SRAM cell and a power supply assist circuit connected to the SRAM cell. The power supply assist circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor. The first transistor receives a power supply voltage. The control terminals of the first transistor and the second transistor are connected to each other. The third transistor switches, in response to a first control signal, to connect the control terminal and the connect terminal of the second transistor. The fourth transistor switches, in response to a second control signal, to drive the control terminal of the second transistor to a system ground voltage. The fifth transistor switches, in response to a third control signal, to drive the control terminal of the first transistor to the power supply voltage.Type: GrantFiled: October 22, 2021Date of Patent: October 3, 2023Assignee: NATIONAL CHUNG CHENG UNIVERSITYInventors: Jinn Shyan Wang, Chien Tung Liu, Chih Jung Liu
-
Patent number: 11778802Abstract: A device is disclosed that includes a fin structure disposed below a first metal layer, extending along a column direction, and corresponding to at least one transistor of a memory bit cell, a word line disposed in the first metal layer and extending along a row direction, a first metal island disposed in the first metal layer separated from the word line, and a first connection metal line disposed in a second metal layer above the first metal layer, extending along the column direction, and configured to couple a power supply through the first metal island to the fin structure. In a layout view, the first connection metal line is separated from the fin structure, and the fin structure crosses over the word line and the first metal island. A method is also disclosed herein.Type: GrantFiled: May 13, 2021Date of Patent: October 3, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hidehiro Fujiwara, Wei-Min Chan, Chih-Yu Lin, Yen-Huei Chen, Hung-Jen Liao
-
Patent number: 11778813Abstract: Semiconductor devices including active regions and gate electrodes are disclosed. An example semiconductor device according to the disclosure includes a gate electrode extending in a first direction, and first and second active regions extending in a second direction. The gate electrode has a side extending in the first direction. The first active region includes: a first center portion having a first width in the first direction; and a first end portion disposed at a first end of the first center portion, and having a second width in the first direction that is greater than the first width. The second active region includes: a second center portion having a third width in the first direction. The gate electrode overlaps along the side with portions of the first end portion and the second center portion.Type: GrantFiled: February 9, 2021Date of Patent: October 3, 2023Assignee: Micron Technology, Inc.Inventor: Masahiro Yokomichi
-
Patent number: 11765878Abstract: Devices and methods are described herein that obviate the need for a read assist circuit. In one example, a semiconductor device includes a source region and a drain region formed above a substrate. A buried insulator (BI) layer is formed beneath either the source region or the drain region. A first nano-sheet is formed (i) horizontally between the source region and the drain region and (ii) vertically above the BI layer. The BI layer reduces current flow through the first nano-sheet.Type: GrantFiled: December 16, 2021Date of Patent: September 19, 2023Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Kam-Tou Sio, Yi-Hsun Chiu
-
Patent number: 11727972Abstract: A memory device is disclosed. The memory device includes word lines, a tracking bit line and a word line driver. The word lines are configured to transmit word line signals to memory cells. The tracking bit line is coupled to a first plurality of tracking cells that are arranged in rows. The word line driver is coupled to the word lines and a control circuit that is coupled through the tracking bit line to the word lines. The word line driver is configured to control a falling edge of each of the word line signals, by receiving each corresponding tracking bit line signal of tracking bit line signals transmitted from the tracking bit line, based on a resistance of a length of the tracking bit line. The length is substantially distanced from each corresponding row of the rows to the control circuit. A method is also disclosed herein.Type: GrantFiled: August 27, 2021Date of Patent: August 15, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsung-Hsien Huang, Wei-Jer Hsieh, Yu-Hao Hsu
-
Patent number: 11728118Abstract: Fuse programming circuits, devices and methods. In some embodiments, a fuse circuit can include a fuse pad configured to receive a voltage, a fuse having a first end coupled to the fuse pad and a second end coupled to a switching element configured to enable a current to pass from the fuse pad to a ground potential.Type: GrantFiled: April 4, 2022Date of Patent: August 15, 2023Assignee: Skyworks Solutions, Inc.Inventor: Bo Zhou
-
Patent number: 11715505Abstract: A memory circuit includes a NAND logic gate configured to receive a first bit line signal and a second bit line signal, and to generate a first signal. The memory circuit further includes a first N-type transistor coupled to the NAND logic gate, and configured to receive a first pre-charge signal. The memory circuit further includes a second N-type transistor coupled to the first N-type transistor and a reference voltage supply, and configured to receive a first clock signal. The memory circuit further includes a first latch coupled to the NAND logic gate, and configured to latch the first signal in response to at least the first clock signal or the first pre-charge signal.Type: GrantFiled: July 29, 2022Date of Patent: August 1, 2023Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC CHINA COMPANY, LIMITEDInventors: Yi-Tzu Chen, Ching-Wei Wu, Hau-Tai Shieh, Hung-Jen Liao, Fu-An Wu, He-Zhou Wan, XiuLi Yang
-
Patent number: 11682450Abstract: A read-port of a Static Random Access Memory (SRAM) cell includes a read-port pass-gate (R_PG) transistor and a read-port pull-down (R_PD) transistor. A write-port of the SRAM cell port includes at least a write-port pass-gate (W_PG) transistor, a write-port pull-down (W_PD) transistor, and a write-port pull-up (W_PU) transistor. The R_PG transistor, the R_PD transistor, the W_PG transistor, the W_PD transistor, and the W_PU transistor are gate-all-around (GAA) transistors. The R_PG transistor has a first channel width. The R_PD transistor has a second channel width. The W_PG transistor has a third channel width. The W_PD transistor has a fourth channel width. The W_PU transistor has a fifth channel width. The first channel width and the fourth channel width are each smaller than the second channel width. The third channel width is greater than the fifth channel width.Type: GrantFiled: July 15, 2021Date of Patent: June 20, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Jhon Jhy Liaw
-
Patent number: 11676660Abstract: A static random access memory (SRAM) includes a first memory cell array, a second memory cell array, a first data line coupled to the first memory cell array and the second memory cell array, a second data line coupled to the first memory cell array and the second memory cell array, a primary driver circuit coupled to at least the first data line, and a supplementary driver circuit coupled to at least the first data line. The supplementary driver circuit is configured to receive a supplementary driver circuit enable signal, sense a voltage of a first signal of the first data line, and pull the voltage of the first signal to a first voltage level during a write operation of a first memory cell in the first memory cell array in response to at least a first NOR output signal.Type: GrantFiled: December 2, 2021Date of Patent: June 13, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Yu Lin, Wei-Cheng Wu, Kao-Cheng Lin, Yen-Huei Chen
-
Patent number: 11678474Abstract: A semiconductor device includes first, second, third, fourth, and fifth active regions each extending lengthwise along a first direction, wherein the first, second, third, and fourth active regions comprise channel regions and source/drain (S/D) regions of first, second, third, and fourth transistors respectively, and the fifth active region comprises channel regions and S/D regions of fifth and sixth transistors; and first, second, third, fourth, fifth, and sixth gates each extending lengthwise along a second direction perpendicular to the first direction, wherein the first through sixth gates are configured to engage the channel regions of the first through sixth transistors respectively, wherein the first, second, and fifth gates are electrically connected, and wherein one of the S/D regions of the first transistor, one of the S/D regions of the second transistor, the third gate, and the fourth gate are electrically connected.Type: GrantFiled: December 23, 2019Date of Patent: June 13, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-Hsiu Hsu, Yu-Kuan Lin, Feng-Ming Chang, Lien Jung Hung, Ping-Wei Wang
-
Patent number: 11664081Abstract: Systems, devices, and methods are described herein for a programmable memory array. A programmable memory system includes an array of programmable memory bit cells. A memory bit cell of the array includes a first transistor of a first type controlled by a bit line, a second transistor of a second type responsive to a first word line and a second word line via a logic gate, and a third transistor of the second type responsive to the word line. The first word line is positioned substantially perpendicular to the bit line, and the second word line is positioned substantially parallel to the bit line. The first word line is activated via an X portion of an address. While the second word line is activated via a Y portion of the address.Type: GrantFiled: December 21, 2021Date of Patent: May 30, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Meng-Sheng Chang, Yoshitaka Yamauchi, Perng-Fei Yuh
-
Patent number: 11657869Abstract: One aspect of this description relates to a memory cell. In some embodiments, the memory cell includes a first gate structure, a second gate structure, a third gate structure, a fourth gate structure, and a fifth gate structure that each extend along a first lateral direction, a first active structure extending along a second lateral direction and overlaid by respective first portions of the first to fourth gate structures, a second active structure extending along the second lateral direction and overlaid by respective second portions of the first to fourth gate structures, and a third active structure extending along the second lateral direction and overlaid by respective third portions of the third and fifth gate structures. In some embodiments, the first and second gate structures are aligned with each other, with the fourth and fifth gate structures aligned with a first segment and a second segment of the third gate structure, respectively.Type: GrantFiled: November 17, 2021Date of Patent: May 23, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Chih-Chuan Yang, Feng-Ming Chang, Kuo-Hsiu Hsu, Ping-Wei Wang
-
Patent number: 11646347Abstract: Disclosed herein is an apparatus that includes: a first diffusion region having a rectangular shape and including first and second source/drain regions arranged in the first direction; a second diffusion region having a rectangular shape and including third to fifth source/drain regions arranged in the first direction; a first gate electrode extending in a second direction, and provided between the first and second source/drain regions and between the third and fourth source/drain regions; and a second gate electrode extending in the second direction, and provided between the fourth and fifth source/drain regions. The first and third source/drain regions are brought into the same potential as each other, and the second and fourth source/drain regions are brought into the same potential as each other.Type: GrantFiled: February 18, 2021Date of Patent: May 9, 2023Assignee: Micron Technology, Inc.Inventor: Toshinao Ishii