Flip-flop (electrical) Patents (Class 365/154)
  • Patent number: 11450369
    Abstract: A semiconductor circuit according to the present disclosure includes a first circuit that generates an inverted voltage of a voltage at a first node, and applies the inverted voltage to a second nodes, a second circuit that generates an inverted voltage of a voltage at the second node, and applies the inverted voltage to the first node, a first memory element that has a first terminal, a second terminal, and a third terminal, and stores information by setting a resistance state between the second terminal and the third terminal to a first resistance state or a second resistance state in accordance with a direction of a first current flowing between the first terminal and the second terminal, a first transistor that couples the first node to the third terminal of the first memory element and a second transistor that is coupled to a first coupling node.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: September 20, 2022
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Yasuo Kanda
  • Patent number: 11430505
    Abstract: The present disclosure relates to in-memory computing using a static random access memory (SRAM). In particular, the present disclosure relates to a structure including a memory configured to store a first word and a second word, the memory further includes a configurable data path circuit, and the configured data path circuit is configured to perform an arithmetic logical operation based on the first word and the second word in parallel.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: August 30, 2022
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Akhilesh Patil, Eric D. Hunt-Schroeder
  • Patent number: 11410721
    Abstract: A semiconductor memory device of an embodiment includes: a first inverter including a first P-channel and first N-channel transistors; a second inverter including a second P-channel and second N-channel transistors and being cross-connected to the first inverter; a third P-channel transistor; a third N-channel transistor; a first wiring; a second wiring; a third wiring; a fourth wiring; a fifth wiring; a sixth wiring; and a controller that drives the first to sixth wirings. When writing second-level data that is at a higher potential level than first-level data into the drain of the second P-channel transistor and the drain of the second N-channel transistor, the controller puts one of the fifth wiring and the sixth wiring into a floating state.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: August 9, 2022
    Assignee: KIOXIA CORPORATION
    Inventor: Atsushi Kawasumi
  • Patent number: 11398274
    Abstract: A pseudo-triple-port memory is provided that includes a plurality of pseudo-triple-port bitcells, each pseudo-triple-port first bitcell having a first read port including a first word line coupled to a first bit line through a first access transistor, a second read port including a second word line coupled to a second bit line through a second access transistor, and a write port including both the word lines, both the bit lines, and the pair of access transistors.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: July 26, 2022
    Assignee: QUALCOMM INCORPORATED
    Inventors: Arun Babu Pallerla, Changho Jung, Sung Son
  • Patent number: 11398273
    Abstract: A memory includes an array with rows and columns of memory cells. The rows include a first row and a second row, which may be adjacent. The memory also includes a plurality of logic gates in the array. Each logic gate of the plurality of logic gates includes a first input coupled to a respective memory cell in the first row, a second input coupled to a respective memory cell in the second row, and an output. The first and second inputs may be connected to internal nodes within the respective memory cells without intervening transistors. The memory further includes a plurality of sense lines in the array. The output of each logic gate of the plurality of logic gates is coupled to a sense line of the plurality of sense lines.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: July 26, 2022
    Inventor: Bindiganavale S. Nataraj
  • Patent number: 11393928
    Abstract: Systems, apparatuses and methods related to access devices formed with conductive contacts are described. An example apparatus may include an access device that includes a field-effect transistor (FET). A vertical pillar may be formed to include a channel of the FET, with a portion of the vertical pillar formed between at least two gates of the FET (i.e., a multi-gate Fin-FET). A conductive contact may be coupled to a body region of the vertical pillar.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: July 19, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Haitao Liu, Yunfei Gao, Kamal M. Karda, Deepak Chandra Pandey, Sanh D. Tang, Litao Yang
  • Patent number: 11388014
    Abstract: An integrated circuit is fabricated using a semiconductor fabrication process. One or more uncontrollable random physical processes in the semiconductor fabrication process can cause small differences between the integrated circuit and other similarly designed integrated circuit. These small differences can cause transistors of the integrated circuit to have different threshold voltages. The integrated circuit can use these different threshold voltages to quantify its physical uniqueness to differentiate itself from other integrated circuits similarly designed and fabricated by the semiconductor fabrication process.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: July 12, 2022
    Inventor: Shih-Lien Linus Lu
  • Patent number: 11379298
    Abstract: A circuit includes: a single-port memory interface which includes a sole address port configured to receive a read/write (RW) address, and a multi-port memory which has multiple address ports coupled to the sole address port of the single-port memory interface, and which is configured to store a data unit and parity bits, some of the parity bits being based on the corresponding RW address; a first decoding circuit configured to generate a decoded write address from the RW address and the parity bits; and an error detecting circuit configured to determine if an address error exists based on a comparison of the decoded write address to the read address.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: July 5, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Saman M. I. Adham, Ramin Shariat-Yazdi, Shih-Lien Linus Lu
  • Patent number: 11361806
    Abstract: Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. A first ferroelectric memory cell may be used to charge a second ferroelectric memory cell by transferring charge from a plate of first ferroelectric memory cell to a plate of the second ferroelectric memory cell. In some examples, prior to the transfer of charge, the first ferroelectric memory cell may be selected for a first operation in which the first ferroelectric memory cell transitions from a charged state to a discharged state and the second ferroelectric memory cell may be selected for a second operation during which the second ferroelectric memory cell transitions from a discharged state to a charged state. The discharging of the first ferroelectric memory cell may be used to assist in charging the second ferroelectric memory cell.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: June 14, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Eric S. Carman
  • Patent number: 11355167
    Abstract: In some embodiments, an in-memory-computing SRAM macro based on capacitive-coupling computing (C3) (which is referred to herein as “C3SRAM”) is provided. In some embodiments, a C3SRAM macro can support array-level fully parallel computation, multi-bit outputs, and configurable multi-bit inputs. The macro can include circuits embedded in bitcells and peripherals to perform hardware acceleration for neural networks with binarized weights and activations in some embodiments. In some embodiments, the macro utilizes analog-mixed-signal capacitive-coupling computing to evaluate the main computations of binary neural networks, binary-multiply-and-accumulate operations. Without needing to access the stored weights by individual row, the macro can assert all of its rows simultaneously and form an analog voltage at the read bitline node through capacitive voltage division, in some embodiments.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: June 7, 2022
    Assignee: The Trustees of Columbia University in the City of New York
    Inventors: Mingoo Seok, Zhewei Jiang, Jae-sun Seo, Shihui Yin
  • Patent number: 11348929
    Abstract: A memory device includes a substrate, a first gate structure and a second gate structure, first, second, third source/drain structures, gate spacers, a first via and a second via, and a semiconductor layer. The first gate structure and the second gate structure are over the substrate. The first, second, third source/drain structures are over the substrate, in which the first and second source/drain structures are on opposite sides of the first gate structure, the second and third source/drain structures are on opposite sides of the second gate structure. The gate spacers are on opposite sidewalls of the first and second gate structures. The first via and the second via are over the first gate structure and the second gate structure, respectively, in which the first via is in contact with the first gate structure. The semiconductor layer is between the second via and the second gate structure.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: May 31, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Wen Su, Chia-En Huang, Shih-Hao Lin, Lien-Jung Hung, Ping-Wei Wang
  • Patent number: 11342021
    Abstract: A mixed mode memory comprises a memory array, a word line decoder, an intermediary circuit and a reading and writing circuit, wherein the word line decoder is electrically coupled to the memory array, and the intermediary circuit is electrically coupled to the memory array and the writing circuit. The memory array comprises mixed mode memory cells with each cell comprising a reading and writing component group, a storage circuit and a selection circuit. The reading and writing component group is electrically coupled to a word line which controls the reading and writing component group to be conducted or not conducted, and electrically coupled to two bit lines which respectively transmit two data signals. The storage circuit generates two reading response signals based on a reading drive signal. The selection circuit controls the storage circuit to operate in a volatile or non-volatile storage mode based on a selection voltage.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: May 24, 2022
    Assignees: JIANGSU ADVANCED MEMORY TECHNOLOGY CO., LTD., JIANGSU ADVANCED MEMORY SEMICONDUCTOR CO., LTD., ALTO MEMORY TECHNOLOGY CORPORATION
    Inventors: Yu-Cheng Liao, Chun-Chih Liu, Ching-Sung Chiu
  • Patent number: 11335397
    Abstract: A memory cell that performs in-memory compute operations, includes a pair of cross-coupled inverters and a pair of transistors for selective performance of read/write/hold operations associated with logic states of the pair of cross-coupled inverters. The memory cell further includes a set of transistors that are gate coupled to and symmetrically arranged about the pair of cross coupled inverters. Output nodes of the memory cell are located at terminals of the set of transistors and provide output based on logic states of the pair of cross coupled inverters and input nodes provided between pairs of the set of transistors. A memory cell array may be generated having a high density arrangement memory cells that can perform in-memory compute operations. The memory cells can be arranged as a neural network including a set of memory cell networks that provide logic output operations based on logic states of the respective memory cells.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: May 17, 2022
    Assignee: STMicroelectronics International N.V.
    Inventors: Anuj Grover, Tanmoy Roy
  • Patent number: 11328762
    Abstract: Circuits, systems, and methods are described herein for generating a boost voltage for a write operation of a memory cell. In one embodiment, a boost circuit includes a first inverter and a second inverter, each configured to invert a write signal. The boost circuit also includes a transistor and a capacitor. The transistor is coupled to an output of the first inverter. The transistor is configured to charge a capacitor based on the write signal and provide a supply voltage to a write driver. The capacitor is coupled to an output of the second inverter. The capacitor is configured to generate and provide a delta voltage to the write driver.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: May 10, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Sanjeev Kumar Jain
  • Patent number: 11322200
    Abstract: A single-rail memory circuit includes an array of memory cells arranged in rows and columns and peripheral circuitry connected to the array for facilitating read and write operations with respect to selected memory cells. The peripheral circuitry includes, but is not limited to, boost circuits for the rows. Each boost circuit is connected to a wordline for a row and to a discrete voltage supply line for the same row. Each boost circuit for a row is configured to increase the voltage levels on the wordline and the voltage supply line for the row during a read of any selected memory cell within the row. Increasing the voltage levels on the wordline and on the voltage supply line during the read operation effectively boosts the read current. A method of operating the memory circuit reduces the probability of a read fail.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: May 3, 2022
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Vivek Raj, Shivraj G. Dharne, Uttam K. Saha, Mahbub Rashed
  • Patent number: 11315624
    Abstract: A memory cell of a 2-port static random access memory (SRAM) includes first and second p-type transistors and first to sixth n-type transistors. Gate interconnects extend in the X direction and are arranged in three rows in the Y direction. The gate interconnects in the first row form gates of the first n-type transistor, the first p-type transistor, and the fourth n-type transistor, the gate interconnect in the second row forms gates of the fifth and sixth n-type transistors, and the gate interconnects in the third row form gates of the third n-type transistor, the second n-type transistor, and the second p-type transistor.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: April 26, 2022
    Assignee: SOCIONEXT INC.
    Inventor: Yoshinobu Yamagami
  • Patent number: 11309025
    Abstract: A semiconductor circuit includes a first circuit that applies an inverted voltage of a voltage at a first node to a second node, a second circuit that applies an inverted voltage of a voltage at the second node to the first node, a first transistor that couples the first node to a third node, and a first memory element having a first terminal coupled to the third node and a second terminal to which a control voltage is to be applied. The semiconductor circuit further includes a second transistor having a drain coupled to the third node and a gate coupled to one of the first node or the second node, a third transistor having a drain coupled to the third node and a gate coupled to the other of the first node or the second node, and a driver.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: April 19, 2022
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Yusuke Shuto
  • Patent number: 11302389
    Abstract: It discloses a circuit for reducing a leakage current of a static random access memory (SRAM) memory array and a control method for the same. The circuit includes a memory array power supply voltage control module, a memory array ground terminal voltage control module and a memory array. The present invention controls the voltages on the power supply terminal and the ground terminal of the memory array through the memory array power supply voltage control module and the memory array ground terminal control module, and may reduce the actual data retention voltages of the bitcells, thereby reducing the leakage power of the SRAM in a data retention state. Meanwhile, the present invention implements the function of adjusting the data retention voltage values of the bitcells by controlling different adjustment signals to cope with different design requirements.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: April 12, 2022
    Assignee: NANJING LOW POWER IC TECHNOLOGY INSTITUTE CO., LTD.
    Inventor: Xiaomin Li
  • Patent number: 11295922
    Abstract: Fuse programming circuits, devices and methods. In some embodiments, a fuse circuit can include a fuse pad configured to receive a voltage, a fuse having a first end coupled to the fuse pad and a second end coupled to a switching element configured to enable a current to pass from the fuse pad to a ground potential.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: April 5, 2022
    Assignee: Skyworks Solutions, Inc.
    Inventor: Bo Zhou
  • Patent number: 11289145
    Abstract: According to various aspects, a memory cell is provided, the memory cell may include a field-effect transistor; a first control node and a second control node, a first capacitor structure including a first electrode connected to the first control node, a second electrode connected to a gate region of the field-effect transistor, and a remanent-polarizable region disposed between the first electrode and the second electrode of the first capacitor structure; and a second capacitor structure including a first electrode connected to the second control node, a second electrode connected to the gate region of the field-effect transistor. In some aspects, the first capacitor structure may have a first capacitance and the second capacitor structure may have a second capacitance different from the first capacitance.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: March 29, 2022
    Assignee: FERROELECTRIC MEMORY GMBH
    Inventor: Johannes Ocker
  • Patent number: 11276448
    Abstract: Methods, systems, and devices for memory array with multiplexed select lines are described. In some cases, a memory cell of the memory device may include a storage component, a first transistor coupled with a word line, and a second transistor coupled with a first select line to selectively couple the memory cell with a first digit line. A third transistor may be coupled with the first digit line and a sense component common to a set of digit lines and a set of select lines. A second select line may be coupled with the third transistor and configured to couple the sense component with the first digit line and to couple the sense component with a second digit line. The sense component may determine a logic state stored by the memory cell based on the signal from the first digit line and the signal from the second digit line.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: March 15, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Daniele Vimercati
  • Patent number: 11276458
    Abstract: A memory and a signal processing method are provided. The memory includes a latch circuit, a decoding circuit, a storage array, a read circuit, and a write circuit. The storage array includes M rows and N columns of bitcells. The latch circuit is configured to receive a first address and a second address. The decoding circuit is configured to: determine a first bitcell based on the first address, and determine a second bitcell based on the second address. The write circuit is configured to: receive data, and write the data into the first bitcell through a first port of the first bitcell. The read circuit is configured to read, through the first port of the first bitcell, data stored in the first bitcell; and is further configured to read, through a second port of the second bitcell, data stored in the second bitcell. Implementing this application can implement 1R1RW.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: March 15, 2022
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Bingwu Ji, Tanfu Zhao, Yunming Zhou, Min Fan, Zhiyan Li, Yunpeng Wang
  • Patent number: 11270762
    Abstract: A memory is provided that is configured to practice both a normal read operation and also a burst mode read operation. A burst mode address comparator compares a current row address to a preceding row address from a preceding read operation to determine whether a read operation is a normal read operation or a burst mode read operation. The burst mode address comparator invokes the burst mode despite the presence of an intervening write operation to a row address not equal to the preceding row address.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: March 8, 2022
    Assignee: Qualcomm Incorporated
    Inventors: Changho Jung, Arun Babu Pallerla, Percy Dadabhoy
  • Patent number: 11270761
    Abstract: A dual-mode memory is provided that includes a self-timed clock circuit for asserting a sense enable signal for a sense amplifier. In a low-bandwidth read mode, the self-timed clock circuit asserts the sense enable signal only once during a memory clock cycle. The sense amplifier then senses only a single bit from a group of multiplexed columns. In a high-bandwidth read mode, the self-timed clock circuit successively asserts the sense enable signal so that the sense amplifier successively senses bits from the multiplexed columns.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: March 8, 2022
    Assignee: Qualcomm Incorporated
    Inventors: Hoan Huu Nguyen, Francois Ibrahim Atallah, Keith Alan Bowman, Daniel Yingling, Jihoon Jeong, Yu Pu
  • Patent number: 11264070
    Abstract: Systems and method are provided for a memory circuit. In embodiments, the circuit includes a plurality of memory cells corresponding to a word of data and a global write word line. A plurality of local write lines are connected to a subset of the plurality of memory cells of the word of data. Selection logic is configured to activate a particular subset of memory cells for writing via a particular local write line based on a signal on the global write line and a selection signal associated with the particular subset of memory cells.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: March 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yi-Hsin Nien, Hidehiro Fujiwara, Yen-Huei Chen
  • Patent number: 11257826
    Abstract: A static random access memory (SRAM) cell has first to sixth transistors that are vertical nanowire (VNW) FETs. The second and fifth transistors are placed side by side sequentially on one side in the X direction of the first transistor. The fourth and sixth transistors are placed side by side sequentially on the other side in the X direction of the third transistor. The first and third transistors are placed side by side in the Y direction.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: February 22, 2022
    Assignee: SOCIONEXT INC.
    Inventor: Shinichi Moriwaki
  • Patent number: 11258596
    Abstract: A method for utilizing a plurality of physical unclonable function (PUF) cells to generate a signature key with a desired bit length is provided. The method includes setting a state of each of the plurality of PUF cells to a uniform level; obtaining an order of change in the state of at least a portion of the plurality of PUF cells; and generating the signature key at least based on the order.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: February 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shih-Lien Linus Lu, Cormac Michael O'Connell
  • Patent number: 11257824
    Abstract: A semiconductor device includes a plurality of first memory cells in a memory region and a first cut-off transistor in a dummy region, the dummy region being adjacent to the memory region. Each of the plurality of the first memory cells includes a static random access memory (SRAM) cell. The static random access memory cell includes a first pull-down transistor and a second pull-down transistor. The plurality of the first memory cells includes a first memory cell. A first source/drain region of the first pull-down transistor in the first memory cell is electrically coupled to a first source/drain region of the first cut-off transistor and a second source/drain region of the first cut-off transistor is electrically coupled to a power supply voltage.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: February 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Chih-Chuan Yang
  • Patent number: 11249658
    Abstract: The present invention is directed to computer storage systems and methods thereof. In an embodiment, a memory system comprises a controller module, a nonvolatile memory, and a volatile memory. The controller module operates according to a command and operation table. The command and operation table can be updated to change the way controller module operates. When the command and operation table is updated, the updated table is stored at a predefined location of the nonvolatile memory. There are other embodiments as well.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: February 15, 2022
    Assignee: Rambus, Inc.
    Inventors: Shih-ho Wu, Christopher Haywood
  • Patent number: 11238912
    Abstract: In an MRAM, each unit cell includes two non-volatile storage units, three N-type transistors and three P-type transistors. Each N-type transistor is coupled in parallel with a corresponding P-type transistor for forming a transmission gate which provides bi-directional current, thereby preventing source degeneration.
    Type: Grant
    Filed: January 11, 2021
    Date of Patent: February 1, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Ting Wu, Cheng-Tung Huang, Jen-Yu Wang, Yung-Ching Hsieh, Po-Chun Yang, Jian-Jhong Chen, Bo-Chang Li
  • Patent number: 11238918
    Abstract: A memory device includes a cell array including cells, an address transition detector outputting a transition detection signal as to whether an address of a write command is changed, and a control logic circuit generating one of word-line-on signals for performing a write operation on the cell array in response to the write command, and terminating the write operation in accordance with the transition detection signal. The word-line-on signals include a long-kept word-line-on signal that stays active before the address is changed and a divided word-line-on signal that is, before the address is changed, divided into sub-word-line-on signals.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: February 1, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Sang-Hoon Jung
  • Patent number: 11211387
    Abstract: Fin-based well straps are disclosed for improving performance of memory arrays, such as static random access memory arrays. An exemplary integrated circuit (IC) device includes a FinFET disposed over a doped region of a first type dopant. The FinFET includes a first fin having a first width doped with the first type dopant and first source/drain features of a second type dopant. The IC device further includes a fin-based well strap disposed over the doped region of the first type dopant. The fin-based well strap connects the doped region to a voltage. The fin-based well strap includes a second fin having a second width doped with the first type dopant and second source/drain features of the first type dopant. The second width is greater than the first width. For example, a ratio of the second width to the first width is greater than about 1.1 and less than about 1.5.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: December 28, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon Jhy Liaw
  • Patent number: 11211107
    Abstract: The present invention is directed to a nonvolatile memory device that includes a plurality of memory slices, each memory slice including one or more memory sectors and a read circuit for sensing the resistance state of a magnetic memory cell in the memory sectors. The read circuit includes first and second input nodes; a sense amplifier having first and second input terminals; a first target resistor and a balancing resistor connected in series between the first input node and the first input terminal; a multiplexer having a first input, a second input, and an output, with the first input being connected to the second input node and the output being connected to the second input terminal; a second target resistor and an offset resistor connected in series between the second input node and the second input; and first and second current sources connected to the first and second input terminals, respectively.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: December 28, 2021
    Assignee: Avalanche Technology, Inc.
    Inventors: Thinh Tran, Ebrahim Abedifard
  • Patent number: 11211502
    Abstract: Provided is a transistor, the transistor being located on a base and having an active layer, and the active layer of the transistor comprising a plurality of semiconductor patterns which are stacked, wherein the plurality of semiconductor patterns are electrically connected; and orthographic projections of any two of the semiconductor patterns on the base are different in shape. A method of manufacturing a transistor, a transistor device, and a display substrate and apparatus are also provided.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: December 28, 2021
    Assignees: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Lei Yan, Jianyun Xie, Yezhou Fang, Jun Fan, Feng Li
  • Patent number: 11205474
    Abstract: One aspect of this description relates to a memory cell including a first layer including a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure. The memory cell includes a second layer including a first active structure and a second active structure. The first gate structure overlaps the first active structure to form a first access transistor, the second gate structure overlaps the first active structure to form a first pull-down transistor, the third gate structure overlaps the first active structure to form a second pull-down transistor, and the fourth gate structure overlaps the first active structure to form a second access transistor. The second gate structure overlapping the second active structure to form a first pull-up transistor, the third gate structure overlapping the second active structure to form a second pull-up transistor.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: December 21, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chih-Chuan Yang, Feng-Ming Chang, Kuo-Hsiu Hsu, Ping-Wei Wang
  • Patent number: 11205476
    Abstract: A read register is provided that captures and stores the read result on a read bit line connected to a set of computational memory cells. The read register may be implemented in the set of computational memory cell to enable the logical XOR, logical AND, and/or logical OR accumulation of read results in the read register. The set of computational memory cells with the read register provides a mechanism for performing complex logical functions across multiple computational memory cells connected to the same read bit line.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: December 21, 2021
    Assignee: GSI TECHNOLOGY, INC.
    Inventors: Bob Haig, Eli Ehrman, Chao-Hung Chang, Mu-Hsiang Huang
  • Patent number: 11205475
    Abstract: A static random access memory (SRAM) includes a first memory cell array, a second memory cell array, a first data line coupled to the first memory cell array and the second memory cell array, a second data line coupled to the first memory cell array and the second memory cell array, a primary driver circuit coupled to at least the first data line, and a supplementary driver circuit coupled to at least the first data line. The supplementary driver circuit is configured to receive a supplementary driver circuit enable signal, sense a voltage of a first signal of the first data line, and pull the voltage of the first signal to a first voltage level during a write operation of the SRAM in response to at least a first NOR output signal.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: December 21, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Yu Lin, Wei-Cheng Wu, Kao-Cheng Lin, Yen-Huei Chen
  • Patent number: 11200924
    Abstract: In an exemplary embodiment, the disclosure provides a memory circuit which includes a dual port memory cell for storing a binary value accessed through a first port and a second port, a first WL switch connected to the dual port memory cell and controlled by a first WL voltage, a second WL switch connected to the dual port memory cell and controlled by a second WL voltage, a BL connected to the first WL switch for accessing the memory cell through the first port and having a first BL voltage, a second BL connected to the second WL switch for accessing the memory cell through the second port and having a second BL voltage, a BL selection circuit connected to the second WL switch for selecting the second BL, and a BL voltage pull down circuit connected to the BL selection circuit and the second WL switch.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: December 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jui-Che Tsai, Chia-En Huang, Yu-Hao Hsu, Yih Wang
  • Patent number: 11200935
    Abstract: Embodiments of 3D memory devices with a static random-access memory (SRAM) and fabrication methods thereof are disclosed herein. In one example, the method for operating a 3D memory device having an input/output circuit, an array of SRAM cells, and an array of 3D NAND memory strings in a same chip. The method may include transferring data through the input/output circuit to the array of SRAM cells, storing the data in the array of SRAM cells, and programming the data into the array of 3D NAND memory strings from the array of SRAM cells.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: December 14, 2021
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Yue Ping Li, Chun Yuan Hou
  • Patent number: 11189340
    Abstract: A memory device includes a plurality of memory cells located in a first region of the memory device. The memory cells include a first signal line, a first circuit located in the first region of the memory device, and a plurality of logic circuits located in a second region of the memory device. The second region and the first region have different design rules. The first circuit is configured to be selectively enabled and disabled. When the first circuit is enabled, the first signal line is electrically coupled in parallel with a second signal line.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: November 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Dian-Sheg Yu, Jhon Jhy Liaw, Ren-Fen Tsui, Bing-Chian Lin
  • Patent number: 11152376
    Abstract: The present disclosure is directed to a circuit layout of a dual port static random-access-memory (SRAM) cell. The memory cell includes active regions in a substrate, with polysilicon gate electrodes on the active regions to define transistors of the memory cell. The eight transistor (8T) memory cell layout includes a reduced aspect ratio and non-polysilicon bit line discharge path routing by positioning an active region for the first port opposite an active region for the second port and consolidating power line nodes at a central portion of the memory cell.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: October 19, 2021
    Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Tushar Sharma, Tanmoy Roy, Shishir Kumar
  • Patent number: 11145651
    Abstract: Briefly, embodiments of claimed subject matter relate to devices and methods for modifying, such as decreasing rise time and/or fall time, of a driver signal output. To achieve such modifications in driver output signals, additional gates may be positioned at PMOS and/or NMOS regions of a semiconductor film. In addition, at least in particular embodiments, etching of portions of one or more semiconductor regions may increase compressive or tensile stress, which may further operate to modify driver output signals.
    Type: Grant
    Filed: May 25, 2020
    Date of Patent: October 12, 2021
    Assignee: Arm Limited
    Inventors: Yew Keong Chong, Sriram Thyagarajan, Kumaraswamy Ramanathan, Damayanti Datta
  • Patent number: 11145660
    Abstract: A dual-port SRAM includes a substrate, first and second active regions over the substrate and oriented lengthwise generally along a first direction; first and second gate electrodes oriented lengthwise generally along a second direction perpendicular to the first direction. The first and second gate electrodes engage the first and second active regions to form first and second pass gate transistors, respectively. The dual-port SRAM further includes a first gate contact disposed over the first gate electrode and electrically connected to the first gate electrode and a first source/drain contact oriented lengthwise generally along the second direction. The first source/drain contact directly contacts source/drain features of the first and second pass gate transistors. A portion of the first gate contact and a portion of the first source/drain contact are at a same vertical level from a top surface of the substrate and are aligned along the first direction.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: October 12, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Dian-Sheg Yu, Ren-Fen Tsui, Jhon Jhy Liaw, Bing-Chian Lin
  • Patent number: 11133322
    Abstract: The disclosure provides a dual-port static random access memory cell layout structure, including a pull-down transistor layout structure, a first and a second pass transistor layout structure. Each of them includes an active region pattern and a polysilicon pattern; and contact hole patterns. The active region pattern of the pull-down transistor layout structure and the first pass transistor layout structure are connected together, and share the contact hole pattern at one end. The active region pattern of the pull-down transistor layout structure and the second pass transistor layout structure are connected together, and share the contact hole pattern at the other end. The disclosure optimizes the dual-port static random access memory cell layout structure, improves the influence of the optical fillet effect on device matching, strengthens the performance including read-write crosstalk of the pull-down transistor under the situation of the same area, and increases the read current.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: September 28, 2021
    Assignee: Shanghai Huali Integrated Circuit Corporation
    Inventors: Dongcheng Wu, Maocheng Fan
  • Patent number: 11127439
    Abstract: A semiconductor device including a FIFO circuit in which a data capacity can be increased while minimizing an increase in a circuit scale is provided. The semiconductor device includes a single-port type storage unit (11) which stores data, a flip-flop (12) which temporarily stores write data (FIFO input) or read data (FIFO output) of the storage unit (11), and a control unit (14, 40) which controls a write timing of a data signal, which is stored in the flip-flop (12), to the storage unit (11) or a read timing of the data signal from the storage unit to avoid an overlap between a write operation and a read operation in the storage unit (11).
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: September 21, 2021
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventor: Kenjiro Matoba
  • Patent number: 11100979
    Abstract: A low-power SRAM memory cell includes five word lines and four bit lines. The five word lines are a first word line, a second word line, a third word line, a fourth word line and a fifth word line. The four bit lines are a first bit line, a second bit line, a third bit line, and a fourth bit line. During the operation process of calculating a binary 10×11, the first word line is 1, the second word line is 0, the third word line is 0, the fourth word line is 1, the high bit stored in the bit cell is 1, and the low bit is 1. The voltage value of the fifth word line is 0.73 volt. At this time, the first bit line, the second bit line, and the third bit line do not discharge, while the fourth bit line discharges.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: August 24, 2021
    Assignee: SHANGHAITECH UNIVERSITY
    Inventors: Yuqi Wang, Yajun Ha
  • Patent number: 11087831
    Abstract: Static Random Access Memory (SRAM) cells and memory structures are provided. An SRAM cell according to the present disclosure includes a first pull-up gate-all-around (GAA) transistor and a first pull-down GAA transistor coupled to form a first inverter, a second pull-up GAA transistor and a second pull-down GAA transistor coupled to form a second inverter, a first pass-gate GAA transistor coupled to an output of the first inverter and an input of the second inverter, a second pass-gate GAA transistor coupled to an output of the second inverter and an input of the first inverter; a first dielectric fin disposed between the first pull-up GAA transistor and the first pull-down GAA transistor, and a second dielectric fin disposed between the second pull-up GAA transistor and the second pull-down GAA transistor.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: August 10, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon Jhy Liaw
  • Patent number: 11088083
    Abstract: In some embodiments, the present application provides a memory device. The memory device includes a chip that includes a magnetic random access memory (MRAM) cell. A magnetic-field-shielding structure at least partially surrounding the chip including a multilayer stack. The multilayer stack includes a magnetic layer and a dielectric layer. A first magnetic region is located inside an inner surface of the magnetic field shielding structure and a second magnetic region is located immediately outside an outer surface of the magnetic field shielding structure. A magnetic field in the first magnetic region is less than a magnetic field in the second magnetic region.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: August 10, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry-Hak-Lay Chuang, Tien-Wei Chiang, Kuo-An Liu, Chia-Hsiang Chen
  • Patent number: 11087837
    Abstract: A circuit cell for a memory device or a logic device comprises: (i) first and a second logic gates having respective output nodes; and (ii) first and second memory units, each comprising (a) first and second terminals and (b) a resistive memory element and a bipolar selector connected in series between the first and second terminals, wherein the first terminals of the first and second memory units are connected to the output nodes of the first and second logic gates, respectively, wherein the resistive memory elements are configured to be switchable between first and second resistance states, and wherein in response to a switching current and the bipolar selectors are configured to be conducting in response to an absolute value of a voltage difference across the bipolar selectors exceeding a threshold voltage of the bipolar selectors and non-conducting in response to the absolute value being lower than the threshold.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: August 10, 2021
    Assignee: IMEC vzw
    Inventors: Trong Huynh Bao, Sushil Sakhare
  • Patent number: 11079957
    Abstract: A storage system comprises a plurality of storage devices, with the storage devices comprising a first set of storage devices each having a first capacity and a second set of storage devices each having a second capacity higher than the first capacity. The storage system is further configured to establish an extended redundant array of independent disks (RAID) group to extend existing RAID stripes of the storage devices of the first set into the storage devices of the second set, and to establish an additional RAID group for the storage devices of the second set, the additional RAID group comprising one or more additional RAID stripes for the storage devices of the second set. The storage devices of the second set are illustratively added to the storage system to expand its capacity beyond that provided by the storage devices of the first set. Other embodiments include methods and computer program products.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: August 3, 2021
    Assignee: Dell Products L.P.
    Inventors: Lior Kamran, Vladimir Shveidel