Magnetoresistive Patents (Class 365/158)
  • Patent number: 10811095
    Abstract: A semiconductor storage device includes first lines second lines, and memory cells. The detection circuit detects data stored in the memory cells. A first transistor is electrically connected to the second lines between the memory cells and the detection circuit. A controller brings the first transistor to an intermediate state between an on-state and an off-state and thereafter brings the first transistor to the on-state to transmit a voltage of the second line to the detection circuit, in a data read operation, while a read voltage is applied to a first memory cell among the memory cells, the first memory cell being connected to a selected first line selectively driven from among the first lines and connected to a selected second line selectively driven from among the second lines, and the first transistor connected to the selected second line.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: October 20, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Takayuki Miyazaki
  • Patent number: 10803916
    Abstract: A method for selectively writing to STT-MRAM using an AC current is provided. The method is performed in a memory device including two or more multilevel magnetic tunnel junctions (MTJs) arranged in series with respect to a single terminal of a transistor, where the two or more multilevel MTJs include a first MTJ having a first magnetic characteristic and first electrical characteristic and a second MTJ having a second magnetic characteristic that is distinct from the first magnetic characteristic and a second electrical characteristic. The method includes writing to an MTJ. The writing includes applying a DC current to the two or more MTJs and applying an AC current to the two or more MTJs, where the AC current is adjusted to a frequency that is tuned to a write assist frequency corresponding to the respective MTJ.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: October 13, 2020
    Assignee: SPIN MEMORY, INC.
    Inventors: Kadriye Deniz Bozdag, Marcin Gajek, Michail Tzoufras, Eric Michael Ryan
  • Patent number: 10804459
    Abstract: Spintronic devices based on metallic antiferromagnets having a non-collinear spin structure are provided. Also provided are methods for operating the devices. The spintronic devices are based on a bilayer structure that includes a spin torque layer of an antiferromagnetic material having a non-collinear triangular spin structure adjoining a layer of ferromagnetic material.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: October 13, 2020
    Assignee: WISCONSIN ALUMNI RESEARCH FOUNDATION
    Inventors: Chang-Beom Eom, Tianxiang Nan
  • Patent number: 10802827
    Abstract: An in-situ in-memory implication gate is disclosed. The gate include a memory cell. The cell includes a first voltage source, a second voltage source lower in value than the first voltage source, a first and second magnetic tunneling junction devices (MTJ) selectively juxtaposed in a series and mirror imaged relationship between the first and second sources, each having a pinned layer (PL) in a first direction and a free layer (FL) having a polarity that can be switched from the first direction in which case the MTJ is in a parallel configuration presenting an electrical resistance to current flow below a first resistance threshold to a second direction in which case the MTJ is in an anti-parallel configuration presenting an electrical resistance to current flow higher than a second resistance threshold, and further each having a non-magnetic layer (NML) separating the PL from the FL.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: October 13, 2020
    Assignee: Purdue Research Foundation
    Inventors: Akhilesh Ramlaut Jaiswal, Amogh Agrawal, Kaushik Roy
  • Patent number: 10803917
    Abstract: A semiconductor storage device includes a first bank that includes a first memory cell group and writes data into the first memory cell group upon receipt of a first command, a second bank that includes a second memory cell group and writes data into the second memory cell group upon receipt of the first command, and a delay controller that issues the first command for the first bank upon receipt of a second command, and issues the first command for the second bank after an interval of at least a first period.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: October 13, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Fumiyoshi Matsuoka
  • Patent number: 10796741
    Abstract: A word line regulator provides a write word line voltage for an asserted word line and includes a write replica circuit, a reference current path, and a regulator circuit. The write replica circuit is a replica of a write path for writing from a low to high resistance value of a resistive memory element of a memory cell. The word line regulator regulates the word line voltage at a value during the write operation of a low to high resistance value such that a select transistor of the memory cell is used as a source follower to regulate a first node of a resistive element of the memory cell being written. The first node is at a higher write voltage than a second node of the resistive element during the write operation, and the first node is located in a write path between the select transistor and the second node.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: October 6, 2020
    Assignee: NXP USA, Inc.
    Inventors: Jacob T. Williams, Jon Scott Choy, Karthik Ramanan
  • Patent number: 10797231
    Abstract: A spin-orbit torque type magnetization reversal element including a ferromagnetic metal layer with a varying magnetization direction; and spin-orbit torque wiring that extends in a first direction intersecting with a stacking direction of the ferromagnetic metal layer and that is joined to the ferromagnetic metal layer; wherein when viewed from the first direction, the spin-orbit torque wiring is asymmetrical in a second direction that is orthogonal to the first direction and the stacking direction, with respect to an axis that passes through a center, in the second direction, of the ferromagnetic metal layer.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: October 6, 2020
    Assignee: TDK CORPORATION
    Inventors: Tomoyuki Sasaki, Yohei Shiokawa
  • Patent number: 10790002
    Abstract: A non-volatile data retention circuit includes a complementary latch configured to generate and store complementary non-volatile spin states corresponding to an input signal when in a write mode, and to concurrently generate a first charge current signal and a second charge current corresponding to the complementary non-volatile spin states when in read mode, and a differential amplifier coupled to the complementary latch and configured to generate an output signal based on the first and second charge current signals.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: September 29, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Titash Rakshit, Ryan Hatcher, Jorge A. Kittl
  • Patent number: 10790016
    Abstract: Neuron circuit structures are presented which employ magnetic tunnel junction (MTJ) elements that change state probabilistically in response to application of electrical source currents that emulate synaptic activity. Some implementations form probabilistic neuron circuits using homogeneous perpendicular spin-transfer torque (STT) MTJ elements. These neuron circuits include a perpendicular STT reference MTJ element coupled via an electrical node with a perpendicular STT neuron MTJ element that can change state. The electrical node for each neuron circuit couples a neuron MTJ element or “perturbation” element to a reference element, and also to an electrical current employed to influence probabilistic magnetization state changes in the perturbation MTJ element. A read current can be applied to the perturbation element to produce an output voltage at the electrical node indicative of a magnetization state of the perturbation element.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: September 29, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Won Ho Choi, Young-Suk Choi
  • Patent number: 10783933
    Abstract: A semiconductor memory device includes a power source pad, a first bank including a plurality of memory cells, a second bank including a plurality of memory cells, the first bank being sandwiched between the power source pad and the second bank, first power supply lines connected to the power source pad and supplying power to the first bank and not to the second bank, and second power supply lines connected to the power source pad, passing over the first bank, and supplying power to the second bank and not to the first bank.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: September 22, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Fumiyoshi Matsuoka, Katsuyuki Fujita
  • Patent number: 10783944
    Abstract: In example embodiments, a SOT magnetic memory and operation method are provided that utilize SOT driven domain wall motion to achieve subsequent switching without the need for an external assist magnetic field. The magnetic memory includes a magnetic tunnel junction having a reference layer, a tunnel barrier layer and a free layer, where the tunnel barrier layer is positioned between the reference layer and free layer. A spin-orbit torque layer is disposed adjacent to the free layer. A pair of pinning site are positioned at a longitudinal end of the free layer and each has an opposite magnetization direction from the other. The SOT layer is configured to exert SOT and switch a magnetization direction of the free layer via domain wall motion in a direction of current flow when an electric current is passed through a length of the SOT layer.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: September 22, 2020
    Assignee: National University of Singapore
    Inventors: Jongmin Lee, Rajagopalan Ramaswamy, Hyunsoo Yang
  • Patent number: 10777734
    Abstract: In a non-limiting embodiment, a magnetic memory device includes a memory component having a plurality of magnetic storage elements for storing memory data, and one or more sensor components configured to detect a magnetic field external to the memory component. The sensor component outputs a signal to one or more components of the magnetic memory device based on the detected magnetic field. The memory component is configured to be terminated when the signal is above a predetermined threshold value. In some embodiments, a magnetic field is generated in a direction opposite to the direction of the detected external magnetic field when the signal is above the predetermined threshold value.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: September 15, 2020
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Bin Liu, Eng Huat Toh, Samarth Agarwal, Ruchil Kumar Jain, Kiok Boone Elgin Quek
  • Patent number: 10769010
    Abstract: A DRAM device includes first terminals, second terminals, third terminals, a control signal generator, a CRC unit, a row decoder, a column decoder, and a memory cell array. The control signal generator generates a control signal. The CRC unit performs a first CRC logical operation on a first data group including qn-bit first data generated by inputting n-bit first data q times, generates a first CRC result signal, performs a second CRC logical operation on a second data group including qn-bit second data by inputting n-bit second q times, generates a second CRC result signal, and generates an error signal based on the first CRC result signal and the second CRC result signal. The error signal is generated based on the second CRC result signal regardless of the first CRC result signal in response to the control signal.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: September 8, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong Pil Son, Sin Ho Kim
  • Patent number: 10762942
    Abstract: An example device for performing a write operation using a spintronic Hall effect includes a Spin Hall Effect (SHE) structure, a Magnetic Tunnel Junction (MTJ) element, and processing circuitry. The MTJ element includes a free structure, a pinned structure, and a tunnel barrier arranged between the free structure and the pinned structure. The free structure comprises a plurality of free layers. The free structure is arranged with the SHE structure such that current in the SHE structure induces spin transfer into the free structure. The processing circuitry is configured to receive an instruction to set the MTJ element to a target state of a plurality of states and in response to receiving the instruction, generate electrical current through the spin Hall effect structure to modify a resistance of the MTJ element to correspond to the target state.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: September 1, 2020
    Assignee: Honeywell International Inc.
    Inventor: Romney R. Katti
  • Patent number: 10762932
    Abstract: A memory device includes a memory cell array that includes memory cells, a row decoder that is connected to the memory cell array through word lines, a column decoder that is connected to the memory cell array through bit lines and source lines, a write driver that transfers a write voltage to a bit line, which is selected by the column decoder, from among the bit lines by using a gate voltage in a write operation, and control logic that generates the gate voltage. The gate voltage is higher than the write voltage.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: September 1, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Artur Antonyan
  • Patent number: 10762958
    Abstract: A method of controlling a reference cell in a resistive memory to identify values stored in a plurality of memory cells is provided. The method includes writing a first value to the plurality of memory cells, providing, to the reference cell, monotonically increasing or monotonically decreasing reference currents. The method includes reading the plurality of memory cells as each of the reference currents is provided to the reference cell, and determining a read reference current based on an aggregation of results of the reading.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: September 1, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Suk-soo Pyo, Hyun-taek Jung, So-hee Hwang, Tae-joong Song
  • Patent number: 10762941
    Abstract: A spin-orbit torque magnetization rotating element includes a spin-orbit torque wiring and a laminated body laminated on the spin-orbit torque wiring. The laminated body includes a first ferromagnetic layer independently having an axis of easy magnetization in a first direction, a nonmagnetic antiferromagnetic coupling layer, and a second ferromagnetic layer independently having an axis of easy magnetization in a second direction, in order from the side of the spin-orbit torque wiring, and the first direction crosses the second direction.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: September 1, 2020
    Assignee: TDK CORPORATION
    Inventor: Yohei Shiokawa
  • Patent number: 10756262
    Abstract: A spin-orbit-torque magnetization rotational element includes: a spin-orbit-torque wiring which extends in a first direction; and a first ferromagnetic layer which is laminated in a second direction intersecting the spin-orbit-torque wiring, wherein the spin-orbit-torque wiring includes a convex portion which protrudes in the second direction in relation to a first surface on the side of the first ferromagnetic layer at a connecting part between the spin-orbit-torque wiring and the first ferromagnetic layer.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: August 25, 2020
    Assignee: TDK CORPORATION
    Inventors: Eiji Komura, Yohei Shiokawa
  • Patent number: 10748614
    Abstract: In order to provide a highly reliable crossbar circuit that enables salvation of reversal of a resistive state of a variable resistance element, the semiconductor device has a configuration obtained by parallelly arranging two unit elements, each including variable-resistance two-terminal elements connected in series, the semiconductor device being provided with: a unit element group being connected to a first wiring and a second wiring; a first programming driver that changes, via the first wiring, a resistive state of the two-terminal element constituting the unit element group; a first selection transistor being connected to the first wiring and the first programming driver; a second programming driver that changes, via the second wiring, a resistive state of the two-terminal element constituting the unit element group; and a second selection transistor being connected to the second wiring and the second programming driver.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: August 18, 2020
    Assignee: NEC CORPORATION
    Inventors: Makoto Miyamura, Ryusuke Nebashi, Toshitsugu Sakamoto, Yukihide Tsuji, Xu Bai, Ayuka Tada
  • Patent number: 10749107
    Abstract: A magnetic tunnel junction element configured by stacking, in a following stack order, a fixed layer formed of a ferromagnetic body and in which a magnetization direction is fixed, a magnetic coupling layer formed of a nonmagnetic body, a reference layer formed of a ferromagnetic body and in which the magnetization direction is fixed, a barrier layer formed of a nonmagnetic body, and a recording layer formed of a ferromagnetic body, a barrier layer formed of a nonmagnetic body, and a recording layer formed by sandwiching an insertion layer formed of a nonmagnetic body between first and second ferromagnetic layers, wherein the magnetic coupling layer is formed using a sputtering gas in which a value of a ratio in which a mass number of an element used in the magnetic coupling layer divided by the mass number of the sputtering gas itself is 2.2 or smaller.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: August 18, 2020
    Assignee: TOHOKU UNIVERSITY
    Inventors: Hiroaki Honjo, Shoji Ikeda, Hideo Sato, Tetsuo Endoh, Hideo Ohno
  • Patent number: 10741232
    Abstract: A memory device comprising a memory array of a plurality of memory bit cells; a read reference system comprising four or more reference memory bit cells in a reference column of the memory array; wherein a first bit cell of the reference memory bit cells is always selected; wherein a bitline of the first bit cell of the reference memory bit cells is connected to a bitline of a first subset of the reference memory bit cells, and a select line of the first bit cell of the reference memory bit cells is connected to a reference select signal; wherein a select line of each of the first subset of the reference memory bit cells and a second subset of the reference memory bit cells are coupled together; and wherein a bitline blref of the second subset of the reference memory bit cells outputs a read reference signal.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: August 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kotb Jabeur, John Kenneth DeBrosse
  • Patent number: 10732933
    Abstract: True random number generation (TRNG) circuits are presented which employ magnetic tunnel junction (MTJ) elements that can change magnetization state probabilistically in response to application of electrical pulses. Some implementations include pulse generators which apply perturbation sequences to the MTJ elements. The MTJ elements responsively produce randomized outputs related to changes in magnetization states. Probability compensators are included which monitor for deviations in measured probabilities in the randomized outputs from a target probability. The probability compensators make adjustments to the perturbation sequences to influence probabilistic changes in the magnetization states of the MTJ elements and bring the measured probabilities to within a predetermined deviation from the target probability.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: August 4, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Won Ho Choi
  • Patent number: 10734052
    Abstract: A bit cell driving mechanism is disclosed. The mechanism includes a bit cell which includes a first magnetic tunnel junction (MTJ) cell, including a pinned layer, a non-magnetic layer, a free layer having two magnetic regions separated by a laterally moveable domain wall, and a spin-hall metal layer configured to receive an electrical current therethrough which causes the DW to move laterally. The mechanism also includes a second MTJ cell coupled to the first MTJ cell as well as an interconnect driver configured to provide electrical current to the first MTJ cell during a write operation.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: August 4, 2020
    Assignee: Purdue Research Foundation
    Inventors: Zubair Al Azim, Ankit Sharma, Kaushik Roy
  • Patent number: 10734054
    Abstract: A magnetic structure includes a magnetic tunnel junction based on a synthetic antiferromagnetic free layer which is regulated by an electric field, and a spin-orbit layer located below the magnetic tunnel junction. The transformation from the antiferromagnetic coupling to the ferromagnetic coupling of the free layer based on a synthetic antiferromagnetic multilayer structure is controlled by an electric field. A spin-orbit torque magnetic random access memory, which includes the magnetic structure, is able to realize stable data writing under the combined interaction of electric field and current, and has advantages of simple structure for scaling, ultralow power consumption, ultrahigh speed of switching, radiation resistance and non-volatility.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: August 4, 2020
    Assignee: XI'AN JIAOTONG UNIVERSITY
    Inventors: Tai Min, Xue Zhou, Xuesong Zhou, Lei Wang
  • Patent number: 10734055
    Abstract: A memory device according to an embodiment includes: a plurality of memory cells including a storage element having a first and second terminals; a reference resistor having a third and fourth terminals; a first current source electrically connected to the first terminal of the storage element in the selected memory cell; a second current source electrically connected to the third terminal; and a determination circuit that determines the greater one among a resistance value of a storage element of selected one and a resistance value of the reference resistor, the resistance value of the reference resistor being smaller than a middle value between a mean value of first resistance values obtained from the storage elements in the high-resistance state and a mean value of second resistance values obtained from the storage elements in the low-resistance state, and greater than the mean value of the second resistance values.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: August 4, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideyuki Sugiyama, Naoharu Shimomura, Kazutaka Ikegami
  • Patent number: 10734076
    Abstract: A semiconductor memory cell and arrays of memory cells are provided In at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type, the second region being formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; a gate positioned between the
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: August 4, 2020
    Assignee: Zeno Semiconductor, Inc.
    Inventor: Yuniarto Widjaja
  • Patent number: 10726892
    Abstract: A MRAM device includes a spin valve containing a reference layer having a fixed magnetization direction, a free layer, and a nonmagnetic metallic barrier layer located between the reference layer and the free layer, a metallic assist structure configured to provide rotating spin transfer torque to the free layer to assist the free layer switching during programming, and a first nonmagnetic metallic spacer layer located between the free layer and the metallic assist structure.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: July 28, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Quang Le, Zhanjie Li, Zhigang Bai, Paul Vanderheijden, Michael Ho
  • Patent number: 10726896
    Abstract: A memory structure includes a first memory array with two transistor-two variable resistor memory cells and a second memory array with one transistor-one variable resistor memory cells, which are each selectively operable in read, write and standby modes. The first memory array and the second memory array are interleaved so that, when the second memory operates in the read mode, the first memory array automatically and concurrently operates in a reference mode. A method of operating the memory structure includes, when the second memory array operates in the read mode, automatically and concurrently operating the first memory array in the reference mode so that the first memory array generates and outputs a statistical reference voltage, which is between the low and high voltages of a nominal memory cell within the second memory array and which is employed by the second memory array to sense a stored data value.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: July 28, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ajey Poovannummoottil Jacob, Amogh Agrawal
  • Patent number: 10720469
    Abstract: The present invention is directed to a magnetic structure including a first seed layer, a second seed layer formed on top of the first seed layer, and a third seed layer made of chromium or iridium formed on top of the second seed layer. One of the first and second seed layers comprises cobalt, iron, and boron. The other one of the first and second seed layers is made of iridium, rhodium, cobalt, platinum, palladium, nickel, ruthenium, or rhenium. The magnetic structure further includes a magnetic fixed layer structure formed on top of the third seed layer and having an invariable magnetization direction substantially perpendicular to a layer plane thereof. The magnetic fixed layer structure includes layers of a magnetic material interleaved with layers of a transition metal. The transition metal may be nickel, platinum, palladium, or iridium.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: July 21, 2020
    Assignee: Avalanche Technology, Inc.
    Inventors: Zihui Wang, Yiming Huai
  • Patent number: 10706926
    Abstract: Subject matter disclosed herein relates to memory devices and, more particularly, to programming a memory cell.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: July 7, 2020
    Assignee: OVONYX MEMORY TECHNOLOGY, LLC
    Inventors: Umberto Di Vincenzo, Carlo Lisi
  • Patent number: 10707219
    Abstract: A semiconductor integrated circuit of an embodiment includes: first to fifth wiring lines; a first OTP memory element including a first and second terminals connected to the first and second wiring lines; a first p-channel transistor including a source and drain terminals connected to the first and third wiring line, and a gate terminal receiving a first control signal; a first n-channel transistor including a source and drain terminals connected to the first and fourth wiring lines, and a gate terminal receiving a second control signal; a second p-channel transistor including a source and drain terminals connected to the second and third wiring lines, and a gate terminal receiving a third control signal; and a second n-channel transistor including a source and drain terminals connected to the second and fifth wiring lines, and a gate terminal receiving a fourth control signal.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: July 7, 2020
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yinghao Ho, Masato Oda, Shinichi Yasuda
  • Patent number: 10706903
    Abstract: A nonvolatile memory cell includes a layered structure body formed by layering a storage layer that stores information in accordance with a magnetization direction and a magnetization fixed layer that defines a magnetization direction of the storage layer; and a heating layer that heats the magnetization fixed layer to control a magnetization direction of the magnetization fixed layer.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: July 7, 2020
    Assignee: Sony Corporation
    Inventors: Yutaka Higo, Masanori Hosomi, Hiroyuki Ohmori, Kazuhiro Bessho, Hiroyuki Uchida
  • Patent number: 10706905
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to a single path memory sense amplifier circuit and methods of manufacture. The circuit includes a sense amplifier circuit comprising a plurality of self-aligned transistors in a single sensing path; and a memory array connected to the sense amplifier circuit by the single sensing path.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: July 7, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yentsai Huang, Chunsung Chiang, Wuyang Hao, Jack T. Wong, Lejan Pu
  • Patent number: 10707414
    Abstract: A radio frequency (RF) switch includes a phase-change material (PCM) and a heating element underlying an active segment of the PCM, the PCM and heating element being situated over a substrate. A contact dielectric is over the PCM. PCM contacts have upper portions and uniform plate slot lower portions. The uniform plate slot lower portions have a total plate resistance RPLATE, and a total plate slot interface resistance RPLATE-INT. The upper portions have a total capacitance CUPPER to the uniform plate slot lower portions, and the PCM has a total capacitance CPCM to the substrate. The uniform plate slot lower portions significantly reduce a product of (RPLATE+RPLATE-INT) and (CUPPER+CPCM). As an alternative to the uniform plate slot lower portions, PCM contacts have segmented lower portions. The segmented lower portions significantly reduce CUPPER.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: July 7, 2020
    Assignee: Newport Fab, LLC
    Inventors: David J. Howard, Jefferson E. Rose, Gregory P. Slovin, Nabil El-Hinnawy, Michael J. DeBar
  • Patent number: 10699765
    Abstract: Circuits and methods for programming a MTJ stack of an MRAM cell minimizes a ferromagnetic free layer or pinned layer polarization reversal due to back-hopping. The programming begins by applying a first segment of the segment of the write pulse at a first write voltage level for a first time period to program the MTJ stack. A second segment of the segment of the write pulse at a second write voltage level that is less than the first write voltage level is applied to the magnetic tunnel junction stack for a second time period to correct the polarization of the MTJ when the MTJ stack has reversed polarization during the first time period. The second segment of the segment of the write pulse may be a ramp, or multiple ramps, or have a quiescent period between it and the first segment of the write pulse.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: June 30, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Huanlong Liu, Guenole Jan, Yuan-Jen Lee, Jian Zhu, Po-Kang Wang
  • Patent number: 10699763
    Abstract: The present disclosure relates to a structure which includes a merged write driver circuit with a first device next to a first memory array and a second device next to a second memory array, and the merged write driver circuit being configured to share a write driver line between the first device and the second device.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: June 30, 2020
    Assignee: Marvell International Ltd.
    Inventors: Wuyang Hao, Jack T. Wong, Chunsung Chiang
  • Patent number: 10699784
    Abstract: The present disclosure includes apparatuses and methods for sensing a resistive memory cell. A number of embodiments include performing a sensing operation on a memory cell to determine a current value associated with the memory cell, applying a programming signal to the memory cell, and determining a data state of the memory cell based on the current value associated with the memory cell before applying the programming signal and a current value associated with the memory cell after applying the programming signal.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: June 30, 2020
    Assignee: Micron Technology, Inc.
    Inventors: D.V. Nirmal Ramaswamy, Gurtej S. Sandhu, Lei Bi, Adam D. Johnson, Brent Keeth, Alessandro Calderoni, Scott E. Sills
  • Patent number: 10693055
    Abstract: Magnetic random access memory (MRAM) devices are provided. The MRAM devices may include a magnetic tunnel junction (MTJ) including a free layer and a pinned layer sequentially stacked in a vertical direction and a conductive layer adjacent to the free layer of the MTJ. The conductive layer may include a horizontal portion and first and second protruding portions that protrude away from the horizontal portion and are spaced apart from each other in a horizontal direction that is perpendicular to the vertical direction. A side of the free layer and a side of the horizontal portion may form a straight side.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: June 23, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kilho Lee, Gwanhyeob Koh, Yoonjong Song
  • Patent number: 10693054
    Abstract: A method of forming a memory cell with a high aspect ratio metal via formed underneath a metal tunnel junction (MTJ) and the resulting device are provided. Embodiments include a device having a metal via formed underneath a metal tunnel junction (MTJ) in a memory cell, and the metal via has an aspect ratio smaller than 2.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: June 23, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Danny Pak-Chum Shum, Wanbing Yi, Curtis Chun-I Hsieh, Yi Jiang, Juan Boon Tan, Benfu Lin
  • Patent number: 10686123
    Abstract: A multilayered magnetic free layer structure is provided that includes a first magnetic free layer and a second magnetic free layer separated by a non-magnetic layer in which the second magnetic free layer has higher magnetic damping (greater than 0.01) as compared with the first magnetic free layer. Such a multilayered magnetic free layer structure substantially reduces the switching current needed to reorient the magnetization of the magnetic free layers. The higher magnetic damping value of the second magnetic free layer as compared to the first magnetic free layer improves the switching speed of the magnetic free layers and thus reduces, and even eliminates, write errors.
    Type: Grant
    Filed: August 16, 2018
    Date of Patent: June 16, 2020
    Assignee: International Business Machines Corporation
    Inventors: Guohan Hu, Daniel Worledge
  • Patent number: 10685693
    Abstract: A method of manufacturing an array of magnetic random access memory cells includes writing to a magnetic random access memory cell. The writing to a memory cell includes determining an optimum write current for the array of memory cells, and applying the optimum write current to a first memory cell in the array. A first read current is applied to the first memory cell to determine whether a magnetic orientation of the first memory cell has changed in response to applying the optimum write current. A second write current is applied to the first memory cell when the magnetic orientation of the first memory cell has not changed. The second write current is different from the optimum write current. A second read current is applied to the first memory cell to determine whether the magnetic orientation of the first memory cell changed in response to applying the second write current.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ji-Feng Ying, Jhong-Sheng Wang, Baohua Niu
  • Patent number: 10679685
    Abstract: A magnetoresistive memory architecture in one aspect includes a plurality of bit lines each coupled to two or more respective columns of magnetoresistive memory cells, and a plurality of source lines each coupled to a respective one of the columns of memory cells. A given memory cell can be accessed by biasing a selected word line, a selected bit line, and a selected source line coupled to corresponding column of memory cells coupled to the selected bit line, and by counter biasing one or more selected source lines coupled to one or more other columns of memory cells coupled to the selected bit line.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: June 9, 2020
    Assignee: Spin Memory, Inc.
    Inventors: Loc Hoang, Amitay Levi
  • Patent number: 10679686
    Abstract: A magnetoresistive memory device includes a memory cell including a magnetic tunnel junction element, a detector to detect a current value writable in units of the memory cell, a current value storage area, and a current controller. The current value storage area stores at least one of a maximum value and a minimum value of the writable current value detected by the detector. The current controller performs at least one control operation of an operation of controlling a write current value of the memory cell based on the maximum value and an operation of controlling a read current value of the memory cell based on the minimum value.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: June 9, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Masatoshi Sonoda, Yoshiaki Sonobe, Takeshi Kato
  • Patent number: 10672975
    Abstract: A device includes a metal layer comprising a plurality of bottom electrode features. The device further includes a Magnetic Tunnel Junction (MTJ) stack layer comprising a plurality of MTJ stack features, each of the MTJ stack features disposed on a top surface of one of the plurality of bottom electrode features. The device further includes sidewall structures that extend along side surfaces of both the bottom electrode features and the MTJ stack features.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: June 2, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Carlos H. Diaz, Harry-Hak-Lay Chuang, Ru-Liang Lee
  • Patent number: 10672832
    Abstract: A magnetic detection circuit for a magnetic random access memory (MRAM) is provided. The magnetic detection circuit includes a sensing array including a plurality of sensing cells and a controller. Each of the sensing cells includes a first magnetic tunnel junction (MTJ) device. The controller is configured to access the first MRAM cells to detect the external magnetic field strength of the MRAM. The controller determines whether to stop the write operation of a plurality of memory cells of the MRAM according to the external magnetic field strength of the MRAM, and each of the memory cells includes a second MTJ device. The first MTJ device is smaller than the second MTJ device.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: June 2, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ji-Feng Ying, Baohua Niu
  • Patent number: 10665281
    Abstract: A device is disclosed including a first resistive storage element, a first access transistor having a first terminal coupled to the first resistive storage element at a first node, a second resistive storage element, a second access transistor having a first terminal coupled to the second resistive storage element at a second node, and a write assist transistor having a first terminal coupled to the first node and a second terminal coupled to the second node.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: May 26, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ajey Poovannummoottil Jacob, Amogh Agrawal, Bipul C. Paul
  • Patent number: 10665773
    Abstract: A magnetic tunnel junction (MTJ) is disclosed wherein first and second interfaces of a free layer (FL) with a first metal oxide (Hk enhancing layer) and second metal oxide (tunnel barrier), respectively, produce perpendicular magnetic anisotropy (PMA) to increase thermal stability. In some embodiments, a capping layer that is a conductive metal nitride such as MoN contacts an opposite surface of the Hk enhancing layer with respect to the first interface to reduce interdiffusion of oxygen and nitrogen compared with a TiN capping layer and maintain an acceptable resistance×area (RA) product. In other embodiments, the capping layer may comprise an insulating nitride such as AlN that is alloyed with a conductive metal to minimize RA. Furthermore, a metallic buffer layer may be inserted between the capping layer and Hk enhancing layer. As a result, electrical shorts are reduced and the magnetoresistive ratio is increased.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: May 26, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jodi Mari Iwata, Guenole Jan, Ru-Ying Tong, Vignesh Sundar, Jian Zhu, Huanlong Liu
  • Patent number: 10658035
    Abstract: A method is provided for a reading memory even if there is a threshold voltage in an overlapped threshold voltage (VTH) region between a first state distribution and a second state distribution. The method includes ramping a bias on a memory cell a first time to determine a first threshold voltage (VTH1) of the memory cell and determining whether the VTH1 is within the overlapped VTH region. Upon determination that the memory cell is within the overlapped VTH region, the method further includes applying a write pulse to the memory cell; ramping a bias on the memory cell a second time to determine a second threshold voltage (VTH2); and determining the state of the memory cell prior to receiving the write pulse based on a comparison between the VTH1 and the VTH2.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: May 19, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Innocenzo Tortorelli, Fabio Pellizzer, Ferdinando Bedeschi
  • Patent number: 10658021
    Abstract: A magnetic storage device includes a plurality of first wires extending along a first direction and a plurality of second wires extending along a second direction different from the first direction. The plurality of second wires form a grid with the plurality of first wires. The magnetic storage device further includes a plurality of spin orbit torque magnetic random access memory (SOT-MRAM) devices. Each of the plurality of SOT-MRAM devices is disposed at a respective position on the grid. The magnetic storage device further includes write circuitry, including a transistor coupled to each respective first wire of the plurality of first wires, to apply a first write current along the respective first wire in the first direction, and readout circuitry to read a data value stored by a respective SOT-MRAM device.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: May 19, 2020
    Assignee: SPIN MEMORY, INC.
    Inventor: Satoru Araki
  • Patent number: 10658575
    Abstract: Techniques are presented for ensuring alignment marks are available for use and patterning magnetoresistive devices following the deposition of layers used to form the magnetoresistive devices. In some cases, the plurality of layers corresponding to the magnetoresistive devices are selectively etched in order to expose the underlying alignment marks, whereas in other embodiments, the deposition of the plurality of layers is controlled by deposition tool tabs that prevent the materials from obscuring the underlying alignment marks.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: May 19, 2020
    Assignee: Everspin Technologies, Inc.
    Inventor: Kerry Joseph Nagel