Magnetoresistive Patents (Class 365/158)
  • Patent number: 10447277
    Abstract: An integrated logic device includes a channel having an interconnect section and a pair of spin-orbit segments connected to the interconnect section at either end of the interconnect section. A P structure includes a P magnet disposed on a surface of a spin-orbit segment. A tunneling barrier is disposed between the P magnet and a Rp magnetic reference layer. A Q structure includes a Q magnet disposed on a surface of the other spin-orbit segment. A tunneling barrier is disposed between the Q magnet and a Rq magnetic reference layer. A method of integrated logic spin-orbit perpendicular-anisotropy (SOPE) gate device operation is also described.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: October 15, 2019
    Assignee: University of Rochester
    Inventor: Mohammad Kazemi
  • Patent number: 10446211
    Abstract: A semiconductor storage device includes a plurality of first memory elements in a first region and a plurality of second memory elements in a second region. The second memory elements each have a physical volume that is greater than a physical volume of the first memory elements. A controller is configured to first write data to the plurality of first memory elements and then transfer the data written to plurality of first memory elements to the plurality of second memory elements when at least one of an elapsed time since initial writing or a data reading frequency exceeds a threshold value. In general, the first memory elements and the second memory elements are variable resistance elements.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: October 15, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Hiroaki Maekawa
  • Patent number: 10446745
    Abstract: A method of manufacturing a magnetoresistive random access memory cell includes the following steps. A first dielectric layer including a first metal line therein is formed on a substrate. A patterned second dielectric layer is formed over the first dielectric layer, wherein the patterned second dielectric layer includes a recess exposing the first metal line. A barrier layer conformally covers the recess and the patterned second dielectric layer. A metal fills up the recess and on the barrier layer. The metal is planarized until the barrier layer being exposed by serving the barrier layer as a stop layer. A magnetic tunneling junction and a top electrode over the metal are formed, thereby a magnetoresistive random access memory cell being formed.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: October 15, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Kun-Ju Li
  • Patent number: 10446208
    Abstract: A magnetic device comprising having a first magnetic layer having a first magnetization direction, a second magnetic layer having a second magnetization direction, a first coupling layer interposed between the first and second magnetic layers, a third magnetic layer having a third magnetization direction, a first magnetoresistive layer interposed between the third magnetic layer and the second magnetic layer, and a circuit connected to one or more of the layers of the magnetic device by at least a pair of leads. The circuit is configured to determine a change in resistance between the pair of leads. The change in resistance is based at least in part on a change in an angular relationship between the third magnetization direction and the second magnetization direction caused by an external magnetic field or a current passing through at least a portion of the device.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: October 15, 2019
    Assignee: Simon Fraser University
    Inventors: Zachary Raymond Nunn, Erol Girt
  • Patent number: 10446205
    Abstract: Spin transfer torque magnetic random access memory structures, integrated circuits, and methods for fabricating integrated circuits are provided. An exemplary spin transfer torque magnetic random access memory structure has a perpendicular magnetic orientation, and includes a bottom electrode, a seed layer over the bottom electrode, a hard layer over the seed layer, a magnetically continuous transition layer over the hard layer, a reference layer over the magnetically continuous transition layer, a tunnel barrier layer over the reference layer, a storage layer formed over the tunnel barrier layer, and a top electrode. The reference layer, the tunnel barrier layer, and the storage layer form a magnetic tunnel junction (MTJ) element with a perpendicular orientation.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: October 15, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Taiebeh Tahmasebi, Dimitri Houssameddine, Michael Nicolas Albert Tran, Chenchen Jacob Wang
  • Patent number: 10438995
    Abstract: A Magnetic Tunnel Junction (MTJ) device can include an array of cells. The array of cells can include a plurality of source lines disposed in columns, set of selectors coupled to respective source lines, MJT structures coupled to respective selectors and a plurality of bit lines disposed in rows and coupled to respective sets of MTJ structures. The array of cells can also include buffers coupled between respective selectors and respective MTJ structures. In addition, multiple arrays can be stacked on top of each other to implement vertical three-dimensional (3D) MTJ devices.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: October 8, 2019
    Assignee: SPIN MEMORY, INC.
    Inventors: Kuk-Hwan Kim, Dafna Beery, Andy Walker, Amity Levi
  • Patent number: 10439829
    Abstract: A physical unclonable function code generating method includes: providing a plurality of non-volatile memory cell pairs including a first non-volatile memory cell and a second non-volatile memory cell; comparing an initial state of the first non-volatile memory cell with an initial state of the second non-volatile memory cell, and generating a first physical unclonable function code according to a comparison result of the state; calculating a formation ratio difference of a logical level in the first physical unclonable function code; and adjusting the formation ratio difference by interactively performing forming operations on the first non-volatile memory cell and the second non-volatile memory cell when the formation ratio difference is greater than or equal to a ratio threshold.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: October 8, 2019
    Assignee: Winbond Electronics Corp.
    Inventors: Lih-Wei Lin, Chi-Shun Lin, Seow Fong Lim
  • Patent number: 10438639
    Abstract: Various memory devices and associated methods of operation are disclosed herein. An exemplary method includes flowing a current through an electrode of a memory device. The current exerts a spin-torque for orienting a magnetic field of a magnetic layer of the memory device and produces a magnetic field in the electrode that assists in orienting the magnetic field of the magnetic layer. The current can produce the magnetic field in the electrode when flowing through a region of the electrode having a winding orientation that is substantially perpendicular to a longitudinal axis of the memory device. In some implementations, flowing the current through the electrode includes storing data in the memory device.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: October 8, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Chwen Yu
  • Patent number: 10438998
    Abstract: Integrated circuit devices may include a substrate including a flash memory region and a variable resistance memory region, a flash memory cell transistor including a cell gate electrode that overlaps the flash memory region of the substrate, a variable resistance element that overlaps the variable resistance memory region of the substrate, and a select transistor including a select source/drain region that is disposed in the variable resistance memory region of the substrate. The select source/drain region may be electrically connected to the variable resistance element. The substrate may include an upper surface facing the cell gate electrode and the variable resistance element, and the upper surface of the substrate may continuously extend from the flash memory region to the variable resistance memory region.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: October 8, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kilho Lee, Gwanhyeob Koh, Hongsoo Kim, Junhee Lim, Chang-Hoon Jeon
  • Patent number: 10431279
    Abstract: A magnetoresistive memory device includes a memory cell including a magnetic tunnel junction element, a detector to detect a current value writable in units of the memory cell, a current value storage area, and a current controller. The current value storage area stores at least one of a maximum value and a minimum value of the writable current value detected by the detector. The current controller performs at least one control operation of an operation of controlling a write current value of the memory cell based on the maximum value and an operation of controlling a read current value of the memory cell based on the minimum value.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: October 1, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Masatoshi Sonoda, Yoshiaki Sonobe, Takeshi Kato
  • Patent number: 10431277
    Abstract: According to one embodiment, a memory device includes a memory cell; and a first circuit configured to perform first read for the memory cell and generate a first voltage, write first data to the memory cell that has undergone the first read, perform second read for the memory cell to which the first data is written and generate a second voltage, and determine data stored in the memory cell at the time of the first read based on the first voltage and the second voltage, wherein when writing the first data, the first circuit electrically sets a generation unit configured to generate the second voltage in a floating state.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: October 1, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kosuke Hatsuda, Yorinobu Fujino
  • Patent number: 10431278
    Abstract: Dynamically controlling voltage for access operations to magneto-resistive random access memory (MRAM) bit cells to account for ambient temperature is disclosed. An MRAM bit cell process variation measurement circuit (PVMC) is configured to measure process variations and ambient temperature in magnetic tunnel junctions (MTJs) that affect MTJ resistance, which can change the write current at a given fixed supply voltage applied to an MRAM bit cell. These measured process variations and ambient temperature are used to dynamically control a supply voltage for access operations to the MRAM to reduce the likelihood of bit errors and reduce power consumption. The MRAM bit cell PVMC may also be configured to measure process variations and/or ambient temperatures in logic circuits that represent the process variations and ambient temperatures in access transistors employed in MRAM bit cells in the MRAM to determine variations in the switching speed (i.e., drive strength) of the access transistors.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: October 1, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Xia Li, Wah Nam Hsu, Wei-Chuan Chen, Seung Hyuk Kang
  • Patent number: 10410704
    Abstract: According to one embodiment, a memory includes a first MTJ element having a first area along a first plane; and second MTJ elements each having a second area along the first plane. The second area is larger than or equal to twice the first area and smaller than or equal to five times the first area. Each of the second MTJ elements includes a first ferromagnet, a second ferromagnet, and a first nonmagnet. Respective magnetizations of respective first ferromagnets of the second MTJ elements are oriented along a first direction. Respective magnetizations of respective second ferromagnets of the second MTJ elements are oriented along a second direction. One of the second MTJ elements is coupled to another one of the second MTJ elements in series or in parallel.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: September 10, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Keiji Hosotani, Tatsuya Kishi, Akira Katayama
  • Patent number: 10410707
    Abstract: According to one embodiment, a nonvolatile memory includes a conductive line including a first portion, a second portion and a third portion therebetween, a storage element including a first magnetic layer, a second magnetic layer and a nonmagnetic layer therebetween, and the first magnetic layer being connected to the third portion, and a circuit flowing a write current between the first and second portions, applying a first potential to the second magnetic layer, and blocking the write current flowing between the first and second portions after changing the second magnetic layer from the first potential to a second potential.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: September 10, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tomoaki Inokuchi, Naoharu Shimomura, Katsuhiko Koui, Yuuzo Kamiguchi, Satoshi Shirotori, Kazutaka Ikegami, Hiroaki Yoda
  • Patent number: 10403343
    Abstract: A memory cell apparatus is provided. The apparatus comprises two or more magnetic tunnel junctions (MTJs), including a first MTJ having a first magnetic characteristic and a first electrical characteristic and a second MTJ having a second magnetic characteristic and a second electrical characteristic. The first magnetic characteristic is distinct from the second magnetic characteristic. The apparatus further comprises a transistor having three terminals, where the first MTJ is coupled to a first terminal of the three terminals and a metallic separator coupling the first MTJ with the second MTJ. The first MTJ and the second MTJ are arranged in series.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: September 3, 2019
    Assignee: SPIN MEMORY, INC.
    Inventors: Kadriye Deniz Bozdag, Marcin Gajek, Mourad El Baraji, Eric Michael Ryan
  • Patent number: 10403811
    Abstract: A material layer stack for a magnetic tunneling junction, the material layer stack including a fixed magnetic layer; a dielectric layer; a free magnetic layer; and an amorphous electrically-conductive seed layer, wherein the fixed magnetic layer is disposed between the dielectric layer and the seed layer. A non-volatile memory device including a material stack including an amorphous electrically-conductive seed layer; and a fixed magnetic layer juxtaposed and in contact with the seed layer. A method including forming an amorphous seed layer on a first electrode of a memory device; forming a material layer stack on the amorphous seed layer, the material stack including a dielectric layer disposed between a fixed magnetic layer and a free magnetic layer, wherein the fixed magnetic layer.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: September 3, 2019
    Assignee: Intel Corporation
    Inventors: Kevin P. O'Brien, Kaan Oguz, Brian S. Doyle, Mark L. Doczy, Charles C. Kuo, Robert S. Chau
  • Patent number: 10403345
    Abstract: An electronic device including a semiconductor memory. The semiconductor memory includes a bit line; a source line; a plurality of resistive memory cells among which a selected memory cell forms a current path between the bit line and the source line; a read current supply unit configured to supply read current to the bit line in a read operation; a sense amplifier configured to generate read data in response to a voltage level of the bit line in the read operation; and a variable switch element configured to flow current from the source line to a ground terminal in the read operation, and be decreased in its resistance value as a voltage level of the source line is high.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: September 3, 2019
    Assignee: SK hynix Inc.
    Inventors: Jae-Yun Yi, Sung-Woong Chung, Seok-Pyo Song
  • Patent number: 10403766
    Abstract: Disclosed is a method of manufacturing flash memory with a vertical cell stack structure. The method includes forming source lines in a cell area of a substrate having an ion-implanted well and forming an alignment mark relative to the source lines. The alignment mark is formed in the substrate outside the cell area of the substrate. After formation of the source lines, cell stacking layers are formed. After forming the cell stacking layers, cell pillars in the cell stacking layers are formed at locations relative to the previously formed source lines using the alignment mark to correctly locate the cell pillars.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: September 3, 2019
    Assignee: Conversant Intellectual Property Management Inc.
    Inventor: Hyoung Seub Rhie
  • Patent number: 10403425
    Abstract: Disclosed herein are layered Heusler alloys. The layered Heusler alloys can comprise a first layer comprising a first Heusler alloy with a face-centered cubic (fcc) crystal structure and a second layer comprising a second Heusler alloy with a fcc crystal structure, the second Heusler alloy being different than the first Heusler alloy, wherein the first layer and the second layer are layered along a layering direction, the layering direction being the [110] or [111] direction of the fcc crystal structure, thereby forming the layered Heusler alloy.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: September 3, 2019
    Assignee: The Board of Trustees of the University of Alabama
    Inventors: William H. Butler, Kamaram Munira, Javad Ghasemi Azadani
  • Patent number: 10395712
    Abstract: A memory device comprising an array of memory cells wherein each memory cell includes a respective magnetic random access memory (MRAM) element, and a respective gating transistor. A plurality of bit lines are routed parallel to each other, wherein each bit line is associated with a respective memory cell of the array of memory cells. A common word line is coupled to gates of gating transistors of the array of memory cells. A common source line is coupled to sources of the gating transistors, wherein the common source line is routed perpendicular to the plurality of bit lines within the array of memory cells. A sacrificial circuit element is coupled to a sacrificial bit line, coupled to the common word line and coupled to the common source line, wherein the sacrificial circuit element is operable to provide a desired voltage to the common source line wherein the desired voltage originates from the sacrificial bit line.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: August 27, 2019
    Assignee: SPIN MEMORY, INC.
    Inventors: Neal Berger, Mourad El Baraji, Lester Crudele, Benjamin Louie
  • Patent number: 10394727
    Abstract: A semiconductor storage device includes at least two nonvolatile semiconductor memories, a buffer in which data received from a host and to be written to the nonvolatile semiconductor memories in response to a write command received from the host can be temporarily stored, and a controller connected to the nonvolatile semiconductor memories and configured to transfer data stored in the buffer to a number N of the nonvolatile semiconductor memories in parallel. The number N is set according to a reception of data from the host, and N is greater than or equal to 1 and less than or equal to m, which is the number of nonvolatile semiconductor memories connected to the controller.
    Type: Grant
    Filed: September 4, 2017
    Date of Patent: August 27, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Kazuhito Okita
  • Patent number: 10395733
    Abstract: An integrated circuit and its manufacturing method are disclosed. The integrated circuit includes a forming voltage pad, a memory array including a plurality of memory cells, and a plurality of access lines connected to the memory cells. A forming voltage rail is coupled to the forming voltage pad. A diode is disposed in current flow communication with the forming voltage rail and an access line in the plurality of access lines. The diode is configured to be forward biased during application of a forming voltage to the forming voltage pad to induce a forming current in memory cells in the plurality of memory cells, and to be reverse biased during application of a reference voltage to the forming voltage pad during utilization of the memory array for memory operations.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: August 27, 2019
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Shang-Chi Yang, Chun-Hsiung Hung
  • Patent number: 10395711
    Abstract: A memory device comprising an array of memory cells wherein each memory cell comprises a respective magnetic random access memory (MRAM) element, a respective gating transistor, and a common wordline coupled to gates of gating transistors of said array of memory cells. The memory device further comprises a common source line coupled to sources of said gating transistors, wherein said common source line is routed perpendicular to said plurality of bit lines within said array of memory cells, and a plurality of bit lines which are routed parallel to each other and connected to the drains of said gating transistors, wherein each bit line is associated with a respective memory cell of said array of memory cells.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: August 27, 2019
    Assignee: SPIN MEMORY, INC.
    Inventors: Neal Berger, Benjamin Louie, Mourad El Baraji, Lester Crudele
  • Patent number: 10395699
    Abstract: In some examples, a memory device may have at least a first and a second memory array. In some cases, a portion of the bit cells of the first memory array may be coupled to first PMOS-follower circuitry and to second PMOS-follower circuitry. A portion of the bit cells of the second memory array may also be coupled to the second PMOS-follower circuitry and to third PMOS-follower circuitry. Additionally, in some cases, the portions of bit cells of both the first memory array and the second memory array may be coupled to shared preamplifier circuitry.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: August 27, 2019
    Assignee: Everspin Technologies, Inc.
    Inventors: Syed M. Alam, Thomas Andre
  • Patent number: 10388344
    Abstract: A magnetic memory includes one or more magnetic tunnel junctions, a heavy metal or anti-ferromagnetic strip film, a first bottom electrode and a second bottom electrode. Every magnetic tunnel junction is located on the strip film and represents a memory cell; the first bottom electrode and the second bottom electrode are respectively connected with two ends of the heavy metal or anti-ferromagnetic strip film; every magnetic tunnel junction includes a first ferromagnetic metal, a first oxide, a second ferromagnetic metal, a first synthetic antiferromagnetic layer and an Xth top electrode from bottom to top in sequence, wherein X is a serial number of the memory cell. A data writing method combines spin orbit torque with spin transfer torque to write data, and respectively applies two currents to the magnetic tunnel junction and the heavy metal or anti-ferromagnetic strip film. Only one current is unable to complete data writing.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: August 20, 2019
    Assignee: BEIHANG UNIVERSITY
    Inventors: Weisheng Zhao, Zhaohao Wang, Mengxing Wang, Wenlong Cai
  • Patent number: 10388371
    Abstract: Embodiments provide a selector device for selecting a memory cell. The selector device includes a first electrode; a second electrode; and a switching layer sandwiched between the first electrode and the second electrode. The switching layer includes at least one metal rich layer and at least one chalcogenide rich layer. The metal rich layer includes at least one of a metal or a metal compound, wherein metal content of the metal rich layer is greater than 50 at. %. The chalcogenide content of the chalcogenide rich layer is greater than 50 at. %.
    Type: Grant
    Filed: January 26, 2016
    Date of Patent: August 20, 2019
    Assignee: Agency for Science, Technology and Research
    Inventors: Hongxin Yang, Minghua Li, Wei He, Yu Jiang, Fei Li
  • Patent number: 10388334
    Abstract: An apparatus can include an array of memory cells coupled to sensing circuitry. The sensing circuitry can include a sense amplifier and a compute component. The sensing circuitry is to receive a scan vector and perform a scan chain operation on the scan vector. The sensing circuitry is controlled to write the resulting scan vector to a second portion of the array of memory cells.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: August 20, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Joshua E. Alzheimer, Debra M. Bell
  • Patent number: 10388349
    Abstract: Methods and memory circuits for altering a magnetic direction of a magnetic memory cell using picosecond electric current pulses are disclosed. One method includes directing a first electric current pulse through the magnetic memory cell that includes a ferrimagnetic material layer to heat the ferrimagnetic material layer to toggle a magnetic direction of the ferrimagnetic material layer from a first magnetic direction to a second magnetic direction.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: August 20, 2019
    Assignee: The Regents of the University of California
    Inventors: Yang Yang, Jon Gorchon, Richard Brian Wilson, Charles Henri Alexandre Lambert, Sayeef Salahuddin, Jeffrey Bokor
  • Patent number: 10388859
    Abstract: In a method of manufacturing an MRAM device, first and second lower electrodes may be formed on first and second regions, respectively, of a substrate. First and second MTJ structures having different switching current densities from each other may be formed on the first and second lower electrodes, respectively. First and second upper electrodes may be formed on the first and second MTJ structures, respectively.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: August 20, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dae-Shik Kim, Jeong-Heon Park, Gwan-Hyeob Koh
  • Patent number: 10388361
    Abstract: Methods, systems, and devices for differential amplifier schemes for sensing memory cells are described. In one example, a memory apparatus may include a differential amplifier having a first input node configured to be coupled with a memory cell and having an output node configured to be coupled with a sense component. In some examples, the memory apparatus may also include a capacitor having a first node coupled with the first input node, and a first switching component configured to selectively couple a second node of the capacitor with the output node. The differential amplifier may configured such that a current at the output node is proportional to a difference between a voltage at the first input node of the differential amplifier and a voltage at the second input node of the differential amplifier.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: August 20, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Daniele Vimercati, Stefan Frederik Schippers, Xinwei Guo
  • Patent number: 10388345
    Abstract: According to one embodiment, a memory device includes a preamplifier configured to execute a first read in which a first current relating to a memory cell is passed through a first path and a second current relating to the first current is passed through a second path, to generate a first voltage, to write first data to the memory cell; and to execute a second read in which a third current relating to the memory cell with the first data written thereto is passed through the first path and a fourth current relating to the third current is passed through the second path, to generate a second voltage; and a sense amplifier configured to determine data stored in the memory cell during execution of the first read based on the first voltage and the second voltage.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: August 20, 2019
    Assignee: TOSHIBA MEMORY CORORATION
    Inventors: Kosuke Hatsuda, Yoshiaki Osada, Yorinobu Fujino, Jieyun Zhou
  • Patent number: 10381060
    Abstract: A magnetic random access memory (MRAM) array including several bit cells is described. Each of the bit cells may include a perpendicular magnetic tunnel junction (pMTJ) including a reference layer, a barrier layer supporting the reference layer, and a free layer supporting the barrier layer. A spin-hall conductive material layer may support the free layer. A driver may be operable to set a state of at least one of the bit cells using an increased spin-transfer torque (STT) current and a spin-hall effect from the spin-hall conductive material layer. The increased STT current may be driven through the spin-hall conductive material layer and the pMTJ so that a spin current is generated from the reference layer and the spin-hall conductive material layer.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: August 13, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Jimmy Jianan Kan, Chando Park, Peiyuan Wang, Sungryul Kim, Seung Hyuk Kang
  • Patent number: 10381102
    Abstract: A semiconductor device is provided with normal memory cells constituted so as to store user data, reference memory cells constituted so as to generate a reference signal for reading out the normal memory cells, and a control circuit that carries out a defect detecting operation for detecting whether or not the reference memory cell and data stored in the reference memory cell are coincident with expected values on the stored data read out from the reference memory cells. Moreover, it is also provided with a control circuit for executing a defect correcting operation for correcting data to be stored in the reference memory cells that are detected as defective. Furthermore, it is also provided with a control circuit that is configured so as to cut off the reference memory cell detected as defective from the sense amplifier.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: August 13, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Kazuhiko Kajigaya
  • Patent number: 10381548
    Abstract: Apparatuses, systems, and methods are disclosed for magnetoresistive random access memory. A magnetic tunnel junction for storing data may include a reference layer, a barrier layer, and a free layer. A barrier layer may be disposed between a reference layer and a free layer. A free layer may include a nucleation region and an arm. A nucleation region may be configured to form a magnetic domain wall. An arm may be narrower than a nucleation region and may extend from the nucleation region. An arm may include a plurality of pinning sites formed at predetermined locations along the arm for pinning a domain wall.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: August 13, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Young-Suk Choi, Won Ho Choi
  • Patent number: 10381549
    Abstract: A memory device includes a first element and a second element. The first element includes: first and second ferromagnets; a first nonmagnet; a first conductor; a third ferromagnet; a second conductor, and a fourth ferromagnet. The fourth ferromagnet contains a metallic element and one or more ferromagnetic elements. The second element includes: fifth and sixth ferromagnet; a second nonmagnet; a third conductor; a seventh ferromagnet; a fourth conductor; and a fifth conductor. The fifth conductor contains the metallic element and the one or more ferromagnetic elements of a quantity of 30% or less of a volume of the fifth conductor.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: August 13, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yuichi Ito
  • Patent number: 10381406
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided herein. The integrated circuit includes a plurality of MRAM structures. The integrated circuit further includes a first lower MTJ stack with the first lower MTJ stack including a first lower free layer. The integrated circuit further includes a spin orbit torque coupling layer overlying the first lower MTJ stack. The integrated circuit further includes a first upper MTJ stack overlying the spin orbit torque coupling layer and the first lower MTJ stack with the first upper MTJ stack including a first upper free layer. The switching energy barrier for each of the first lower free layer and the first upper free layer is reduced in the presence of an electrical voltage passing through each of the MTJ stacks. The first lower free layer and said first upper free layer are configured to have magnetizations independent of each other.
    Type: Grant
    Filed: February 17, 2018
    Date of Patent: August 13, 2019
    Assignee: Globalfoundries, Inc.
    Inventors: Ajey Poovannummoottil Jacob, Jaiswal Akhilesh
  • Patent number: 10381552
    Abstract: The present disclosure generally relates to a SOT-MRAM cell that has a spin Hall effect layer and a magnetic tunnel junction. The magnetic tunnel junction is disposed at an edge of the spin Hall effect layer. In order to write the cell, current is applied through the spin Hall effect layer to create spin accumulation of z-polarized spins under the free layer due to the spin Hall effect. The spins exert a spin torque on the free layer via spin diffusion. Based upon the design, the SOT-MRAM cell has deterministic switching of the perpendicular free layer with the spin Hall effect layer without application of an external magnetic field.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: August 13, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Goran Mihajlovic, Neil Smith
  • Patent number: 10381553
    Abstract: A magnetoresistive random-access memory (MRAM) device is disclosed. The device described herein has a thermal stability enhancement layer over the free layer of a magnetic tunnel junction. The thermal stability enhancement layer improves the thermal stability of the free layer, increases the magnetic moment of the free layer, while also not causing the magnetic direction of the free layer to become in plan. The thermal stability enhancement layer can be include a layer of CoFeB ferromagnetic material.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: August 13, 2019
    Assignee: Spin Transfer Technologies, Inc.
    Inventors: Mustafa Pinarbasi, Bartek Kardasz
  • Patent number: 10381551
    Abstract: A Magnetoresistive Random Access Memory (MRAM) assembly includes a first ferromagnetic shielding component, a second ferromagnetic shielding component, a plurality of MRAM cells located between the first and second ferromagnetic shielding components, a plurality of bit lines located between the first and second ferromagnetic shielding components, each bit line coupled to at least one of the plurality of MRAM cells, a plurality of word lines located between the first and second ferromagnetic shielding components, each word line coupled to at least one of the plurality of MRAM cells, a ferromagnetic yoke electrically connecting the first and second ferromagnetic shielding components, and located in an area of the assembly substantially free of the MRAM cells, bit lines, and word lines, and an insulator surrounding the magnetic yoke.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: August 13, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Jeffrey Lille
  • Patent number: 10375698
    Abstract: A memory system is provided. The memory system includes a memory area configured to include a plurality of memory cells; a driving area configured to drive the memory cells; and a control area configured to supply a standby current to the memory area before the memory area records data; a plurality of word lines is crossing to a plurality of bit lines via the plurality of memory cells; and wherein each of the memory cells includes a memory layer, a magnetic fixed layer, an intermediate layer including a non-magnetic material provided between the memory layer and the magnetic fixed layer, a top electrode provided over the memory layer, a bottom electrode provided over the magnetic fixed layer.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: August 6, 2019
    Assignee: Sony Corporation
    Inventors: Yutaka Higo, Masanori Hosomi, Hiroyuki Ohmori, Kazuhiro Bessho, Tetsuya Asayama, Kazutaka Yamane, Hiroyuki Uchida
  • Patent number: 10374006
    Abstract: The present invention provides a magnetic random access memory (MRAM) structure, the MRAM structure includes a transistor including a gate, a source and a drain, and a magnetic tunnel junction (MTJ) device, the MTJ device includes at least one free layer, an insulating layer and a fixed layer, the insulating layer is disposed between the free layer and the fixed layer, and the free layer is located above the insulating layer. The free layer of the MTJ device is electrically connected to a bit line (BL). The fixed layer of the MTJ device is electrically connected to the source of the transistor, and the drain of the transistor is electrically connected to a sense line (SL). And a first conductive via, directly contacting the MTJ device, the material of the first conductive via comprises tungsten.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: August 6, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chung-Liang Chu, Yu-Ping Wang, Yu-Ruei Chen
  • Patent number: 10374151
    Abstract: Provided is a spin current magnetoresistance effect element, including: a magnetoresistance effect element including a first ferromagnetic metal layer, a second ferromagnetic metal layer configured for magnetization direction to be changed, and a non-magnetic layer sandwiched between the first ferromagnetic metal layer and the second ferromagnetic metal layer; and a spin-orbit torque wiring extending in a first direction which intersects a lamination direction of the magnetoresistance effect element and joined to the second ferromagnetic metal layer, wherein, a third end portion of the non-magnetic layer is located between a first end portion of the first ferromagnetic metal layer and a second end portion of the second ferromagnetic metal layer as viewed from the lamination direction on one of side surfaces of the magnetoresistance effect element.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: August 6, 2019
    Assignee: TDK CORPORATION
    Inventors: Eiji Komura, Yohei Shiokawa
  • Patent number: 10374146
    Abstract: There is disclosed a memory element including a memory layer that has a magnetization perpendicular to a film face; a magnetization-fixed layer that has a magnetization that is perpendicular to the film face; and an insulating layer that is provided between the memory layer and the magnetization-fixed layer, wherein an electron that is spin-polarized is injected in a lamination direction of a layered structure, and thereby the magnetization direction of the memory layer varies and a recording of information is performed, a magnitude of an effective diamagnetic field which the memory layer receives is smaller than a saturated magnetization amount of the memory layer, and in regard to the insulating layer and the other side layer with which the memory layer comes into contact at a side opposite to the insulating layer, at least an interface that comes into contact with the memory layer is formed of an oxide film.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: August 6, 2019
    Assignee: Sony Corporation
    Inventors: Yutaka Higo, Masanori Hosomi, Hiroyuki Ohmori, Kazuhiro Bessho, Kazutaka Yamane, Hiroyuki Uchida
  • Patent number: 10366748
    Abstract: Apparatuses and methods for sensing a resistance variable memory cell include circuitry to apply a programming signal to a memory cell in the array, the programming signal associated with programming resistance variable memory cells to a particular data state, and detect a change in resistance of the memory cell to determine if a data state of the memory cell changes from an initial data state to a different data state during application of the programming signal.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: July 30, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Ferdinando Bedeschi
  • Patent number: 10366745
    Abstract: Provided are a semiconductor device and an information processing device that can be manufactured easily at low cost and can calculate an arbitrary interaction model such as an Ising model. A semiconductor device that performs a non-linear operation includes a memory, a reading unit that reads data from the memory, a majority circuit that inputs a result of a predetermined operation on the data read by the reading unit, and a write circuit that receives an output of the majority circuit, a value of a predetermined signal is stochastically inverted at a preceding stage of the majority circuit.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: July 30, 2019
    Assignee: HITACHI, LTD.
    Inventors: Takuya Okuyama, Masanao Yamaoka
  • Patent number: 10365894
    Abstract: Described is an apparatus which comprises: a magnetic tunneling junction (MTJ) device with out-of-plane magnetizations for its free and fixed magnetic layers, and configured to have a magnetization offset away from a center and closer to a switching threshold of the MTJ device; and logic for generating random numbers according to a resistive state of the MTJ device.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: July 30, 2019
    Assignee: Intel Corporation
    Inventors: Charles C. Kuo, Justin S. Brockman, Juan G. Alzate Vinasco, Kaan Oguz, Kevin P. O'Brien, Brian S. Doyle, Mark L. Doczy, Satyarth Suri, Robert S. Chau, Prashant Majhi, Ravi Pillarisetty, Elijah V. Karpov
  • Patent number: 10360961
    Abstract: Methods and structures useful for magnetoresistive random-access memory (MRAM) are disclosed. The MRAM device has a magnetic tunnel junction stack having a significantly improved performance of the free layer in the magnetic tunnel junction structure. The MRAM device utilizes an in-plane polarization magnetic layer and a perpendicular MTJ in conjugation with a alternating current precharge and a programming current pulse that comprises an alternating perturbation frequency and a direct current.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: July 23, 2019
    Assignee: Spin Memory, Inc.
    Inventors: Michail Tzoufras, Marcin Jan Gajek, Kadriye Deniz Bozdag, Mourad El Baraji
  • Patent number: 10360976
    Abstract: A memory device includes a sense amplifier including a first input node and a second input node and configured to output a signal based on a difference between input values at the first input node and the second input node; a first path including a memory cell to be selectively connected to the first input node and provided between the first input node and a ground node; and a second path including a reference cell to be selectively connected to the second input node and provided between the second input node and the ground node.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: July 23, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Akira Katayama
  • Patent number: 10355207
    Abstract: A method for forming a non-volatile memory cell intended to switch the memory cell from an unformed state to a formed state, the memory cell including an ordered stack of a lower electrode, a layer of insulating material and an upper electrode. The forming method includes a breakdown operation in which at least one laser shot is emitted towards the layer of insulating material to make the layer of insulating material active by making it pass from a high resistance state to a low resistance state, the memory cell being formed when the layer of insulating material is active.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: July 16, 2019
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, UNIVERSITE D'AIX-MARSEILLE, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE (CNRS)
    Inventors: Alexis Krakovinsky, Marc Bocquet, Jean Coignus, Vincenzo Della Marca, Jean-Michel Portal, Romain Wacquez
  • Patent number: RE47583
    Abstract: A ferromagnetic thin-film based digital memory having a plurality of bit structures interconnected with manipulation circuitry having a plurality of transistors so that each bit structure has transistors electrically coupled thereto that selectively substantially prevents current in at least one direction along a current path through that bit structure and permits selecting a direction of current flow through the bit structure if current is permitted to be established therein. A bit structure has a nonmagnetic intermediate layer with two major surfaces on opposite sides thereof and a memory film of an anisotropic ferromagnetic material on each of the intermediate layer major surfaces with an electrically insulative intermediate layer is provided on the memory film on which a magnetization reference layer is provided having a fixed magnetization direction.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: August 27, 2019
    Assignee: NVE Corporation
    Inventors: James M. Daughton, Arthur V. Pohm, Brenda A. Everitt