Magnetoresistive Patents (Class 365/158)
  • Patent number: 11152067
    Abstract: Ternary content addressable memory (TCAM) circuits are provided herein. In one example implementation, a TCAM circuit can include a first spin-orbit torque (SOT) magnetic tunnel junction (MTJ) element having a pinned layer coupled to a first read transistor controlled by a first search line, and having a spin hall effect (SHE) layer coupled in a first configuration across complemented write inputs. The TCAM circuit can include a second SOT MTJ element having a pinned layer coupled to a second read transistor controlled by a second search line, and having a SHE layer coupled in a second configuration across the complemented write inputs. The TCAM circuit can include a bias transistor configured to provide a bias voltage to drain terminals of the first read transistor and the second read transistor, and a voltage keeper element that couples the drain terminals to a match indicator line.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: October 19, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Won Ho Choi, Jongyeon Kim
  • Patent number: 11145348
    Abstract: The disclosure provides a circuit structure and method for memory storage using a memory cell and magnetic random access memory (MRAM) stack. A circuit structure includes a memory cell having a first latch configured to store a digital bit, a first diode coupled to the first latch, and a first magnetic random access memory (MRAM) stack coupled to the first latch of the memory cell through the first diode. The first MRAM stack includes a first layer and a second layer each having a respective magnetic moment. The magnetic moment of the second layer is adjustable between a parallel orientation and an antiparallel orientation with respect to the magnetic moment of the first layer. Further, the magnetic anisotropy of the second layer can be modified through application of an applied voltage (VCMA effect). A spin Hall electrode is directly coupled to the first MRAM stack.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: October 12, 2021
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Akhilesh R. Jaiswal, Ajey Poovannummoottil Jacob, Steven R. Soss
  • Patent number: 11145346
    Abstract: According to one embodiment, a device includes a first cell between first and second interconnects; a second cell between second and third interconnects; a third cell between fourth and fifth interconnects; a fourth cell between fifth and sixth interconnects; a equalization circuit connected to the first to sixth interconnects; and a control circuit controlling operation on the first to fourth cells. During the operation, the control circuit applies a first voltage to the first interconnect, applies a second voltage higher than the first voltage to the second interconnect, applies a third voltage to the fifth interconnect, and applies a fourth voltage higher than the third voltage to the sixth interconnect. After the operation, the equalization circuit connects the first interconnect to the sixth interconnect.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: October 12, 2021
    Assignee: KIOXIA CORPORATION
    Inventor: Yorinobu Fujino
  • Patent number: 11145361
    Abstract: A bistable device allows supercurrent to flow when functioning in one regime, wherein magnetization directions of different magnetic layers are antiparallel, but restricts supercurrent when switched to function in a resistive regime, wherein the magnetization directions are parallel. In the first regime, the device acts as a Josephson junction, which allows it to be used in superconducting quantum interference devices (SQUIDs) and other circuits in which quantization of magnetic flux in a superconducting loop is desired. In the second, resistive regime, flux quantization is effectively eliminated in loops containing the device, and current is diverted to parallel superconducting components. The bistable device thereby acts as a superconducting switch, useful for a variety of circuit applications, including to steer current for memory or logic circuits, adjust logical circuit functionality at runtime, or to burn off stray flux during cooldown.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: October 12, 2021
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Eric C. Gingrich, Randall M. Burnett, Donald L. Miller
  • Patent number: 11145347
    Abstract: A memory device and a memory circuit is provided. The memory device includes a magnetic tunnel junction (MTJ), a read word line, a read selector, a write word line and a write selector. The read word line is connected to the MTJ with the read selector in between. The read word line is electrically connected to the MTJ when the read selector is turned on, and electrically disconnected from the MTJ when the read selector is in an off state. The write word line is connected to the MTJ with the write selector in between. The write word line is electrically connected to the MTJ when the write selector is turned on, and electrically disconnected from the MTJ when the write selector is off. A turn-on voltage of the write selector is greater than a turn-on voltage of the read selector.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: October 12, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Li Chiang, Tzu-Chiang Chen, Katherine H. Chiang, Ming-Yuan Song
  • Patent number: 11145676
    Abstract: A memory device includes a plurality of word lines, a plurality of bit lines, a plurality of source lines and a plurality of multi-level memory cells is introduced. Each of the multi-level memory cells is coupled to one of the word lines, one of the bit lines and one of the source lines. Each of the multi-level memory cells includes a ferroelectric storage element and a magneto-resistive storage element cascaded to the ferroelectric storage element. The ferroelectric storage element is configured to store a first bit of a multi-bit data. The magneto-resistive storage element is configured to store a second bit of the multi-bit data.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: October 12, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Li Chiang, Chao-Ching Cheng, Chih-Sheng Chang, Tzu-Chiang Chen, Jin Cai
  • Patent number: 11139340
    Abstract: A magnetic recording array includes: a plurality of spin elements each including a wiring and a laminated body having a first ferromagnetic layer laminated on the wiring and arranged in a matrix; a plurality of write wirings connected to first ends of the spin elements' wiring; a plurality of read wirings connected to the laminated bodies of the spin elements; a plurality of common wirings connected to second ends of the wirings of the spin elements belonging to the same column; and a control unit configured to control a write current flowing between first and second ends of each spin element, wherein when data writing is performed continuously, the unit is configured to prohibit writing to at least a spin element connected to the same common wiring as a first spin element and adjacent to the first spin element after the first element to which the current is applied.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: October 5, 2021
    Assignee: TDK CORPORATION
    Inventors: Yohei Shiokawa, Atsushi Tsumita
  • Patent number: 11133046
    Abstract: A data write device for a resistive memory element, the resistive memory element including: a conductive electrode provided at one end of the memory element; and a reading electrode provided at the other end of the memory element being configured to vary a resistance of the memory element by applying a write current to the conductive electrode, the data write device for the resistive memory element further includes: a writing means, an output means, and a control means. The output means is provided between a power supply and the reading electrode. As output signals, a read signal from the memory element and a monitor signal to monitor a writing status of the memory element written by the writing means are output from the output means. By the monitor signal, a termination of data-writing into the resistive memory element is detected.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: September 28, 2021
    Assignee: TOHOKU UNIVERSITY
    Inventors: Takahiro Hanyu, Daisuke Suzuki, Hideo Ohno, Tetsuo Endoh
  • Patent number: 11133045
    Abstract: A bit cell is described. In some embodiments, the bit cell comprises (1) a magnetic tunnel junction (MTJ), and (2) an access transistor circuit coupled to the MTJ, wherein the access transistor circuit comprises a negative-capacitance field-effect-transistor.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: September 28, 2021
    Assignee: Synopsys, Inc.
    Inventors: Jamil Kawa, Victor Moroz
  • Patent number: 11133456
    Abstract: According to one embodiment, a magnetic storage device includes: a magnetoresistive effect element including a non-magnet, and a stacked structure on the non-magnet, the stacked structure including: a first ferromagnet on the non-magnet; an anti-ferromagnet being exchange-coupled with the first ferromagnet; and a second ferromagnet between the first ferromagnet and the anti-ferromagnet. The stacked structure is configured to: have a first resistance value in response to a first current flowing through the stacked structure in a first direction, and have a second resistance value different from the first resistance value in response to a second current flowing through the stacked structure in a second direction opposite to the first direction.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: September 28, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takeshi Iwasaki, Akiyuki Murayama, Tadashi Kai, Tadaomi Daibou, Masaki Endo, Shumpei Omine, Taichi Igarashi, Junichi Ito
  • Patent number: 11127447
    Abstract: The disclosure provides a voltage-controlled magnetic anisotropic magnetic random access memory. The memory comprises a virtual array, a memory array and a peripheral circuit, wherein the memory array comprises memory cells with X rows and Y columns; the virtual array comprises virtual cells with X rows and one column; the peripheral circuit comprises at least one data sampling-decision-output circuit, the data sampling-decision-output circuit comprises a sensitive amplifier circuit and a logic circuit in series, and are simultaneously connected to the data sampling-decision-output circuit in the peripheral circuit at the same time. By changing the width-length ratio of a differential circuit in the sensitive amplifier circuit and adding the virtual array, the problem that the storage state of the voltage-controlled magnetic anisotropy magnetic random access memory cannot be determined is effectively solved, and the risk of resistance deviation under different process conditions also can be avoided.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: September 21, 2021
    Assignee: SHANGHAI IC R&D CENTER CO., LTD
    Inventors: Ling Shen, Yu Jiang, Huijie Yan, Jianxin Wen
  • Patent number: 11127641
    Abstract: This spin current magnetization rotational element includes a first ferromagnetic metal layer for a magnetization direction to be changed, and a spin-orbit torque wiring extending in a second direction intersecting a first direction which is an orthogonal direction to a surface of the first ferromagnetic metal layer and configured to be joined to the first ferromagnetic metal layer, wherein the spin-orbit torque wiring has a structure in which a spin conduction layer joined to the first ferromagnetic metal layer and a spin generation layer joined to the spin conduction layer on a surface on a side opposite to the first ferromagnetic metal layer are laminated.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: September 21, 2021
    Assignee: TDK CORPORATION
    Inventors: Yohei Shiokawa, Tomoyuki Sasaki, Tomomi Kawano, Minoru Sanuki
  • Patent number: 11127900
    Abstract: Variable resistance memory devices are provided. A variable resistance memory device includes conductive lines and a memory cell including a variable resistance element on one of the conductive lines. The variable resistance memory device includes a first insulating region between the conductive lines. Moreover, the variable resistance memory device includes a second insulating region on the first insulating region between the conductive lines. Methods of forming variable resistance memory devices are also provided.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: September 21, 2021
    Inventors: Shin-Jae Kang, Gyuhwan Oh, Jiyoon Chung, Junyeon Hwang
  • Patent number: 11120858
    Abstract: A magnetic memory according to an embodiment includes: a first wiring; a second wiring; a first switching element disposed between the first wiring and the second wiring; a first magnetic member extending in a first direction and disposed between the first switching element and the second wiring; a third wiring disposed between the first magnetic member and the second wiring; a first magnetoresistive element disposed between the third wiring and the second wiring; and a second switching element disposed between the first magnetoresistive element and the second wiring.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: September 14, 2021
    Assignee: Kioxia Corporation
    Inventors: Yoshihiro Ueda, Michael Arnaud Quinsat
  • Patent number: 11120857
    Abstract: Disclosed is a reference circuit having an even number m of groups of m parallel-connected magnetic tunnel junctions (MTJs). The MTJs in half of the groups are programmed to have parallel resistances (RP) and the MTJs in the other half are programmed to have anti-parallel resistances (RAP). Switches connect the groups in series, creating a series-parallel resistor network. The total resistance (RT) of the network has low variability and is essentially equal to half the sum of a nominal RP plus a nominal RAP and can be employed as a reference resistance (RREF). Under specific biasing conditions the series-parallel resistor network can generate a low variability reference parameter (XREF) that is dependent on this RREF. Also disclosed are an integrated circuit (IC) that includes the reference circuit and a magnetic random access memory (MRAM) structure, which uses XREF to determine stored data values in MRAM cells and associated methods.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: September 14, 2021
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Akhilesh Jaiswal, Bipul C. Paul
  • Patent number: 11114145
    Abstract: Disclosed is a three-dimensional magnetic device based on a spin Hall effect which includes an internal electrode, at least one magnetic junction and at least one external electrode. The internal electrode, the at least one magnetic junction and the at least one external electrode have columnar structures. Each of the at least one magnetic junction comprises a magnetic free layer, a magnetic reference layer and a non-magnetic spacing layer between magnetic free layer and magnetic reference layer. The magnetic free layer is in contact with internal electrode, and the magnetic reference layer in each of the at least one magnetic junction is in contact with a corresponding one of the at least one external electrode. The three-dimensional magnetic device may be stacked in a normal direction of the bottom surface of the internal electrode. Magnetization reversal of three-dimensional magnetic device may be realized by a combination of a spin-orbit torque and a spin transfer torque.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: September 7, 2021
    Assignee: Xi'an Jiaotong University
    Inventors: Tai Min, Runzi Hao, Lei Wang, Xue Zhou
  • Patent number: 11108395
    Abstract: A memory cell of MRAM includes a PMOS transistor and a storage element. A first terminal of the PMOS transistor is connected with a first end of the memory cell. A control terminal of the PMOS transistor is connected with a second end of the memory cell. A first terminal of the storage element is connected with a second terminal of the PMOS transistor. A second terminal of the storage element is connected with a third end of the memory cell. During a write operation, a first voltage is provided to the first end of the memory cell, a second voltage is provided to the third end of the memory cell, and a control voltage is provided to the second end of the memory cell. Consequently, the memory cell is in a first storage state.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: August 31, 2021
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventor: Chia-Fu Chang
  • Patent number: 11101012
    Abstract: A magnetic storage device includes a magnetic body including first and second magnetic regions and a magnetic connection region that connects the first and second magnetic regions, and in which a plurality of magnetic domains each storing information by a magnetization direction thereof is formed, a read element that is electrically connected to the magnetic connection region and by which a magnetization direction of one of the magnetic domains is read, and a write element by which a magnetic domain having a magnetization direction is formed in the magnetic body according to information to be stored. The magnetic domains formed in each of the first and second magnetic regions are shifted in a predetermined direction in response to current that flows through the corresponding one of the first and second magnetic regions.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: August 24, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yoshihiro Ueda, Shinji Miyano
  • Patent number: 11100966
    Abstract: A memory device is provided. The memory device includes: a plurality of subarrays, a row control, a column control, a plurality of sense amplifiers, a plurality of sub word drivers, and a repeater. Each of the subarrays are electrically coupled to each other. The row control is configured to control at least a row of the subarrays. The column control is configured to control at least one column of the subarrays. The sense amplifiers are adapted to each of the subarrays are periodically enabled during a data access operation. The sub word drivers are disposed adjacent to each of the subarrays and provides a driving signal corresponds to the subarrays. The repeater is configured to disposed on the edge of the subarrays.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: August 24, 2021
    Assignee: Winbond Electronics Corp.
    Inventor: San-Ha Park
  • Patent number: 11094361
    Abstract: In some embodiments, the present disclosure relates to an integrated circuit. The integrated circuit has an operative magnetic tunnel junction (MTJ) device configured to store a data state. The operative MTJ device is coupled to a bit-line. A regulating access apparatus is coupled between the operative MTJ device and a first word-line. The regulating access apparatus has one or more regulating MTJ devices that are configured to control a current provided to the operative MTJ device.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: August 17, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Katherine Chiang, Chung Te Lin, Min Cao, Yuh-Jier Mii, Sheng-Chih Lai
  • Patent number: 11094362
    Abstract: Virtual ground sensing circuits, control circuit, electrical systems, computing devices, and related methods are disclosed. A control circuit includes a virtual ground sensing circuit configured to provide a virtual ground to a conductive line. The virtual ground sensing circuit is further configured to selectively operably couple the conductive line to a sense node of a sense circuit, wherein the sense node having a sense node capacitance less than a capacitance of the conductive line. Further, virtual ground sensing circuit is configured to compare a sense node voltage to a reference voltage.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: August 17, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Giulio Giuseppe Marotta, Marco Domenico Tiburzi
  • Patent number: 11094743
    Abstract: According to one embodiment, a magnetic memory device includes a first memory cell which includes a first stacked structure including a magnetic layer, and a second memory cell which is provided on the first memory cell and includes a second stacked structure including a magnetic layer, wherein each of the first stacked structure and the second stacked structure has a structure in which a plurality of layers including a predetermined layer are stacked, and the predetermined layer included in the first stacked structure and the predetermined layer included in the second stacked structure have different thicknesses.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: August 17, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Masayoshi Iwayama, Tatsuya Kishi, Masahiko Nakayama, Toshihiko Nagase, Daisuke Watanabe, Tadashi Kai
  • Patent number: 11093824
    Abstract: The present disclosure provides a neuromorphic device and a method of driving the same. The neuromorphic device of the present disclosure includes a channel, the magnetization direction of which is changed as a plurality of data is integrated, first and second magnetization regulators formed on both ends of the channel and responsible for changing the magnetization direction of the channel according to a plurality of input data, and a controller formed on the channel between the first and second magnetization regulators and responsible for firing data equal to or greater than a critical value integrated in the channel.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: August 17, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jea Gun Park, Du Yeong Lee, Seung Eun Lee
  • Patent number: 11087799
    Abstract: MRAM reference voltage generation is disclosed. In one aspect, a reference circuit for generating a reference level includes first and second non-overlapping paths from a first node to a second node, each path having a precision resistor in series with a set of two or more magnetic MRAM elements electrically connected in parallel. The first set of two or more MRAM elements are in a parallel state and the second set of two or more MRAM elements are in an anti-parallel state, or a first portion of the first and second sets of two or more MRAM elements are in a parallel state and a second portion of the first and second sets of two or more MRAM elements are in an anti-parallel state. A measurement circuit receives a first value indicative of a resistance between the first node and the second node and outputs a reference level based at least in part on the first value.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: August 10, 2021
    Assignee: QUALCOMM Incorporated
    Inventor: Sushil Sudam Sakhare
  • Patent number: 11088201
    Abstract: Some embodiments relate to a memory device. The memory device includes a magnetoresistive random-access memory (MRAM) cell comprising a magnetic tunnel junction (MTJ). The MTJ device comprises a stack of layers, comprising a bottom electrode disposed over a substrate. A seed layer disposed over the bottom electrode. A buffer layer is disposed between the bottom electrode and the seed layer. The buffer layer prevents diffusion of a diffusive species from the bottom electrode to the seed layer.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: August 10, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsann Lin, Chien-Min Lee, Ji-Feng Ying
  • Patent number: 11087814
    Abstract: The present disclosure relates to a structure including a non-fixed read-cell circuit configured to switch from a first state to a second state based on a state of a memory cell to generate a sensing margin.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: August 10, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Amogh Agrawal, Ajey Poovannummoottil Jacob, Bipul C. Paul
  • Patent number: 11086745
    Abstract: A memory system includes a memory device, a first controller, and a second controller. The first controller is configured to output a control signal for the memory device and data to be stored in the memory device based on a signal received from a host. The second controller includes a non-volatile memory configured to store the data. The second controller is configured to receive the control signal and the data from the first controller, and control the memory device based on the control signal.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: August 10, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kui-Yon Mun, Jae-Yong Jeong, Sung-Kyu Park, Beomkyu Shin, Young-Seok Hong
  • Patent number: 11088318
    Abstract: Spin-orbit-torque (SOT) lines are provided near free regions in magnetoresistive devices that include magnetic tunnel junctions. Current flowing through such SOT lines injects spin current into the free regions such that spin torque is applied to the free regions. The spin torque generated from a SOT switching line can be used to switching the free region or to act as an assist to spin-transfer torque generated by current flowing vertically through the magnetic tunnel junction, in order to improve the reliability, endurance, or both of the magnetoresistive device. Further, one or more additional layers or regions may improve the SOT switching efficiency and the thermal stability of magnetoresistive devices including SOT lines.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: August 10, 2021
    Assignee: Everspin Technologies, Inc.
    Inventor: Jijun Sun
  • Patent number: 11087812
    Abstract: A MRAM includes a plurality of memory cells, an operation unit, a voltage generator, and an input/output circuit. The operation unit includes multiple groups of memory cells among the plurality of memory cells. The voltage generator is configured to provide a plurality of control signals by voltage-dividing a voltage control signal and selectively output the plurality of control signals to the input/output circuit. The input/output circuit is configured to output a plurality of switching pulse signals to the multiple groups of memory cells according to the plurality of control signals, wherein each switching pulse signal differs in pulse width or level.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: August 10, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Hui Lee, I-Ming Tseng, Chiu-Jung Chiu, Chung-Liang Chu, Yu-Chun Chen, Ya-Sheng Feng, Yi-An Shih, Hsiu-Hao Hu, Yu-Ping Wang
  • Patent number: 11074972
    Abstract: A semiconductor circuit of the present disclosure includes: a first circuit that is configured to apply an inverted voltage of a voltage at a first node to a second node; a second circuit that is configured to apply an inverted voltage of a voltage at the second node to the first node; a first transistor that is configured to couple the first node to a third node to which a first memory element is coupled; a second transistor having a drain coupled to the third node and a gate coupled to a first predetermined node; a third transistor having a drain coupled to the third node and a gate coupled to a second predetermined node; a fourth transistor that is configured to couple the second node to a fourth node to which a second memory element is coupled; a fifth transistor having a drain coupled to the fourth node and a gate coupled to the second predetermined node; and a sixth transistor having a drain coupled to the fourth node and a gate coupled to the first predetermined node.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: July 27, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Yusuke Shuto
  • Patent number: 11074968
    Abstract: A system and method for storing data that includes at least one memory device having a plurality of memory cells for storing data; and a memory control circuit that manages the read current and read pulse width applied to the memory cells, wherein the at least one memory device has a read current circuit configured to utilize adjustments to at least one of the read current or the read pulse width applied to the memory cells. In response to a request to read a group of the memory cells, the memory control circuit in an example, in response to determining that a comparative temperature value exceeds a first threshold, is configured to perform at least one of reducing the read current and/or increasing the read pulse width to be applied to the group of memory devices to be read.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: July 27, 2021
    Assignee: International Business Machines Corporation
    Inventors: Saravanan Sethuraman, Karthick Rajamani, Venkata K. Tavva, Hillery Hunter, Chitra Subramanian
  • Patent number: 11069390
    Abstract: Spin-orbit torque magnetoresistive random-access memory (SOT-MRAM) cells that undergo perpendicular magnetization switching in the absence of an in-plane magnetic field and methods for their operation are provided. The SOT-MRAM cells use cobalt-iron-boron alloys, cobalt-iron alloys, metallic cobalt, and/or metallic iron as the ferromagnetic free layer in a magnetic tunnel junction. By designing the ferromagnetic layer with appropriate lateral dimensions and operating the SOT-MRAM cells with an appropriate charge current density, deterministic perpendicular magnetization switching is achieved without the need to apply an external in-plane bias collinear with the charge current.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: July 20, 2021
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Jiamian Hu, Minyi Dai
  • Patent number: 11056187
    Abstract: A memory device includes a memory cell array including a plurality of memory cells, each of the plurality of memory cells having a switch element, and a data storage element connected to the switch element and containing a phase-change material; and a memory controller for obtaining first read voltages from the plurality of memory cells, inputting a first write current to the plurality of memory cells, and then, obtaining second read voltages from the plurality of memory cells, wherein the memory controller compares the first read voltage of a first memory cell of the plurality of memory cells to the second read voltage of the first memory cell to determine a state of the first memory cell.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: July 6, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae Hui Na, Mu Hui Park, Kwang Jin Lee, Yong Jun Lee
  • Patent number: 11050015
    Abstract: A storage device includes a first conductor that extends in a first direction, a first stacked body that extends in the first direction, is electrically connected to the first conductor, and includes a first ferromagnetic body that extends in the first direction, a second ferromagnetic body, a first insulator between the first stacked body and the second ferromagnetic body, a first switching element having first and second ends, wherein the first end is electrically connected to the second ferromagnetic body, the first switching element regulating current flow between the first and second ends in response to a voltage applied between the first and second ends, a second conductor that extends in a second direction crossing the first direction and is electrically connected to the second end of the first switching element, a third ferromagnetic body, and a second insulator between the third ferromagnetic body and another stacked body.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: June 29, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yuichi Ito
  • Patent number: 11048434
    Abstract: A memory circuit has compute-in-memory (CIM) circuitry that performs computations based on time-to-digital conversion (TDC). The memory circuit includes an array of memory cells addressable with column address and row address. The memory circuit includes CIM sense circuitry to sense a voltage for multiple memory cells triggered together. The CIM sense circuitry including a TDC circuit to convert a time for discharge of the multiple memory cells to a digital value. A processing circuit determines a value of the multiple memory cells based on the digital value.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: June 29, 2021
    Assignee: Intel Corporation
    Inventors: Raghavan Kumar, Phil Knag, Gregory K. Chen, Huseyin Ekin Sumbul, Sasikanth Manipatruni, Amrita Mathuriya, Abhishek Sharma, Ram Krishnamurthy, Ian A. Young
  • Patent number: 11050273
    Abstract: Apparatuses and methods for removing a defective energy storage cell from an energy storage array is described. An apparatus includes an energy storage array including a plurality of energy storage cells, and a cell removal circuit coupled to the energy storage array. The cell removal circuit is configured to prevent a defective energy storage cell of the plurality of energy storage cells from causing other energy storage cells of the plurality of energy storage cells to become defective. A method includes receiving power at a charging node of an energy storage array, the energy storage array including a plurality of energy storage cells. Responsive to failure of an energy storage cell of the plurality of energy storage cells, current is provided through the defective energy storage cell, and responsive to the defective energy storage cell becoming an open circuit, discontinuing provision of the current through the defective energy storage cell.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: June 29, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Shaun Stickel
  • Patent number: 11043267
    Abstract: Row electrode drivers and column electrode drivers for a memory device are distributed within a footprint share by a memory cell array.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: June 22, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Hernan A. Castro, Everardo Torres Flores, Jeremy M. Hirst
  • Patent number: 11043246
    Abstract: A memory module is provided including a plurality of semiconductor memory devices mounted on a circuit board. A control device is mounted on the circuit board and configured to receive a command signal, an address signal, and a clock signal and to provide the command signal, the address signal, and the clock signal to the plurality of semiconductor memory devices. A first group of the semiconductor memory devices is disposed between the control device and a first edge portion of the circuit board, and a second group of the semiconductor memory devices is disposed between the control device and a second edge portion of the circuit board. The control device is configured to transmit the address signal to the first group of the semiconductor memory devices and the second group of the semiconductor memory devices through a first transmission line and a second transmission line, respectively.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: June 22, 2021
    Assignee: SAMSUNG ELECTRONICS CO, LTD.
    Inventors: Gyuchae Lee, Kyudong Lee
  • Patent number: 11038100
    Abstract: A magnetoresistive element comprises a perpendicular coupling layer between a novel perpendicular AFM layer and ferromagnetic recording layer. The perpendicular coupling layer introduces giant magnetic anisotropy energies (P-MAE) on the recording layer interface and the P-AFM layer interface which further introduce RKKY coupling between the magnetic moment of the recording layer and the P-MAE induced magnetic moment at the P-AFM layer interface, yielding a giant perpendicular magnetic anisotropy of the recording layer.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: June 15, 2021
    Inventor: Yimin Guo
  • Patent number: 11037624
    Abstract: Devices and methods for programming resistive change elements using an electrical stimulus are disclosed. According to some aspects of the present disclosure the devices and methods program at least one resistive change element within at least one resistive change element cell in a resistive change element array using an electrical stimulus having a voltage level greater than a steady state voltage level that can be supplied by a power supply.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: June 15, 2021
    Assignee: Nantero, Inc.
    Inventors: Jia Luo, Sheyang Ning, Lee E. Cleveland
  • Patent number: 11037643
    Abstract: According to one embodiment, a magnetic memory puts a first magnetic domain having a magnetization direction which is the same as or opposite to a magnetic domain of a first layer of a magnetic memory line, into the first layer, based on a value of data and the magnetization direction of the first layer. When receiving a first command, the magnetic memory puts a first additional magnetic domain and a second additional magnetic domain having a magnetization direction opposite to the first additional magnetic domain into the magnetic memory line. When receiving a second command, the magnetic memory read the first and second additional magnetic domains to determine the magnetization direction of the first magnetic domain.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: June 15, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Marie Takada, Masanobu Shirakawa, Yoshihiro Ueda, Naomi Takeda, Hideki Yamada
  • Patent number: 11031058
    Abstract: A spin-transfer torque (STT) magnetoresistive memory device includes a first electrode, a second electrode, and a magnetic tunnel junction located between the first electrode and the second electrode. The magnetic tunnel junpction includes a reference layer having a fixed magnetization direction, a free layer stack, and a nonmagnetic tunnel barrier layer located between the reference layer and the free layer stack. The free layer stack has a total thickness of less than 2 nm, and contains in order, a proximal ferromagnetic layer located proximal to the nonmagnetic tunnel barrier layer, a first non-magnetic metal sub-monolayer, an intermediate ferromagnetic layer, a second non-magnetic metal sub-monolayer, and a distal ferromagnetic layer.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: June 8, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Tiffany Santos, Neil Smith
  • Patent number: 11031541
    Abstract: A spin-orbit torque wiring extending in a first direction and a first ferromagnetic layer laminated on one surface of the spin-orbit torque wiring. In addition, the spin-orbit torque wiring includes a first wiring and a second wiring from the first ferromagnetic layer side. The first wiring and the second wiring are both made of a metal and a temperature dependency of the resistivity of the first wiring in a temperature range of at least ?40° C. to 100° C. is higher than that of the second wiring.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: June 8, 2021
    Assignee: TDK CORPORATION
    Inventor: Tomoyuki Sasaki
  • Patent number: 11031061
    Abstract: A system and method include determining, by a memory controller associated with a memory device, a value of a parameter of a write pulse for a plurality of bits of a B-bit word to be stored in the memory device. The value of the parameter is based upon a relative importance of a bit position of the plurality of bits in the B-bit word to a performance of a machine learning or signal processing task involving the B-bit word, a fidelity metric, and a resource metric. The system and method also include writing each of the plurality of bits of the B-bit word in a different sub-array of the memory device using the write pulse generated based on the value of the parameter determined for a particular one of the plurality of bits.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: June 8, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Yongjune Kim, Yoocharn Jeon, Won Ho Choi, Cyril Guyot, Yuval Cassuto
  • Patent number: 11031062
    Abstract: According to one embodiment, a magnetic memory device includes a stacked body and a controller. The stacked body includes a first conductive layer, a second conductive layer, a first magnetic layer provided between the first conductive layer and the second conductive layer, a second magnetic layer provided between the first magnetic layer and the second conductive layer, and a nonmagnetic layer provided between the first magnetic layer and the second magnetic layer. A resistance value per unit area of the nonmagnetic layer exceeds 20 ??m2. The controller is electrically connected to the first conductive layer and the second conductive layer, and supplies a write pulse to the stacked body in a first operation.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: June 8, 2021
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Yoichi Shiota, Takayuki Nozaki, Shinji Yuasa
  • Patent number: 11018185
    Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes a first magnetic tunneling junction (MTJ) pattern on a substrate, a second MTJ pattern adjacent to the first MTJ pattern, and a third MTJ pattern between the first MTJ pattern and the second MTJ pattern. Preferably, the first MTJ pattern, the second MTJ pattern, and the third MTJ pattern constitute a staggered arrangement.
    Type: Grant
    Filed: January 20, 2020
    Date of Patent: May 25, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Ting Wu, Jian-Jhong Chen, Po-Chun Yang, Jhen-Siang Wu, Yung-Ching Hsieh, Bo-Chang Li, Jen-Yu Wang, Cheng-Tung Huang
  • Patent number: 11017821
    Abstract: A magnetic recording array includes: a plurality of domain wall moving elements; a first wiring which is electrically connected to a reference potential and is electrically connected to at least one domain wall moving element of the plurality of domain wall moving elements; a second wiring which is electrically connected to at least two or more domain wall moving elements of the plurality of domain wall moving elements; a first switching element which is connected between each of the domain wall moving elements and the first wiring; and a second switching element which is connected between each of the domain wall moving elements and the second wiring, wherein an OFF resistance of the first switching element is smaller than an OFF resistance of the second switching element.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: May 25, 2021
    Assignee: TDK CORPORATION
    Inventors: Takuya Ashida, Tatsuo Shibata
  • Patent number: 11018690
    Abstract: A device for generating a random electric signal, including an input duct, an output duct, a generator of magnetic particles generating magnetic particles in the input duct, a diffusion chamber connected to the input duct and the output duct, wherein the diffusion chamber is designed to diffuse the generated magnetic particles, a displacement unit for displacement of the generated magnetic particles towards the diffusion chamber, and a converter that is designed to generate an electrical signal proportional to a characteristic, wherein the characteristic is the particle density in the diffusion chamber or the passage of magnetic particles at a predetermined location of an output duct connected to the diffusion chamber.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: May 25, 2021
    Assignee: THALES
    Inventors: Daniele Pinna, Julie Grollier, Vincent Cros, Damien Querlioz, Pierre Bessiere, Jacques Droulez
  • Patent number: 11011697
    Abstract: A magnetic tunnel junction (MTJ) structure having faceted sidewalls is formed on a conductive landing pad that is present on a surface of an electrically conductive structure embedded in a dielectric material layer. No metal ions are re-sputtered onto the sidewalls of the MTJ structure during the patterning of the MTJ material stack that provides the MTJ structure. The absence of re-sputtered metal on the MTJ structure sidewalls reduces the risk of shorts.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: May 18, 2021
    Assignee: International Business Machines Corporation
    Inventors: Oscar van der Straten, Alexander Reznicek, Praneet Adusumilli
  • Patent number: 11011243
    Abstract: A storage device is provided which shares a host memory with a host. The storage device includes an interface that exchanges data with the host and implements a protocol to use a partial area of the host memory as a buffer of the storage device. A storage controller of the storage device monitors deterioration information of a first area of the buffer and transmits a corruption prediction notification associated with the first area to the host based on a result of the monitoring.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: May 18, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-Ryoul Lee, Hyun Ju Yi, Jaeho Sim, Kicheol Eom, Hyotaek Leem