Magnetoresistive Patents (Class 365/158)
  • Patent number: 12274073
    Abstract: An electronic device may include a first electrode, a first piezoelectric layer electrically coupled to the first electrode, a first magnetostrictive layer above the first piezoelectric layer, a first tunnel barrier layer above the first magnetostrictive layer, and a ferromagnetic layer above the first ferroelectric layer. The electronic device may further include a second electrode electrically coupled to the ferromagnetic layer a second tunnel barrier layer above the ferromagnetic layer, a second magnetostrictive layer above the second tunnel barrier layer, a second piezoelectric layer above the second magnetostrictive layer, and a third electrode electrically coupled to the second piezoelectric layer. The first piezoelectric layer may be strained responsive to voltage applied across the first and second electrodes, and the second piezoelectric layer may be strained responsive to voltage applied across the second and third electrodes.
    Type: Grant
    Filed: January 25, 2022
    Date of Patent: April 8, 2025
    Assignee: EAGLE TECHNOLOGY, LLC
    Inventors: Matt Bauer, Steven R. Snyder
  • Patent number: 12272399
    Abstract: Differential programming of multiple resistive switching memory cells defining a bit is disclosed. The differential programming can mitigate invalid data values for the defined bit, referred to herein as an identifier bit. Embodiments of the present disclosure provide for detection of a program event(s) for a portion of resistive switching memory cells defining an identifier bit, and disconnecting a remainder of the memory cells from program supply voltage, prior to a duration of a program cycle. Additionally, the program cycle can be continued for the programmed memory cell(s) to facilitate a robust programming and enhance data longevity. The detection and subsequent disconnection can facilitate proper differential programming and mitigate unwanted program events that lead to invalid identifier bit results, as well as reducing power consumption for a program cycle of resistive switching memory.
    Type: Grant
    Filed: February 26, 2024
    Date of Patent: April 8, 2025
    Assignee: Crossbar, Inc.
    Inventor: Hagop Nazarian
  • Patent number: 12266408
    Abstract: In some embodiments, the present disclosure relates to an integrated chip (IC) memory structure. The IC memory structure includes a first conductor over a substrate and a second conductor over the first conductor. The first conductor is vertically separated from the second conductor by an isolation structure. A first channel structure is arranged on a sidewall of the isolation structure. The first channel structure is vertically between the first conductor and the second conductor. A vertical gate electrode is disposed along sidewalls of the first conductor, the second conductor, and the first channel structure. The sidewall of the first channel structure faces away from the isolation structure.
    Type: Grant
    Filed: July 24, 2023
    Date of Patent: April 1, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Chih Lai, Chung-Te Lin
  • Patent number: 12254945
    Abstract: A neuromorphic device includes a memory cell array including first resistive memory cells connected to word lines, bit lines and source lines, second resistive memory cells connected to the word lines, at least one redundancy bit line and at least one redundancy source line, third resistive memory cells connected to at least one redundancy word line, the bit lines and the source lines. The memory cell array stores data corresponding to a weight of a neural network in the first resistive memory cells, and is configured to generate a plurality of read currents based on input signals and the data. The neuromorphic device further includes an analog to digital converter (ADC) circuit configured to convert the plurality of read currents into a plurality of digital signals.
    Type: Grant
    Filed: May 31, 2023
    Date of Patent: March 18, 2025
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Youngnam Hwang
  • Patent number: 12256647
    Abstract: An integrated circuit die includes a magnetic tunnel junction as a storage element of a MRAM cell. The integrated circuit die includes a top electrode positioned on the magnetic tunnel junction. The integrated circuit die includes a first sidewall spacer laterally surrounding the top electrode. The first sidewall spacer acts as a mask for patterning the magnetic tunnel junction. The integrated circuit die includes a second sidewalls spacer positioned on a lateral surface of the magnetic tunnel junction.
    Type: Grant
    Filed: May 2, 2023
    Date of Patent: March 18, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jun-Yao Chen, Harry-Hak-Lay Chuang, Hung Cho Wang
  • Patent number: 12249371
    Abstract: A physically unclonable function (PUF) device includes first and second inverters, each of which includes a common gate node and a common drain node. The common drain node of the first inverter is electrically connected to the common gate node of the second inverter. The PUF device also includes a common output node, a first resistive memory device (RMD) electrically connected to the common drain node of the first inverter and the common output node, and a second RMD electrically connected to the common drain node of the second inverter and the common output node.
    Type: Grant
    Filed: January 14, 2022
    Date of Patent: March 11, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yun-Feng Kao, Katherine H. Chiang
  • Patent number: 12236989
    Abstract: The present invention provides a layer structure for a magnetic memory element in which the drive current required for domain wall motion is reduced, and the controllability of domain wall motion is improved, and provides a magnetic memory element having the layer structure. A layer structure (9) for a magnetic memory element (10) comprises multiple first ferromagnetic layers (1) with a switchable spin state and boundary layers (2) each located between each pair of the multiple first ferromagnetic layers (1) to form a domain wall, the boundary layers (2) being for generating ferromagnetic interaction (Aex) between the multiple first ferromagnetic layers (1).
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: February 25, 2025
    Assignee: KYOTO UNIVERSITY
    Inventor: Teruo Ono
  • Patent number: 12237010
    Abstract: Concurrent access of multiple memory cells in a cross-point memory array is disclosed. In one aspect, a forced current approach is used in which, while a select voltage is applied to a selected bit line, an access current is driven separately through each selected word line to concurrently drive the access current separately through each selected memory cell. Hence, multiple memory cells are concurrently accessed. In some aspects, the memory cells are accessed using a self-referenced read (SRR), which improves read margin. Concurrently accessing more than one memory cell in a cross-point memory array improves bandwidth. Moreover, such concurrent accessing allows the memory system to be constructed with fewer, but larger cross-point arrays, which increases array efficiency. Moreover, concurrent access as disclosed herein is compatible with memory cells such as MRAM which require bipolar operation.
    Type: Grant
    Filed: September 7, 2022
    Date of Patent: February 25, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Nathan Franklin, Ward Parkinson, Michael Grobis, James O'Toole
  • Patent number: 12230569
    Abstract: A scheme intelligently balances existing TM0 resources to simultaneously boost both AC and DC power delivery topologies without incurring a penalty on either area or IR drop. TM0 tracks are either regular or staples. Regular tracks are continuous across the width of an active silicon. Staples are located right under the respective TM1 (Top Metal 1) tracks. TM1 is above TM0 in the hierarchy of metal layers. The staples aid in increasing the total TV0 (Top Via 0 that connects TM0 to TM1) density for all supplies simultaneously as they are consecutively track-shared between the TM1 tracks. This boost in via density helps reduce the net series resistance of the MIM capacitor as the Manhattan (displacement) distance between the supply and ground vias is now reduced. The outcome is a high-density high-bandwidth MIM capacitor, located between the main power distribution layers in the die metal stack—TM0 and TM1.
    Type: Grant
    Filed: February 16, 2021
    Date of Patent: February 18, 2025
    Assignee: Intel Corporation
    Inventors: Kushal Sreedhar, Christopher Mozak, Mahmoud Elassal
  • Patent number: 12225705
    Abstract: A memory device having an error detection function and being capable of storing a large amount of data per unit area is provided. A driver circuit of the memory device is formed using a transistor formed on a semiconductor substrate, and a memory cell of the memory device is formed using a thin film transistor. A plurality of layers each of which includes a memory cell using the thin film transistor can be stacked over the semiconductor substrate, so that the amount of data that can be stored per unit area can be increased. Part of a peripheral circuit including the memory device can be formed using a thin film transistor, and thus, an error detection circuit is formed using the thin film transistor and stacked over the semiconductor substrate.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: February 11, 2025
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hitoshi Kunitake, Tatsuya Onuki, Tomoaki Atsumi, Kiyoshi Kato
  • Patent number: 12224325
    Abstract: A method includes forming a dummy gate structure over a substrate; forming a source/drain structure over the substrate; replacing the dummy gate structure with a metal gate structure; forming a protection cap over the metal gate structure; forming a source/drain contact over the source/drain structure; performing a selective deposition process to form a first etch stop layer on the protection cap, in which the selective deposition process has a faster deposition rate on the protection cap than on the source/drain contact; depositing a second etch stop layer over the first etch stop layer the source/drain contact; etching the second etch stop layer to form an opening; and forming a via contact in the opening.
    Type: Grant
    Filed: July 14, 2023
    Date of Patent: February 11, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Zhen Yu, Chia-Hao Chang, Cheng-Chi Chuang, Yu-Ming Lin, Chih-Hao Wang
  • Patent number: 12223991
    Abstract: A semiconductor storage apparatus according to one embodiment of the present disclosure includes a plurality of memory cells and a control circuit. Each of the memory cells includes a magnetization reversal memory device and a first switch device that controls a current to flow to the magnetization reversal memory device. The control circuit performs a writing control based on an asymmetric property of a writing error rate curve line with respect to a writing voltage of the magnetization reversal memory device.
    Type: Grant
    Filed: April 7, 2021
    Date of Patent: February 11, 2025
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Taro Tatsuno
  • Patent number: 12224005
    Abstract: An apparatus for storing data in a nonvolatile memory includes a controller configured to erase a group of physical memory cells in the nonvolatile memory. The controller is configured to write multiple bits of information to each of a first group of physical memory cells in the nonvolatile memory. The controller is configured to map a logical address range to a physical address range for the first group of physical memory cells in the nonvolatile memory. The controller is configured to determine if the first group of physical memory cells fails a data integrity test. If the first group of physical memory cells fails the data integrity test, the controller writes at least some of the information stored in the first group of physical memory cells to a second group of physical memory cells in the nonvolatile memory. The controller writes a single bit of information per cell in the second group of physical memory cells.
    Type: Grant
    Filed: October 25, 2024
    Date of Patent: February 11, 2025
    Assignee: Vervain, LLC
    Inventor: G. R. Mohan Rao
  • Patent number: 12218668
    Abstract: A system and method for a logic device is disclosed. A substrate is provided. Three nanotracks are disposed over the substrate and intersect in a central portion. Two nanotracks are disposed about a first axis and one nanotrack is disposed about a second axis perpendicular to the first axis. A ground pad is disposed in the central portion. An input value is set by nucleating a skyrmion about a first end of the nanotracks disposed about the first axis. Presence of the skyrmion indicates a first value and absence indicates a second value. A charge current is passed in the substrate, along the first axis to move the nucleated skyrmions towards the central portion. Presence of the skyrmion is sensed in the central portion and indicates a first value when skyrmion is present.
    Type: Grant
    Filed: February 28, 2023
    Date of Patent: February 4, 2025
    Assignee: Ceremorphic, Inc.
    Inventors: Akshaykumar Salimath, Sanghamitra Debroy, Venkat Mattela
  • Patent number: 12216183
    Abstract: A magnetic sensor includes a first path and a second path, a plurality of structures, and a plurality of first electrodes and a plurality of second electrodes. The first path includes at least one first array. The second path includes at least one second array. The at least one first array and the at least one second array are disposed so that they are arranged in a first direction. The at least one first array and the at least one second array each include an odd number of structures disposed so that they are arranged in a second direction.
    Type: Grant
    Filed: August 26, 2022
    Date of Patent: February 4, 2025
    Assignee: TDK CORPORATION
    Inventors: Tetsuya Hiraki, Kenzo Makino, Naoki Ohta
  • Patent number: 12217810
    Abstract: A circuit includes a plurality of anti-fuse cells coupled to a first selection circuit, a plurality of magnetic random-access memory (MRAM) cells coupled to a second selection circuit, an amplifier including a first input terminal coupled to each of the first and second selection circuits, an analog-to-digital converter (ADC) including input terminals coupled to output terminals of the amplifier, and a comparator including a first input port coupled to an output port of the ADC. The amplifier, ADC, and comparator are configured to output data bits from the comparator responsive to current levels received from the first selection circuit at the first input terminal of the amplifier and first voltage levels received from the second selection circuit at the first input terminal of the amplifier.
    Type: Grant
    Filed: March 11, 2024
    Date of Patent: February 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Chih-Min Liu
  • Patent number: 12211524
    Abstract: A magnetoresistance effect element has a first ferromagnetic metal layer, a second ferromagnetic metal layer, and a tunnel barrier layer that is sandwiched between the first and second ferromagnetic metal layers, the tunnel barrier layer is expressed by a chemical formula of AB2Ox, and has a spinel structure in which cations are arranged in a disordered manner, A represents a divalent cation that is either Mg or Zn, and B represents a trivalent cation that includes a plurality of elements selected from the group consisting of Al, Ga, and In.
    Type: Grant
    Filed: August 15, 2023
    Date of Patent: January 28, 2025
    Assignee: TDK CORPORATION
    Inventor: Tomoyuki Sasaki
  • Patent number: 12211547
    Abstract: A method can include performing a single-read operation at a read reference voltage to detect bits from memory cells. Dummy data is previously programmed into the memory cells. Original bits of the memory cells can be determined based on a default read reference voltage and known values of the dummy data. The detected bits and the original bits are compared to determine an upper-state failed bit count (FBC) corresponding to the memory cells having threshold voltages shifted from above the read reference voltage to below the read reference voltage and a lower-state FBC corresponding to the memory cells having threshold voltages shifted from below the read reference voltage to above the read reference voltage. When a difference between the upper-state FBC and the lower-state FBC being smaller than a threshold, the read reference voltage can be determined to be a best read reference voltage.
    Type: Grant
    Filed: February 1, 2023
    Date of Patent: January 28, 2025
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventor: Lu Guo
  • Patent number: 12205623
    Abstract: Provided is a cache memory, including: a first field-effect transistor, a field-like spin torque layer underneath a magnetic tunnel junction, an electrode, and a second field-effect transistor sequentially arranged and connected; wherein the first field-effect transistor is configured to provide a writing current and to control the on-off of the writing current through a gate electrode; the field-like spin torque layer is configured to generate field-like spin torques for switching a first ferromagnetic layer of the magnetic tunnel junction; the magnetic tunnel junction includes a first ferromagnetic layer, a tunneling layer, a second ferromagnetic layer and a pinning layer arranged sequentially; the electrode is configured to connect the cache memory with the second field-effect transistor; and the second field-effect transistor is configured to control the on-off of the second field-effect transistor through the gate electrode to read the resistive state of the magnetic tunnel junction.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: January 21, 2025
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Chong Bi, Ming Liu
  • Patent number: 12207566
    Abstract: A magnetic tunneling junction (MTJ) structure is described. The MJT structure includes a stress modulating layer on a first electrode layer, where a material of the stress modulating layer is different from a material of the first electrode layer. The MJT structure further includes a MTJ material stack on the stress modulating layer. And the MJT structure further includes a second electrode layer on the MTJ material stack. The stress modulating layer reduces crystal growth defects and interfacial defects during annealing and improve the interface lattice epitaxy. This will improve device performance.
    Type: Grant
    Filed: July 27, 2023
    Date of Patent: January 21, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jesmin Haq, Tom Zhong, Vinh Lam, Vignesh Sundar, Zhongjian Teng
  • Patent number: 12205639
    Abstract: A programming method of a memory device comprising a multi-level cell is introduced. The programming method includes applying a sequence of program pulses comprising at least one set pulse and at least one reset pulse to the multi-level cell; determining whether the resistance of the multi-level cell is in a target range after each program pulse of the sequence of program pulses is applied to the multi-level cell; keeping applying the sequence of program pulses to the multi-level cell in response to determining that the resistance of the multi-level cell is not in the target range; and stopping applying the sequence of program pulses to the multi-level cell in response to determining that the resistance of the multi-level cell is in the target range.
    Type: Grant
    Filed: August 22, 2022
    Date of Patent: January 21, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jeremy Guy
  • Patent number: 12205620
    Abstract: The present disclosure generally relates to a magnetic recording system comprising a magnetic recording head. The magnetic recording head comprises a main pole, a shield, and a spintronic device disposed between the main pole and the shield. The spintronic device comprises a field generation layer (FGL) spaced a distance of about 2 nm to about 3 nm from the main pole, a first spacer layer disposed on the FGL, a spin torque layer (STL) disposed on the first spacer layer, a second spacer layer disposed on the STL, and a negative polarization layer (NPL) disposed between the second spacer layer and the shield. The spintronic device has a length of about 17 nm to about 21. During operation, the STL has a magnetization precession of about 16 degrees to about 170 degrees, and the FGL has a magnetization precession of about 60 degrees to about 70 degrees.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: January 21, 2025
    Assignee: Western Digital Technologies, Inc.
    Inventors: Alexander Goncharov, Muhammad Asif Bashir, Yunfei Ding
  • Patent number: 12207478
    Abstract: In an embodiment, a semiconductor device includes a first dielectric layer over a substrate and a first access transistor and a second access transistor in a memory cell of a memory array, the first access transistor and the second access transistor each including a bottom electrode in the first dielectric layer, a conductive gate in a second dielectric layer, where the second dielectric layer is over the bottom electrode and the first dielectric layer, a channel region extending through the conductive gate to contact the bottom electrode, and a top electrode over the channel region.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: January 21, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chenchen Jacob Wang, Sai-Hooi Yeong, Yu-Ming Lin, Chi On Chui
  • Patent number: 12205640
    Abstract: A method is provided that includes reading a plurality of resistance-switching memory cells comprising a block of data, decoding the block of data using an error correction code decoder, and based on results of the decoding, selectively performing an overwrite-read process to read the block of data. The overwrite read process determines a change in resistance of the resistance-switching memory cells in response to a write pulse.
    Type: Grant
    Filed: July 14, 2021
    Date of Patent: January 21, 2025
    Assignee: SanDisk Technologies LLC
    Inventors: Michael K. Grobis, Daniel Bedau, Christopher J. Petti
  • Patent number: 12207477
    Abstract: A semiconductor device is provided. The semiconductor device includes a base layer, a first MRAM device formed on the base layer, and a second MRAM device formed on the base layer. The first MRAM device has a different performance characteristic than the second MRAM device.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: January 21, 2025
    Assignee: International Business Machines Corporation
    Inventors: Yann Mignot, Oscar van der Straten, Dimitri Houssameddine
  • Patent number: 12198761
    Abstract: The present application provides methods for programming a circuit device with reduced disturbances. The methods may include: selecting a first target device on a target row of a plurality of rows and a target column of a plurality of columns; selecting the target row; connecting the plurality of rows other than the target row to a voltage potential with the same polarity as a programming signal; grounding the target column; preparing the programming signal on the target rows; sending a pulse signal enable an access transistor on the target column; and sending the programming signal to pass the first target device.
    Type: Grant
    Filed: November 30, 2022
    Date of Patent: January 14, 2025
    Assignee: TetraMem Inc.
    Inventor: Ning Ge
  • Patent number: 12200946
    Abstract: There is described a two-terminal multi-level memristor element synthesised from binary memristors, which is configured to implement a variable resistance based on unary or binary code words. There is further described a circuit such as a synapse circuit implemented using a multi-level memristor element.
    Type: Grant
    Filed: May 25, 2023
    Date of Patent: January 14, 2025
    Assignee: Cirrus Logic Inc.
    Inventors: John Paul Lesso, Gordon James Bates
  • Patent number: 12190927
    Abstract: A method for operating a memory device is provided. A first address is decoded to select a bit line of a memory device. A second address is decoded to select a word line of the memory device. A word line voltage is applied to the selected word line. A bit line voltage is applied to the selected bit line. A first bias voltage is applied to each of a plurality of unselected word lines connected to a plurality of memory cells connected to the selected bit line san a memory cell connected to both the selected bit line and the selected word line.
    Type: Grant
    Filed: August 20, 2021
    Date of Patent: January 7, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Sheng Chang, Chia-En Huang, Gu-Huan Li
  • Patent number: 12190929
    Abstract: The present disclosure provides a memory array, a memory cell, and a data read and write method thereof. Two storage nodes are provided in each memory cell of a memory array of a magnetic random access memory (MRAM), such that when one storage node in the memory cell fails, the other storage node in the memory cell can be used to write and read data.
    Type: Grant
    Filed: November 9, 2022
    Date of Patent: January 7, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Yulei Wu, Xiaoguang Wang
  • Patent number: 12190949
    Abstract: A memory circuit includes a bias voltage generator including a first buffer configured to generate a first bias voltage based on a reference voltage and a plurality of second buffers configured to generate a plurality of second bias voltages based on the first bias voltage. The memory circuit includes a plurality of voltage clamp devices coupled to the plurality of second buffers, and each voltage clamp device is configured to apply a drive voltage to a corresponding resistance-based memory device of a plurality of resistance-based memory devices based on the corresponding second bias voltage of the plurality of second bias voltages.
    Type: Grant
    Filed: May 12, 2023
    Date of Patent: January 7, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Perng-Fei Yuh, Shao-Ting Wu, Yu-Fan Lin
  • Patent number: 12185641
    Abstract: A plasma enhanced chemical vapor deposition (PECVD) method is disclosed for forming a SiON encapsulation layer on a magnetic tunnel junction (MTJ) sidewall that minimizes attack on the MTJ sidewall during the PECVD or subsequent processes. The PECVD method provides a higher magnetoresistive ratio for the MTJ than conventional methods after a 400° C. anneal. In one embodiment, the SiON encapsulation layer is deposited using a N2O:silane flow rate ratio of at least 1:1 but less than 15:1. A N2O plasma treatment may be performed immediately following the PECVD to ensure there is no residual silane in the SiON encapsulation layer. In another embodiment, a first (lower) SiON sub-layer has a greater Si content than a second (upper) SiON sub-layer. A second encapsulation layer is formed on the SiON encapsulation layer so that the encapsulation layers completely fill the gaps between adjacent MTJs.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: December 31, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Vignesh Sundar, Yu-Jen Wang, Dongna Shen, Sahil Patel, Ru-Ying Tong
  • Patent number: 12178052
    Abstract: A MRAM circuit structure is provided in the present invention, with the unit cell composed of three transistors in series and four MTJs, wherein the junction between first transistor and third transistor is first node, the junction between second transistor and third transistor is second node, and the other ends of first transistor and third transistor are connected to a common source line. First MTJ is connected to second MTJ in series to form a first MTJ pair that connecting to the first node, and third MTJ is connected to fourth MTJ in series to form a second MTJ pair that connecting to the second node.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: December 24, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Ting Wu, Cheng-Tung Huang, Jen-Yu Wang, Yung-Ching Hsieh, Po-Chun Yang, Jian-Jhong Chen, Bo-Chang Li
  • Patent number: 12165684
    Abstract: The present disclosure is drawn to a magnetoresistive device including an array of memory cells arranged in rows and columns, each memory cell comprising a magnetic tunnel junction, each row comprising a word line, and each column comprising a bit line; a column select device that selects a bit line. The magnetoresistive device also includes a sense amplifier comprising a first input corresponding to a selected bit line, a second input corresponding to a reference bit line, and a data output. The plurality of columns comprise a reference column, the reference column comprising a conductive element coupled to the magnetic tunnel junctions in the reference column.
    Type: Grant
    Filed: April 10, 2023
    Date of Patent: December 10, 2024
    Assignee: Everspin Technologies, Inc.
    Inventors: Syed M. Alam, Yaojun Zhang, Frederick Neumeyer
  • Patent number: 12165733
    Abstract: A sense amplifier of a memory device that includes sense amplifier circuits and a reference sharing circuit is introduced. The sense amplifier circuits are configured to sense the plurality of bit lines according to an enable signal. The reference sharing circuit includes first switches and second switches that are coupled to the reference nodes and second reference nodes of the sense amplifier circuits, respectively. The first switches and second switches are controlled according to a control signal to control a first electrical connection among the first reference nodes, and to control a second electrical connection among the second reference nodes. An operation method of the sense amplifier and a memory device including the sense amplifier are also introduced.
    Type: Grant
    Filed: April 14, 2022
    Date of Patent: December 10, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Win-San Khwa, Yen-Cheng Chiu, Yi-Lun Lu, Jui-Jen Wu, Meng-Fan Chang
  • Patent number: 12160529
    Abstract: A reconfigurable PUF device based on fully electric field-controlled domain wall motion includes a voltage control layer, upper electrodes, a lower electrode, antiferromagnetic pinning layers, and a magnetic tunnel junction (MTJ). The MTJ includes, from bottom to top, a ferromagnetic reference layer, a potential barrier tunneling layer and a ferromagnetic free layer. In the device, an energy potential well is formed in a middle portion of the ferromagnetic free layer by applying a voltage to the voltage control layer to control magnetic anisotropy, and a current is fed into either of the upper electrodes to drive generation of the magnetic domain walls and pin the magnetic domain walls to the potential well. After the voltage is removed, the potential well is lowered so that the magnetic domain walls are in a metastable state, thereby either a high resistance state or a low resistance state is randomly obtained.
    Type: Grant
    Filed: December 5, 2022
    Date of Patent: December 3, 2024
    Assignee: INSTITUTE OF MICROELECTRONICS OF THE CHINESE ACADEMY OF SCIENCES
    Inventors: Guozhong Xing, Huai Lin, Di Wang, Long Liu, Kaiping Zhang, Guanya Wang, Yan Wang, Xiaoxin Xu, Ming Liu
  • Patent number: 12159670
    Abstract: A non-volatile storage circuit (10) of an embodiment includes a volatile storage unit (11) that stores information, a non-volatile storage unit (20) into which the information in the volatile storage unit is written by a store operation, and from which the information is read out to the volatile storage unit (11) by a restore operation via a restore path different from a store path in the store operation, a driver unit (12, 15) that receives a power supply and performs the store operation, and a switch unit (13, 14, 16, 17) that shuts off the power supply to the driver unit (12, 15) during the restore operation.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: December 3, 2024
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Keizo Hiraga
  • Patent number: 12153101
    Abstract: One example discloses a sensor calibration circuit, including: a controller configured to transmit a first modulation signal to the sensor and receive a first output signal from the sensor in response; wherein the controller configured to transmit a second modulation signal to the sensor and receive a second output signal from the sensor in response; and wherein the controller is configured to calibrate the sensor based on the first and second modulation signals and the first and second output signals.
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: November 26, 2024
    Assignee: NXP USA, Inc.
    Inventors: Klaus Reimann, Siamak Delshadpour
  • Patent number: 12136455
    Abstract: A flash controller for managing at least one MLC non-volatile memory module and at least one SLC non-volatile memory module. The flash controller is adapted to determine if a range of addresses listed by an entry and mapped to said at least one MLC non-volatile memory module fails a data integrity test. In the event of such a failure, the controller remaps said entry to an equivalent range of addresses of said at least one SLC non-volatile memory module. The flash controller is further adapted to determine which of the blocks in the MLC and SLC non-volatile memory modules are accessed most frequently and allocating those blocks that receive frequent writes to the SLC non-volatile memory module and those blocks that receive infrequent writes to the MLC non-volatile memory module.
    Type: Grant
    Filed: March 22, 2024
    Date of Patent: November 5, 2024
    Assignee: Vervain, LLC
    Inventor: G. R. Mohan Rao
  • Patent number: 12133394
    Abstract: A magnetic memory device including a first memory cell which includes a first stacked structure including a magnetic layer and a second memory cell which is provided on the first memory cell and includes a second stacked structure including a magnetic layer. Each of the first stacked structure and the second stacked structure includes a first magnetic layer having a variable magnetization direction, a second magnetic layer having a fixed magnetization direction, and a nonmagnetic layer provided between the first magnetic layer and the second magnetic layer. A concentration of iron (Fe) contained in the first magnetic layer included in the first stacked structure and a concentration of iron (Fe) contained in the first magnetic layer included in the second stacked structure are different from each other.
    Type: Grant
    Filed: August 1, 2023
    Date of Patent: October 29, 2024
    Assignee: Kioxia Corporation
    Inventors: Masayoshi Iwayama, Tatsuya Kishi, Masahiko Nakayama, Toshihiko Nagase, Daisuke Watanabe, Tadashi Kai
  • Patent number: 12132526
    Abstract: A system includes a group of transceiver nodes and diagnostic circuitry. A first transceiver node of the group broadcasts one or more beacons which a second transceiver node of the group attempts to receive. The second transceiver node provides a reception indication to the diagnostic circuitry. Based on the reception indication, the diagnostic circuitry determines a radio performance change for the first transceiver node and/or second transceiver node. Using a change threshold based on a distribution of radio performance changes for the group, the diagnostic circuitry may determine whether to generate a change indication for the first transceiver node and/or second transceiver node.
    Type: Grant
    Filed: August 26, 2022
    Date of Patent: October 29, 2024
    Assignee: Building Robotics, Inc.
    Inventor: Jun Gao
  • Patent number: 12125512
    Abstract: The present disclosure generally relates to spin-orbit torque (SOT) magnetic tunnel junction (MTJ) devices comprising a doped bismuth antimony (BiSbE) layer having a (012) orientation. The devices may include magnetic write heads, read heads, or MRAM devices. The dopant in the BiSbE layer enhances the (012) orientation. The BiSbE layer may be formed on a texturing layer to ensure the (012) orientation, and a migration barrier may be formed over the BiSbE layer to ensure the antimony does not migrate through the structure and contaminate other layers. A buffer layer and interlayer may also be present. The buffer layer and the interlayer may each independently be a single layer of material or a multilayer of material. The buffer layer and the interlayer inhibit antimony (Sb) migration within the doped BiSbE layer and enhance uniformity of the doped BiSbE layer while further promoting the (012) orientation of the doped BiSbE layer.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: October 22, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Quang Le, Cherngye Hwang, Brian R. York, Randy G. Simmons, Xiaoyong Liu, Kuok San Ho, Hisashi Takano, Michael A. Gribelyuk, Xiaoyu Xu
  • Patent number: 12119054
    Abstract: A controller for managing at least one MLC non-volatile memory space including at least one MLC non-volatile memory element and at least one SLC non-volatile memory space including at least one SLC non-volatile memory element. The controller is adapted to determine if a range of addresses listed by an entry and mapped to the at least one MLC non-volatile memory element fails a data integrity test performed at the controller based upon received data retained at the controller and which received data is stored in the at least one MLC memory element as stored data. In the event of such a failure, the controller remaps said entry to an the at least one SLC non-volatile memory element.
    Type: Grant
    Filed: March 22, 2024
    Date of Patent: October 15, 2024
    Assignee: Vervain, LLC
    Inventor: G. R. Mohan Rao
  • Patent number: 12119069
    Abstract: In an anti-fuse memory reading circuit with controllable reading time, a reading time control circuit generates a control signal corresponding to reading time. Based on a clock signal, a programmable reading pulse generation circuit generates a reading pulse with a pulse width corresponding to the control signal. Based on the reading pulse and the control signal, the reading amplification circuit selects a pull-up current source corresponding to the reading time, pulls up a voltage on a bit line (BL) of an anti-fuse memory cell, reads data stored in the anti-fuse memory cell starting from a rising edge of the reading pulse, and latches the read data at a falling edge of the reading pulse. The anti-fuse memory reading circuit can generate a reading pulse with a corresponding pulse width and a pull-up current source with a corresponding size based on the required reading time.
    Type: Grant
    Filed: September 29, 2022
    Date of Patent: October 15, 2024
    Assignee: WUXI ESIONTECH CO., LTD.
    Inventors: Zhengzhou Cao, Jie Zhu, Yanfei Zhang, Jing Sun, Zhenkai Ji, Zhengnan Ding
  • Patent number: 12112825
    Abstract: The present application provides a sense amplifier, a memory, and a control method. The sense amplifier includes: an amplification module, configured to amplify a voltage difference between a bit line and a reference bit line when the sense amplifier is at an amplification stage; and a controlled power module, connected to the amplification module, and configured to: determine a drive parameter according to a rated compensation voltage range between the bit line and the reference bit line, and supply power to the amplification module according to the drive parameter, so as to control the amplification module to pull a compensation voltage between the bit line and the reference bit line to be a rated compensation voltage at an offset cancellation stage, where the rated compensation voltage is within the rated compensation voltage range.
    Type: Grant
    Filed: July 21, 2021
    Date of Patent: October 8, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Hsin-Cheng Su
  • Patent number: 12108683
    Abstract: A magnetic tunnel junction device and an operating method thereof are disclosed. The magnetization switching of a free layer may be induced through spin orbit torque or spin transfer torque, and a magnetization direction of a pinned layer may be easily set according to the intention of a designer through ferromagnetic coupling and antiferromagnetic coupling.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: October 1, 2024
    Assignee: IUCF-HYU (INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY)
    Inventors: Jin Pyo Hong, Jeong Hun Shin, Yoon Seong Choi
  • Patent number: 12096148
    Abstract: An image sensor device includes a first image pixel connected to a first data line, a second image pixel connected to the first data line, an analog-to-digital converter that generates a digital signal based on a ramp signal and a voltage level of the first data line, and a clamp signal generator that generates a clamp signal depending on an analog gain of the analog-to-digital converter. While a data voltage is provided from the first image pixel to the first data line, the second image pixel provides a clamp voltage to the first data line based on the clamp signal.
    Type: Grant
    Filed: October 21, 2022
    Date of Patent: September 17, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jinyoung Jeong, Jewon Lee, Seokyong Hong
  • Patent number: 12089501
    Abstract: Semiconductor structure and fabrication method are provided. The semiconductor structure includes: a substrate and a magnetic tunnel junction on the substrate. The magnetic tunnel junction includes: a bottom electromagnetic structure on the substrate, an insulating layer on the bottom electromagnetic structure, and a top electromagnetic structure on the insulating layer. The semiconductor structure further includes a sidewall tunneling layer on sidewall surfaces of the magnetic tunnel junction.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: September 10, 2024
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Ming Zhou
  • Patent number: 12089507
    Abstract: A semiconductor device for internet of things (IoT) device includes a substrate having an array region defined thereon and a ring of dummy pattern surrounding the array region. Preferably, the ring of dummy pattern includes a plurality of magnetic tunneling junctions (MTJs) and a ring of metal interconnect pattern overlapping the MTJs and surrounding the array region. The semiconductor device further includes a gap between the array region and the ring of dummy pattern.
    Type: Grant
    Filed: March 7, 2023
    Date of Patent: September 10, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chun-Hsien Lin
  • Patent number: 12085603
    Abstract: A noise monitoring apparatus includes a row selection circuit, a direct current (DC) cancellation circuit and an amplifier circuit. The row selection circuit selects a row of a DUT array to be a selected row during a readout period, wherein the selected row comprises a plurality of selected DUTs. The DC cancellation circuit is coupled to unselected DUTs of the DUT array during the readout period, generates a DC current signal based on bias current signals from a group of unselected DUTs and subtract the DC current signal from a first noise signal of the selected DUT to generate a second noise signal. The amplifier circuit is coupled to the plurality of selected DUTs of the selected row during the readout period, and amplifies the second noise signal from each of the selected DUTs to generate an output signal.
    Type: Grant
    Filed: August 2, 2022
    Date of Patent: September 10, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin Yin, Chih-Lin Lee, Kuo-Yu Chou
  • Patent number: RE50331
    Abstract: A magnetoresistive element (e.g., a spin-torque magnetoresistive memory element) includes a fixed magnetic layer, a free magnetic layer, having a high-iron alloy interface region located along a surface of the free magnetic layer, wherein the high-iron alloy interface region has at least 50% iron by atomic composition, and a first dielectric, disposed between the fixed magnetic layer and the free magnetic layer. The magnetoresistive element further includes a second dielectric, having a first surface that is in contact with the surface of the free magnetic layer, and an electrode, disposed between the second dielectric and a conductor. The electrode includes: (i) a non-ferromagnetic portion having a surface that is in contact with a second surface of the second dielectric, and (ii) a second portion having at least one ferromagnetic material disposed between the non-ferromagnetic portion of the electrode and the conductor.
    Type: Grant
    Filed: April 8, 2022
    Date of Patent: March 4, 2025
    Assignee: Everspin Technologies, Inc.
    Inventors: Renu Whig, Jijun Sun, Nicholas Rizzo, Jon Slaughter, Dimitri Houssameddine, Frederick Mancoff