Magnetoresistive Patents (Class 365/158)
  • Patent number: 11990168
    Abstract: According to one embodiment, a magnetic device includes first and second conductive portions, first and second stacked bodies, and a controller. The first conductive portion includes first to third region. The third region is between the first and second regions. The first stacked body includes first and second magnetic layers. The second magnetic layer is between the third region and the first magnetic layer. The second conductive portion includes fourth to sixth regions. The sixth region is between the fourth and fifth regions. The second stacked body includes third and fourth magnetic layers. The fourth magnetic layer is between the sixth region and the third magnetic layer. The first stacked body is configured to be in a first low or high electrical resistance state. The second stacked body is configured to be in a second low high electrical resistance state.
    Type: Grant
    Filed: October 8, 2020
    Date of Patent: May 21, 2024
    Assignee: SP-AITH LIMITED
    Inventors: Hiroaki Yoda, Yuichi Ohsawa, Yushi Kato, Tomomi Yoda
  • Patent number: 11990182
    Abstract: An operation method for a memory device is provided. The memory device includes a two-terminal selector and a resistance variable storage element coupled to the two-terminal selector. The method includes providing a voltage pulse to the memory device. A voltage applied across the two-terminal selector during a falling part of the voltage pulse falls below a holding voltage of the two-terminal selector. A voltage falling rate of the falling part at which the voltage applied across the two-terminal selector reaches the holding voltage is raised for reducing threshold voltage drift of the two-terminal selector.
    Type: Grant
    Filed: January 18, 2022
    Date of Patent: May 21, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hengyuan Lee, Cheng-Hsien Wu, Yu-Sheng Chen, Elia Ambrosi, Chien-Min Lee, Xinyu Bao
  • Patent number: 11980104
    Abstract: According to one embodiment, a magnetic memory device includes a magnetoresistance effect element including a first magnetic layer having a variable magnetization direction, a second magnetic layer having a variable magnetization direction, a third magnetic layer having a fixed magnetization direction and a nonmagnetic layer, the first magnetic layer being provided between the second and third magnetic layers, and the nonmagnetic layer being provided between the first and third magnetic layers. The second magnetic layer has a superlattice structure in which first element layers and second element layers are alternately stacked. The first element is Co, and the second element is selected from Pt, Ni and Pd, and the second magnetic layer contains Cr as a third element.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: May 7, 2024
    Assignee: Kioxia Corporation
    Inventors: Masaru Toko, Hideyuki Sugiyama, Soichi Oikawa, Masahiko Nakayama
  • Patent number: 11980026
    Abstract: A random code generating method for the magnetoresistive random access memory is provided. Firstly, a first magnetoresistive random access memory cell and a second magnetoresistive random access memory cell are programmed into an anti-parallel state. Then, an initial value of a control current is set. Then, an enroll action is performed on the first and second magnetoresistive random access memory cells. If the first and second magnetoresistive random access memory cells fail to pass the verification action, the control current is increased by a current increment, and the step of setting the control current is performed again. If the first and second magnetoresistive random access memory cells pass the verification action, a one-bit random code is stored in the first magnetoresistive random access memory cell or the second magnetoresistive random access memory cell.
    Type: Grant
    Filed: June 14, 2022
    Date of Patent: May 7, 2024
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Tsung-Mu Lai, Chun-Yuan Lo, Chun-Chieh Chao
  • Patent number: 11978491
    Abstract: Technology for reading reversible resistivity cells in a memory array when using a current-force read is disclosed. The memory cells are first read using a current-force referenced read. If the current-force referenced read is successful, then results of the current-force referenced read are returned. If the current-force referenced read is unsuccessful, then a current-force self-referenced read (SRR) is performed and results of the current-force SRR are returned. In an aspect this mixed current-force read is used for MRAM cells, which are especially challenging to read.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: May 7, 2024
    Assignee: SanDisk Technologies LLC
    Inventors: Michael Nicolas Albert Tran, Ward Parkinson, Michael Grobis, Nathan Franklin, Raj Ramanujan
  • Patent number: 11972822
    Abstract: Technology is disclosed for a fast ECC engine for a mixed read of MRAM cells. A codeword read from MRAM cells using a referenced read is decoded using a first ECC mode. If decoding passes, results are provided to a host. If decoding fails, a self-referenced read (SRR) is performed. The data read using the SRR is decoded with a second ECC mode that is capable of correcting a greater number of bits than the first ECC mode. The second ECC mode may have a higher mis-correction rate than the first ECC mode (for a given raw bit error rate (RBER)). However, the RBER may be lower when using the second ECC mode. Therefore, the first and second ECC modes may result in about the same probability of an undetectable error (or mis-correction).
    Type: Grant
    Filed: December 15, 2021
    Date of Patent: April 30, 2024
    Assignee: SanDisk Technologies LLC
    Inventors: Martin Hassner, Michael Nicolas Albert Tran, Ward Parkinson, Michael Grobis, Nathan Franklin, Raj Ramanujan
  • Patent number: 11973105
    Abstract: An integrated circuit structure comprises at least one metal gate formed in a first dielectric layer, the at least one metal gate comprising a workfunction layer and the gate oxide layer along sidewalls of the first dielectric layer. A field effect (FE) dielectric layer dielectric layer is above the first dielectric layer of the at least one metal gate. A precision resistor comprising a thin-film metallic material is formed on the FE dielectric layer above the at least one metal gate and extending laterally over the at least one metal gate.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: April 30, 2024
    Assignee: Intel Corporation
    Inventors: Chieh-Jen Ku, Bernhard Sell, Leif Paulson, Kinyip Phoa, Shi Liu
  • Patent number: 11972798
    Abstract: A nonvolatile memory includes a first memory cell and a second memory cell above the first memory cell. The first memory cell includes a variable resistance layer extending in a first direction, a semiconductor layer extending in the first direction and in contact with the variable resistance layer, an insulator layer extending in the first direction and in contact with the semiconductor layer, and a first voltage applying electrode extending in a second direction and in contact with the insulator layer. The second memory cell includes a second voltage applying electrode in contact with the insulator layer. When a write operation is performed on the first memory cell, a first voltage is applied to the second voltage applying electrode, and when a write operation is performed on the second memory cell, a second voltage, lower than the first voltage, is applied to the first voltage applying electrode.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: April 30, 2024
    Assignee: Kioxia Corporation
    Inventors: Tomoki Chiba, Daisaburo Takashima, Hidehiro Shiga
  • Patent number: 11972787
    Abstract: Technology is disclosed herein for refreshing threshold switching selectors in programmable resistance memory cells in cross-point memory arrays. The Vt of the threshold switching selector may drift over time. The memory system resets the Vt of the threshold switching selectors with a selector refresh operation and uses a separate data refresh operation to refresh data in programmable resistance memory elements. The data refresh operation itself may also refresh the selector. However, the threshold switching selector refresh operation is faster than the data refresh operation. Moreover, the selector refresh operation consumes much less power and/or current then the data refresh operation. The selector refresh operation may thus be performed at a higher rate than the data refresh operation.
    Type: Grant
    Filed: May 25, 2022
    Date of Patent: April 30, 2024
    Assignee: SanDisk Technologies LLC
    Inventors: Michael Nicolas Albert Tran, Michael K. Grobis, Ward Parkinson, Nathan Franklin
  • Patent number: 11967375
    Abstract: A memory device that includes at least one memory cell is introduced. Each of the at least one memory cell is coupled to a bit line and a word line. Each of the at least one memory cell includes a memory element and a selector element, in which the memory element is configured to store data of the at least one memory cell. The selector element is coupled to the memory element in series and is configured to select the memory element for a read operation and amplify the data stored in the memory element in the read operation.
    Type: Grant
    Filed: November 18, 2021
    Date of Patent: April 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Li Chiang, Chao-Ching Cheng, Tzu-Chiang Chen, Yu-Sheng Chen, Hon-Sum Philip Wong
  • Patent number: 11967370
    Abstract: A controller for managing at least one MLC non-volatile memory space including at least one MLC non-volatile memory element and at least one SLC non-volatile memory space including at least one SLC non-volatile memory element. The controller is adapted to determine if a range of addresses listed by an entry and mapped to the at least one MLC non-volatile memory element fails a data integrity test performed at the controller based upon received data retained at the controller and which received data is stored in the at least one MLC memory element as stored data. In the event of such a failure, the controller remaps said entry to an the at least one SLC non-volatile memory element.
    Type: Grant
    Filed: December 20, 2023
    Date of Patent: April 23, 2024
    Assignee: Vervain, LLC
    Inventor: G. R. Mohan Rao
  • Patent number: 11968909
    Abstract: The output voltage of an MRAM is increased by means of an Fe(001)/MgO(001)/Fe(001) MTJ device, which is formed by microfabrication of a sample prepared as follows: A single-crystalline MgO (001) substrate is prepared. An epitaxial Fe(001) lower electrode (a first electrode) is grown on a MgO(001) seed layer at room temperature, followed by annealing under ultrahigh vacuum. A MgO(001) barrier layer is epitaxially formed on the Fe(001) lower electrode (the first electrode) at room temperature, using a MgO electron-beam evaporation. A Fe(001) upper electrode (a second electrode) is then formed on the MgO(001) barrier layer at room temperature. This is successively followed by the deposition of a Co layer on the Fe(001) upper electrode (the second electrode). The Co layer is provided so as to increase the coercive force of the upper electrode in order to realize an antiparallel magnetization alignment.
    Type: Grant
    Filed: July 7, 2023
    Date of Patent: April 23, 2024
    Assignee: Godo Kaisha IP Bridge 1
    Inventor: Shinji Yuasa
  • Patent number: 11968843
    Abstract: An embodiment of an integrated circuit chip includes a combination processing core and magnetoresistive random access memory (MRAM) circuitry integrated into the chip. The MRAM circuitry includes a plurality of MRAM cells. The MRAM cells are organized into a number of memories, including a cache memory, a main or working memory and an optional secondary storage memory. The cache memory includes multiple cache levels.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: April 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Te Lin, Yen-Chung Ho, Pin-Cheng Hsu, Han-Ting Tsai, Katherine Chiang
  • Patent number: 11967350
    Abstract: A system and method for a memory device is disclosed. A substrate is provided. A nucleation pad is disposed over the substrate. A nanowire is disposed substantially perpendicular, about a center of the nucleation pad. A charge current is selectively passed through the substrate to nucleate a magnetic vortex in the nucleation pad, the magnetic vortex indicative of a magnetic domain and a direction of the magnetic vortex indicative of a polarity of the magnetic domain. A shift current is applied through the nanowire to shift the magnetic domain into the nanowire.
    Type: Grant
    Filed: January 31, 2022
    Date of Patent: April 23, 2024
    Assignee: Ceremorphic,inc.
    Inventors: Akshaykumar Salimath, Venkat Mattela, Sanghamitra Debroy
  • Patent number: 11961545
    Abstract: Various embodiments of the present disclosure are directed towards a memory device. The memory device has a first transistor having a first source/drain and a second source/drain, where the first source/drain and the second source/drain are disposed in a semiconductor substrate. A dielectric structure is disposed over the semiconductor substrate. A first memory cell is disposed in the dielectric structure and over the semiconductor substrate, where the first memory cell has a first electrode and a second electrode, where the first electrode of the first memory cell is electrically coupled to the first source/drain of the first transistor. A second memory cell is disposed in the dielectric structure and over the semiconductor substrate, where the second memory cell has a first electrode and a second electrode, where the first electrode of the second memory cell is electrically coupled to the second source/drain of the first transistor.
    Type: Grant
    Filed: December 7, 2022
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fa-Shen Jiang, Hsia-Wei Chen, Hsun-Chung Kuang, Hai-Dang Trinh, Cheng-Yuan Tsai
  • Patent number: 11963456
    Abstract: Embodiments of present invention provide a method of improving yield of making MRAM arrays. More specifically, the method includes receiving an MRAM array; identifying a weak MRAM cell from the MRAM array wherein the weak MRAM cell includes an access transistor; and modifying the access transistor. In one embodiment, modifying the access transistor includes performing a hot carrier injection into a gate dielectric layer of the access transistor.
    Type: Grant
    Filed: April 12, 2022
    Date of Patent: April 16, 2024
    Assignee: International Business Machines Corporation
    Inventors: Dimitri Houssameddine, Kangguo Cheng, Julien Frougier, Ruilong Xie
  • Patent number: 11963462
    Abstract: A memory device has a magnetic tunnel junction (MTJ) element that includes a free layer structure, a free/pinned layer structure, and a tunnel barrier structure between the free layer structure and the free/pinned layer structure. A first electrode is coupled to the free layer structure, and a second electrode is coupled to the free/pinned layer structure. Processing circuitry is operatively coupled to the MTJ element. The processing circuitry is configured to apply a voltage to the MTJ element to modulate magnetic anisotropy using an electric field, to enable writing with reduced write currents; issue a charge current to the MTJ element to induce spin-dependent writing and magnetic spin accumulation in the free layer structure to set a bit state of the MTJ element, using spin-transfer torque into the free layer structure; and remove the voltage from the MTJ element that modulates the magnetic anisotropy, to perform a write operation.
    Type: Grant
    Filed: March 18, 2022
    Date of Patent: April 16, 2024
    Assignee: Honeywell International Inc.
    Inventor: Romney R. Katti
  • Patent number: 11963463
    Abstract: Magnetic random access memory (MRAM) cells are provided. MRAM cell includes a plurality of stacked magnetic tunnel junction (MTJ) devices coupled in serial, and a transistor. The transistor has a gate coupled to a word line, a first terminal coupled to a bit line through the stacked MTJ devices, and a second terminal coupled to a source line. The stacked MTJ devices have different sizes. Each of the stacked MTJ devices includes a free layer, a pinned layer and a barrier layer between the free layer and the pinned layer. The free layers of two adjacent stacked MTJ devices are in direct contact with each other.
    Type: Grant
    Filed: May 2, 2022
    Date of Patent: April 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Perng-Fei Yuh, Yih Wang
  • Patent number: 11957063
    Abstract: A magnetoresistive element comprises a nonmagnetic nano-current-channel (NCC) structure provided on a surface of the magnetic recording layer, which is opposite to a surface of the magnetic recording layer where the tunnel barrier layer is provided, and comprising a spatial distribution of perpendicular conducting channels throughout the NCC structure thickness and surrounded by an insulating medium, making the magnetic recording layer a magnetically soft-hard composite structure. Correspondingly, the critical write current and write power are reduced with reversal modes of exchange-spring magnets of the magnetically soft-hard composite structure.
    Type: Grant
    Filed: August 28, 2021
    Date of Patent: April 9, 2024
    Inventors: Yimin Guo, Rongfu Xiao, Jun Chen
  • Patent number: 11955549
    Abstract: A semiconductor device includes a transistor and a ferroelectric tunnel junction. The ferroelectric tunnel junction is connected to a drain contact of the transistor. The ferroelectric tunnel junction includes a first electrode, a second electrode, a crystalline oxide layer, and a ferroelectric layer. The second electrode is disposed over the first electrode. The crystalline oxide layer and the ferroelectric layer are disposed in direct contact with each other in between the first electrode and the second electrode. The crystalline oxide layer comprises a crystalline oxide material. The ferroelectric layer comprises a ferroelectric material.
    Type: Grant
    Filed: July 1, 2022
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mauricio Manfrini, Han-Jong Chia
  • Patent number: 11948616
    Abstract: The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate; a transistor, including a control terminal, a first terminal, and a second terminal; a first magnetic memory structure, a bottom electrode of which is electrically connected to the first terminal of the transistor; a second magnetic memory structure, a top electrode of which is electrically connected to the first terminal of the transistor, the bottom electrode of the first magnetic memory structure is located in a same layer with a bottom electrode of the second magnetic memory structure; a first bit line, electrically connected to a top electrode of the first magnetic memory structure; a second bit line, electrically connected to the bottom electrode of the second magnetic memory structure; and a selection line, electrically connected to a second terminal of the transistor.
    Type: Grant
    Filed: June 23, 2022
    Date of Patent: April 2, 2024
    Assignees: CHANGXIN MEMORY TECHNOLOGIES, INC., BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY
    Inventors: Xiaoguang Wang, Dinggui Zeng, Huihui Li, Jiefang Deng, Kanyu Cao
  • Patent number: 11942128
    Abstract: Disclosed is a magnetic memory device including a pinned magnetic pattern and a free magnetic pattern that are sequentially stacked on a substrate, a tunnel barrier pattern between the pinned magnetic pattern and the free magnetic pattern, a top electrode on the free magnetic pattern, and a capping pattern between the free magnetic pattern and the top electrode. The capping pattern includes a lower capping pattern, an upper capping pattern between the lower capping pattern and the top electrode, a first non-magnetic pattern between the lower capping pattern and the upper capping pattern, and a second non-magnetic pattern between the first non-magnetic pattern and the upper capping pattern. Each of the lower capping pattern and the upper capping pattern includes a non-magnetic metal. The first non-magnetic pattern and the second non-magnetic pattern include different metals from each other.
    Type: Grant
    Filed: January 14, 2022
    Date of Patent: March 26, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Whankyun Kim, Jeong-Heon Park, Heeju Shin, Youngjun Cho, Joonmyoung Lee, Junho Jeong
  • Patent number: 11943935
    Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region, a second cell region, a third cell region, and a fourth cell region and a diffusion region on the substrate extending through the first cell region, the second cell region, the third cell region, and the fourth cell region. Preferably, the diffusion region includes a H-shape according to a top view.
    Type: Grant
    Filed: September 26, 2022
    Date of Patent: March 26, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Yen Tseng, Shu-Ru Wang, Yu-Tse Kuo, Chang-Hung Chen, Yi-Ting Wu, Shu-Wei Yeh, Ya-Lan Chiou, Chun-Hsien Huang
  • Patent number: 11942129
    Abstract: A magnetic tunnel junction is provided. The magnetic tunnel junction comprises an insulating tunnel barrier and a fixed ferromagnet layer adjacent the tunnel barrier. The fixed ferromagnet comprises a fixed magnetization along an easy axis approximately normal to an interface between the fixed ferromagnet and the tunnel barrier. A free ferromagnet layer is adjacent the tunnel barrier on the side opposite the fixed ferromagnet. The free ferromagnet layer comprises a bistable magnetization along the easy axis that can switch between a parallel state and an anti-parallel state with the fixed ferromagnet. A heavy metal layer is adjacent the free ferromagnet on the side opposite the tunnel barrier. A unidirectional electric current pulse through the heavy metal layer switches the bistable magnetization of the free ferromagnet, thereby switching an electrical resistance state of the magnetic tunnel junction.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: March 26, 2024
    Assignee: Board of Regents, The University of Texas System
    Inventors: Joseph S. Friedman, Naimul Hassan
  • Patent number: 11937435
    Abstract: Embodiments disclosed herein include a semiconductor structure. The semiconductor structure may include a semiconductor structure. The semiconductor structure may include an embedded magnetic random access memory (MRAM) array electrically connected between a bottom metal level and a top metal level. The MRAM array may include a first tier with first MRAM cells and first vias above the first MRAM cells, and a second tier with second MRAM cells and second vias below the second MRAM cells.
    Type: Grant
    Filed: October 28, 2021
    Date of Patent: March 19, 2024
    Assignee: International Business Machines Corporation
    Inventors: Ashim Dutta, Chih-Chao Yang
  • Patent number: 11929128
    Abstract: A circuit includes an operational amplifier including an inverting input terminal capacitively coupled to each of an OTP cell array and an NVM cell array and first and second output terminals, an ADC coupled to the first and second output terminals, thereby configured to receive a differential output voltage from the operational amplifier, and a comparator coupled to the ADC and configured to output a data bit responsive to a digital output signal received from the ADC. The circuit is configured to cause the operational amplifier to generate the differential output voltage based on each of a current received from an OTP cell of the OTP cell array and a voltage received from an NVM cell of the NVM cell array.
    Type: Grant
    Filed: March 27, 2023
    Date of Patent: March 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Chih-Min Liu
  • Patent number: 11930720
    Abstract: The present disclosure provides a storage unit, a data writing method and a data reading method thereof, a memory and an electronic device. The storage unit includes a semiconductor substrate, a first insulating medium layer, a ferroelectric thin film layer, a bottom electrode, a tunnel junction, a first metal interconnection portion, a second metal interconnection portion, a third metal interconnection portion and a fourth metal interconnection portion. The first insulating medium layer is formed on the semiconductor substrate, the ferroelectric thin film layer is disposed on the first insulating medium layer, the bottom electrode is formed on the ferroelectric thin film layer, and the tunnel junction is formed on the bottom electrode. The first metal interconnection portion is connected to a first end of the bottom electrode, and the third metal interconnection portion is connected to a second end of the bottom electrode.
    Type: Grant
    Filed: October 6, 2021
    Date of Patent: March 12, 2024
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Meiyin Yang, Jun Luo, Yan Cui, Jing Xu
  • Patent number: 11929106
    Abstract: A first memory cell includes a first variable resistance element and a first switching element. A control circuit is configured to execute first detection of detecting a first value of a first physical quantity related to the first memory cell, execute first write for storing first data in the first memory cell, execute second detection of detecting a second value of the first physical quantity related to the first memory cell following the first write, and read second data related to the first memory cell based on the first value and the second value. At least one of the first value and the second value is a value during a change in the first physical quantity related to the first memory cell.
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: March 12, 2024
    Assignee: Kioxia Corporation
    Inventor: Fumiyoshi Matsuoka
  • Patent number: 11930719
    Abstract: Magnetic memory devices are provided. The devices comprise a first ferromagnetic layer, a second ferromagnetic layer, and a tunnel barrier layer composed of a doped semiconductor (instead of an insulator or a dielectric) between the first and second ferromagnetic layers and forming at least one ferromagnetic-doped semiconductor interface.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: March 12, 2024
    Assignee: Northwestern University
    Inventors: Pedram Khalili Amiri, Manijeh Razeghi
  • Patent number: 11921835
    Abstract: A MLU-based magnetic device including a plurality of MLU-based magnetic cells, each MLU cell including a first ferromagnetic layer having a first magnetization, a second ferromagnetic layer having a second magnetization, and a spacing layer between the first and second ferromagnetic layers. An input device is configured for generating an input signal adapted for changing the orientation of the first magnetization relative to the second magnetization and vary a resistance of the MLU device. A bit line is configured for passing a sense signal adapted for measuring the resistance. A processing unit is configured for computing an electrical variation from the sense signal and outputting an electrical variation signature. The present disclosure further pertains to an authentication method for reading the MLU device.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: March 5, 2024
    Assignee: CROCUS TECHNOLOGY SA
    Inventors: Quentin Stainer, Myckael Mouchel, Yann Conraux
  • Patent number: 11923657
    Abstract: Provided are a laser diode driver for a multilevel optical signal and a multilevel optical signal transmission device including the same, wherein the laser diode driver includes: a clock generator configured to generate and output a clock signal; a first latch configured to delay output of data corresponding to a first timing of the clock signal from among data sequentially input at each data input period; a second latch configured to delay output of data corresponding to a second timing of the clock signal from among data sequentially input at each data input period; a first synchronization processor configured to output a signal corresponding to the data input by the first latch according to the clock signal; and a second synchronization processor configured to output a signal corresponding to the data input by the second latch according to the clock signal.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: March 5, 2024
    Assignee: SOLiD, INC.
    Inventor: Won Song Chang
  • Patent number: 11922986
    Abstract: The present invention relates to a kind of magnetic heterojunction structure and the method of controlling and achieving spin logic and multiple-state storage functions. The said single magnetic heterojunction structure comprises the substrate, in-plane anti-ferromagnetic layer, in-plane ferromagnetic layer, nonmagnetic layer, vertical ferromagnetic layer, and vertical anti-ferromagnetic layer respectively from the bottom up; the said in-plane ferromagnetic layer and the said vertical ferromagnetic layer are coupled together through the said nonmagnetic layer in the middle; in-plane exchange biases, namely exchange biases in the plane, exist between the said in-plane ferromagnetic layer and the said in-plane anti-ferromagnetic layer, and out-of-plane exchange biases, namely exchange biases out of the plane, exist between the said vertical ferromagnetic layer and the said vertical anti-ferromagnetic layer.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: March 5, 2024
    Assignee: SHAN DONG UNIVERSITY
    Inventors: Shishen Yan, Yufeng Tian, Lihui Bai, Yibo Fan, Xiang Han
  • Patent number: 11922108
    Abstract: A memory cell array includes a first and a second column of memory cells, a first and a second bit line, a source line and a first set of vias. The first or second bit line includes a first conductive line located on a first metal layer, and a second conductive line located on a second metal layer. The first and second conductive lines overlap a source of a transistor of a memory cell of the first column or second column of memory cells. The source line is coupled to the first and second column of memory cells. The first set of vias is electrically coupled to the first and second conductive line. A pair of vias of the first set of vias is located above where the first conductive line overlaps each memory cell of the first or second column of memory cells.
    Type: Grant
    Filed: October 19, 2021
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Hsiang Weng, Yu-Der Chih
  • Patent number: 11922987
    Abstract: A novel storage device is provided. The storage device includes a first wiring, a second wiring, and a first memory cell. The first memory cell includes a first transistor and a first magnetic tunnel junction device. One of a source or a drain of the first transistor is electrically connected to a first wiring. The other of the source or the drain of the first transistor is electrically connected to one terminal of the first magnetic tunnel junction device. Another terminal of the first magnetic tunnel junction device is electrically connected to the second wiring. The first transistor includes an oxide semiconductor in its channel formation region.
    Type: Grant
    Filed: December 14, 2022
    Date of Patent: March 5, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiaki Oikawa, Atsushi Miyaguchi, Hideki Uochi
  • Patent number: 11917809
    Abstract: Methods, systems, and devices for thin film transistor deck selection in a memory device are described. A memory device may include memory arrays arranged in a stack of decks formed over a substrate, and deck selection components distributed among the layers to leverage common substrate-based circuitry. For example, each memory array of the stack may include a set of digit lines of a corresponding deck, and deck selection circuitry operable to couple the set of digit lines with a column decoder that is shared among multiple decks. To access memory cells of a selected memory array on one deck, the deck selection circuitry corresponding to the memory array may each be activated, while the deck selection circuitry corresponding to a non-selected memory array on another deck may be deactivated. The deck selection circuitry, such as transistors, may leverage thin-film manufacturing techniques, such as various techniques for forming vertical transistors.
    Type: Grant
    Filed: July 13, 2022
    Date of Patent: February 27, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Daniele Vimercati
  • Patent number: 11908501
    Abstract: A storage device includes a first interconnection, a second interconnection, a memory cell connected between the first and second interconnections and including a variable resistance element and a switching element that is connected in series to the variable resistance element, and a control circuit configured to exercise control of a read operation to read data stored in the memory cell. The control circuit exercises control in such a manner as to set the first interconnection which has been charged with a first voltage and the second interconnection which has been charged with a second voltage into floating states, to set the switching element into an on-state by discharging the second interconnection set into the floating state to thereby increase a voltage applied to the memory cell, and to read the data stored in the memory cell in a state in which the switching element is set into the on-state.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: February 20, 2024
    Assignee: Kioxia Corporation
    Inventors: Akira Katayama, Kosuke Hatsuda
  • Patent number: 11907544
    Abstract: Described apparatuses and methods provide automated error correction with memory refresh. Memory devices can include error correction code (ECC) technology to detect or correct one or more bit-errors in data. Dynamic random-access memory (DRAM), including low-power double data rate (LPPDR) synchronous DRAM (SDRAM), performs refresh operations to maintain data stored in a memory array. A refresh operation can be a self-refresh operation or an auto-refresh operation. Described implementations can combine ECC technology with refresh operations to determine a data error with data that is being refreshed or to correct erroneous data that is being refreshed. In an example, data for a read operation is checked for errors. If an error is detected, a corresponding address can be stored. Responsive to the corresponding address being refreshed, corrected data is stored at the corresponding address in conjunction with the refresh operation. Alternatively, data being refreshed can be checked for an error.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: February 20, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Hyun Yoo Lee, Kang-Yong Kim
  • Patent number: 11908515
    Abstract: Provided are a device comprising a bit cell tile including at least two memory cells, each of the at least two memory cells including a resistive memory element, and methods of operating an array of the memory cells, each memory cell including a resistive memory element electrically coupled in series to a corresponding first transistor and to a corresponding second transistor, the first transistor including a first gate coupled to a corresponding one of a plurality of first word lines and the second transistor including a second gate coupled to a corresponding one of a plurality of second word lines, each memory cell coupled between a corresponding one of a plurality of bit lines and a corresponding one of a plurality of source lines. The methods may include applying voltages to the first word line, second word line, source line, and bit line of a memory cell selected for an operation, and resetting the resistive memory element of the memory cell in response to setting the selected bit line to ground.
    Type: Grant
    Filed: January 18, 2023
    Date of Patent: February 20, 2024
    Assignee: Hefei Reliance Memory Limited
    Inventors: Deepak Chandra Sekar, Wayne Frederick Ellis, Brent Steven Haukness, Gary Bela Bronner, Thomas Vogelsang
  • Patent number: 11903327
    Abstract: This spin element includes: a current-carrying part that extends in a first direction; and an element part that is laminated on one surface of the current-carrying part, wherein the current-carrying part includes a first wiring and a second wiring in order from a side of the element part, and wherein both of the first wiring and the second wiring are metals and temperature dependence of resistivity of the first wiring is larger than temperature dependence of resistivity of the second wiring in at least a temperature range of ?40° C. to 100° C.
    Type: Grant
    Filed: November 9, 2022
    Date of Patent: February 13, 2024
    Assignee: TDK CORPORATION
    Inventor: Tomoyuki Sasaki
  • Patent number: 11903326
    Abstract: In some embodiments, the present disclosure relates to a memory device that includes a spin orbit torque (SOT) layer arranged over a substrate. A magnetic tunnel junction (MTJ) structure may be arranged over the SOT layer. The MTJ structure includes a free layer, a reference layer, and a diffusion barrier layer disposed between the free layer and the reference layer. A first conductive wire is arranged below the SOT layer and coupled to the SOT layer. A second conductive wire is arranged below the SOT layer and coupled to the SOT layer. A third conductive wire is arranged over the MTJ structure. The memory device further includes a first selector structure arranged between the first conductive wire and the SOT layer.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: February 13, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming Yuan Song, Shy-Jay Lin
  • Patent number: 11887655
    Abstract: A sense amplifier includes an amplification module and a control module electrically connected to the amplification module. Herein, in a case of reading a data in a memory cell on a first bit line, at an offset compensation stage of the sense amplifier, the control module is arranged to configure the amplification module to include a first diode structure, a first current mirror structure, and a first inverter with an input terminal and an output terminal connected to each other. In a case of reading a data in a memory cell on a second bit line, at the offset compensation stage of the sense amplifier, the control module is arranged to configure the amplification module to include a second diode structure, a second current mirror structure, and a second inverter with an input terminal and an output terminal connected to each other.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: January 30, 2024
    Assignees: ANHUI UNIVERSITY, CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Wenjuan Lu, Junlin Ge, Jun He, Zhan Ying, Xin Li, Kanyu Cao, Chunyu Peng, Zhiting Lin, Xiulong Wu, Junning Chen
  • Patent number: 11881259
    Abstract: A neuromorphic device including an electrode including a first terminal connected to a bit line through a write drive transistor and a second terminal connected to a source line, a plurality of unit weighting elements having different resistance values, each of the unit weighting elements including a free layer arranged on the top of the electrode, a tunnel barrier layer arranged on the top of the free layer, and a fixed layer arranged on the top of the tunnel barrier layer, and corresponding to each bit of a synapse weight, and a plurality of control electrodes connected to the bit line through a plurality of read drive transistors, respectively, a control voltage being applied between the free layer and the fixed layer of each of the plurality of unit weighting elements through each of the plurality of control electrodes.
    Type: Grant
    Filed: April 14, 2022
    Date of Patent: January 23, 2024
    Assignee: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventor: Seung Heon Baek
  • Patent number: 11875835
    Abstract: A memory and a read and write method of memory can prevent the magnetic random-access memory (MRAM) from being easily damaged or degraded by excessive write current during use, and increase memory integration density. The memory includes: a storage unit, comprising a storage element; a source line, electrically connected to a first end of the storage element; the memory is configured to change a storage state of the storage element by a first current and a second current, the first current flowing through the storage element and the second current flowing through the source line without flowing through the storage element.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: January 16, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Baolei Wu, Yulei Wu, Xiaoguang Wang, Erxuan Ping
  • Patent number: 11871585
    Abstract: A semiconductor device includes a sense amplifier, a first magnetic tunneling junction (MTJ) connected to the sense amplifier at a first distance, a second MTJ connected to the sense amplifier at a second distance, and a third MTJ connected to the sense amplifier at a third distance. Preferably, the first distance is less than the second distance, the second distance is less than the third distance, a critical dimension of the first MTJ is less than a critical dimension of the second MTJ, and the critical dimension of the second MTJ is less than a critical dimension of the third MTJ.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: January 9, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Wei Wang, Yi-An Shih, Huan-Chi Ma
  • Patent number: 11868621
    Abstract: A data storage system can employ a read destructive memory configured with multiple levels. A non-volatile memory unit can be programmed with a first logical state in response to a first write voltage of a first hysteresis loop by a write controller prior to being programmed to a second logical state in response to a second write voltage of the first hysteresis loop, as directed by the write controller. The first and second logical states may be present concurrently in the non-volatile memory unit and subsequently read concurrently as the first logical state and the second logical state.
    Type: Grant
    Filed: June 20, 2022
    Date of Patent: January 9, 2024
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Jon D. Trantham, Praveen Viraraghavan, John W. Dykes, Ian J. Gilbert, Sangita Shreedharan Kalarickal, Matthew J. Totin, Mohamad El-Batal, Darshana H. Mehta
  • Patent number: 11869540
    Abstract: According to one embodiment, a magnetic head includes first and second magnetic poles, a stacked body, and first to third terminals. The stacked body is provided between the first and second magnetic poles. The stacked body includes a first magnetic layer, a second magnetic layer between the first magnetic layer and the second magnetic pole, a third magnetic layer between the second magnetic layer and the second magnetic pole, a fourth magnetic layer between the third magnetic layer and the second magnetic pole, a first nonmagnetic layer between the first magnetic pole and the first magnetic layer, a second nonmagnetic layer between the first and second magnetic layers, a third nonmagnetic layer between the second and third magnetic layers, a fourth nonmagnetic layer between the third and fourth magnetic layers and a fifth nonmagnetic layer between the fourth magnetic layer and the second magnetic pole.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: January 9, 2024
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Tazumi Nagasawa, Yuji Nakagawa, Naoyuki Narita, Masayuki Takagishi, Tomoyuki Maeda, Ryo Osamura
  • Patent number: 11871586
    Abstract: A magnetic memory of the present embodiment includes an electrode extending along a plane including a first direction and a second direction, a first wiring extending in the first direction, second wirings between the electrode and the first wiring, extending in the second direction and arranged in the first direction, first magnetic members each including a first part electrically connected to the first wiring and a second part electrically connected to the electrode, extending in a third direction, and being positioned between neighboring two of the second wirings when seen from the third direction, and a control circuit. When writing first information to one first magnetic member, the control circuit supplies first current to at least two second wirings positioned on one side of the one first magnetic member in the first direction.
    Type: Grant
    Filed: March 14, 2022
    Date of Patent: January 9, 2024
    Assignee: Kioxia Corporation
    Inventors: Naoharu Shimomura, Nobuyuki Umetsu, Tsuyoshi Kondo, Yoshihiro Ueda, Yasuaki Ootera, Akihito Yamamoto, Mutsumi Okajima, Masaki Kado, Tsutomo Nakanishi, Michael Arnaud Quinsat
  • Patent number: 11871678
    Abstract: A magnetic memory device includes a first magnetic memory device, a second magnetic memory device, a pulse power supplying current pulses to the first and second magnetic memory devices; and a switch configured to selectively connect the pulse power to one of the first and second magnetic memory devices. A resistance value of an MTJ device composed of the first fixed layer, the first non-magnetic layer, and the free layer is different from a resistance value of a MTJ device composed of the second fixed layer, the second non-magnetic layer, and the free layer.
    Type: Grant
    Filed: January 21, 2022
    Date of Patent: January 9, 2024
    Assignees: Samsung Electronics Co., Ltd., Kansai University, National University Corporation Ehime University
    Inventors: Yoshiaki Sonobe, Syuta Honda, Yasuaki Nakamura, Yoshihiro Okamoto
  • Patent number: 11864468
    Abstract: A magnetoresistive random access memory (MRAM) device includes a first array region and a second array region on a substrate, a first magnetic tunneling junction (MTJ) on the first array region, a first top electrode on the first MTJ, a second MTJ on the second array region, and a second top electrode on the second MTJ. Preferably, the first top electrode and the second top electrode include different nitrogen to titanium (N/Ti) ratios.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: January 2, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Si-Han Tsai, Dong-Ming Wu, Chen-Yi Weng, Ching-Hua Hsu, Ju-Chun Fan, Yi-Yu Lin, Che-Wei Chang, Po-Kai Hsu, Jing-Yin Jhang
  • Patent number: 11854591
    Abstract: The present invention is directed to a nonvolatile memory device that includes one or more memory sectors and a read circuit for sensing the resistance state of a magnetic memory cell in the memory sectors. The read circuit includes first and second input nodes; a sense amplifier having first and second input terminals; a reference resistor connected to the first input node at one end and the first input terminal at the other end; a multiplexer having a first input, a second input, and an output, with the first input being connected to the second input node and the output being connected to the second input terminal; a first target resistor and an offset resistor connected in series between the second input node and the second input; and first and second current sources connected to the first and second input terminals, respectively.
    Type: Grant
    Filed: December 21, 2021
    Date of Patent: December 26, 2023
    Assignee: Avalanche Technology, Inc.
    Inventors: Thinh Tran, Ebrahim Abedifard