Abstract: Disclosed is an electric field-controlled magnetoresistive random-access memory (MRAM) including memory cells. The memory cell has a heterogenous double tunnel junction structure including a first tunnel junction and a second tunnel junction. The first tunnel junction includes a magnetic tunnel junction layer having a magnetization direction that changes according to spin transfer torque when an external voltage is applied, and the second tunnel junction includes an electric-field control layer that controls an electric field applied to the magnetic tunnel junction layer to induce a change in magnetic anisotropy within the magnetic tunnel junction layer. The heterogeneous tunnel junction structure combines electric field-controlled magnetic anisotropy and spin transfer torque to enable low power driving of memory cells, thereby enabling a high energy-efficient electric field-controlled MRAM.

Abstract: A semiconductor device includes an array region defined on a substrate, a ring of dummy pattern surrounding the array region, and a gap between the array region and the ring of dummy pattern. Preferably, the ring of dummy pattern further includes a ring of magnetic tunneling junction (MTJ) pattern surrounding the array region and a ring of metal interconnect pattern overlapping the ring of MTJ and surrounding the array region.

Abstract: A chirality detector of the present invention for detecting chirality of chiral material, includes: a first electrode and a second electrode that are configured to apply a voltage to a subject containing the chiral material; a spin detection layer configured to be in contact with the subject; a power supply; and a control section. The power supply and the control section are configured to generate an electric field at the subject by applying the voltage between the first electrode and the second electrode. The control section is configured to detect a voltage generated in the spin detection layer in a direction that goes across a direction of the electric field or a voltage generated between the spin detection layer and the subject, and also is configured to detect chirality of the chiral material on the basis of the detected voltage.

Abstract: A magnetic tunnel junction (MTJ) is disclosed wherein a free layer (FL) interfaces with a first metal oxide (Mox) layer and second metal oxide (tunnel barrier) to produce perpendicular magnetic anisotropy (PMA) in the FL. In some embodiments, conductive metal channels made of a noble metal are formed in the Mox that is MgO to reduce parasitic resistance. In a second embodiment, a discontinuous MgO layer with a plurality of islands is formed as the Mox layer and a non-magnetic hard mask layer is deposited to fill spaces between adjacent islands and form shorting pathways through the Mox. In another embodiment, end portions between the sides of a center Mox portion and the MTJ sidewall are reduced to form shorting pathways by depositing a reducing metal layer on Mox sidewalls, or performing a reduction process with forming gas, H2, or a reducing species.

Abstract: The present disclosure includes apparatuses and methods for determining soft data. A number of embodiments include determining soft data associated with a data state of a memory cell. In a number of embodiments, the soft data may be determined by performing a single stepped sense operation on the memory cell.

Abstract: A sense amplifier includes a voltage comparator with offset compensation, a first clamping device and a second clamping device. The voltage comparator is coupled to a bit line and a reference bit line respectively, and configured to compare a first input voltage and a second input voltage to output a sensing signal. The first clamping circuit and the second clamping circuit trim a voltage corresponding to the bit line and a voltage corresponding to the reference bit line respectively to match the voltage corresponding to the reference bit line with the voltage corresponding to the bit line.

Abstract: Provided are a non-volatile memory device and a manufacturing method thereof. The non-volatile memory device includes a substrate having a memory region and a dummy region surrounding the memory region, an interconnect structure, memory cells, conductive vias and dummy vias. The interconnect structure is disposed on the substrate and in the memory region. The memory cells are disposed on the interconnect structure and arranged in an array when viewed from a top view. The memory cells include first memory cells in the memory region and second memory cells in the dummy region. The conductive vias are disposed in the memory region and between the first memory cells and the interconnection structure to electrically connect each of the first memory cells to the interconnect structure. The dummy vias are disposed in the dummy region and surround the memory region.

Abstract: Magnetic memory structure and memory device are provided. A magnetic memory structure includes a metal layer, a first magnetic tunnel junction, and a second magnetic tunnel junction. The metal layer includes a first contact region and a second contact region. Electrical resistivity of at least a first part of the first contact region is different than electrical resistivity of the second contact region. The first magnetic tunnel junction is disposed on the metal layer. The first magnetic tunnel junction includes a first free layer in contact with the first contact region of the metal layer. The second magnetic tunnel junction is disposed on the metal layer. The second magnetic tunnel junction includes a second free layer in contact with the second contact region of the metal layer.

Abstract: A perpendicular magnetic tunnel junction is disclosed wherein a metal insertion (MIS) layer is formed within a free layer (FL), a partially oxidized Hk enhancing layer is on the FL, and a nitride capping layer having a buffer layer/nitride layer (NL) is on the Hk enhancing layer to provide an improved coercivity (Hc)/switching current (Jc) ratio for spintronic applications. Magnetoresistive ratio is maintained above 100%, resistance×area (RA) product is below 5 ohm/?m2, and thermal stability to 400° C. is realized. The FL comprises two or more sub-layers, and the MIS layer may be formed within at least one sub-layer or between sub-layers. The buffer layer is used to prevent oxygen diffusion to the NL, and nitrogen diffusion from the NL to the FL. FL thickness is from 11 Angstroms to 25 Angstroms while MIS layer thickness is preferably from 0.5 Angstroms to 4 Angstroms.

Abstract: A memory includes first lines arrayed along a surface of a substrate. Second lines are arrayed along the surface of the substrate either above or below the first lines and intersecting with the first lines. Resistance change memory cells are provided to correspond to intersection regions between the first lines and the second lines, respectively. First switching elements are arranged on a side of first ends of the first lines and transmitting a first voltage for writing or reading data to at least one memory cell among the memory cells. Second switching elements are arranged on a side of second ends of the first lines on an opposite side to the first ends and transmitting the first voltage to at least another one memory cell among the memory cells. The first switching elements and the second switching elements are connected to different ones of the first lines, respectively.

Abstract: A magnetic field controlled transistor circuit includes a first electrode, a second electrode, and a channel including a magneto-resistive material. The channel is arranged between the first and second electrodes and electrically coupled to the first and second electrodes. The transistor circuit further includes a third electrode, a fourth electrode, and a control layer including an electrically conductive material. The control layer is arranged between the third and fourth electrodes and electrically coupled to the third and fourth electrodes. In addition, an insulating layer including an insulating material is provided. The insulating layer is arranged between the channel and the control layer and configured to electrically insulate the channel from the control layer. A related method for operating a transistor circuit and a corresponding design structure are also provided.

Abstract: Methods for programming memory cells of a resistive memory device include applying a voltage pulse sequence to a memory cell to set a logic state of the memory cell. An initial set sequence of voltage pulses may be applied to the memory cell, followed by a reform voltage pulse having an amplitude greater than the amplitudes of the initial set sequence, and within ±5% of the amplitude of a voltage pulse used in an initial forming process. Additional voltage pulses having amplitudes that are less than the amplitude of the reform voltage pulse may be subsequently applied. By applying a reform voltage pulse in the middle of, or at the end of, a memory set sequence including multiple voltage pulses, a resistive memory device may have a larger memory window and improved data retention relative to resistive memory devices programmed using conventional programming methods.

Abstract: One aspect of this description relates to a memory array. The memory array includes a plurality of N-stack pass gates, a plurality of enable lines, a plurality of NMOS stacks, a plurality of word lines, and a matrix of resistive elements. Each N-stack pass gate includes a stage-1 PMOS core device and a stage-N PMOS core device in series. Each stage-1 PMOS is coupled to a voltage supply. Each enable line drives a stack pass gate. Each N-stack selector includes a plurality of NMOS stacks. Each NMOS stack includes a stage-1 NMOS core device and a stage-N N MOS core device in series. Each stage-1 NMOS core device is coupled to a ground rail. Each word line is driving a stack selector. Each resistive element is coupled between a stack pass gate and a stack selector. Each voltage supply is greater than a breakdown voltage for each of the core devices.

Abstract: A magnetic storage device includes a magnetic body including first and second magnetic regions and a magnetic connection region that connects the first and second magnetic regions, and in which a plurality of magnetic domains each storing information by a magnetization direction thereof is formed, a read element that is electrically connected to the magnetic connection region and by which a magnetization direction of one of the magnetic domains is read, and a write element by which a magnetic domain having a magnetization direction is formed in the magnetic body according to information to be stored. The magnetic domains formed in each of the first and second magnetic regions are shifted in a predetermined direction in response to current that flows through the corresponding one of the first and second magnetic regions.

Abstract: A method of manufacturing an MRAM device, the method including forming a first magnetic layer on a substrate; forming a first tunnel barrier layer on the first magnetic layer such that the first tunnel barrier layer includes a first metal oxide, the first metal oxide being formed by oxidizing a first metal layer at a first temperature; forming a second tunnel barrier layer on the first tunnel barrier layer such that the second tunnel barrier layer includes a second metal oxide, the second metal oxide being formed by oxidizing a second metal layer at a second temperature that is greater than the first temperature; and forming a second magnetic layer on the second tunnel barrier layer.

Abstract: An integrated circuit includes a latch array including a plurality of latches logically configured in rows and columns, a plurality of repair latches operatively coupled to the plurality of latches and latch array built in self-test and repair logic (LABISTRL) coupled to the plurality of latches. In some implementations the LABISTRL configures latches in the array as one or more column serial test shift register, detects one or more defective latches of the plurality of latches based on applied test data, and selects at least one repair latch in response to detection of at least one defective latch.

Abstract: The present disclosure is drawn to a magnetoresistive device including an array of memory cells arranged in rows and columns, each memory cell comprising a magnetic tunnel junction, each row comprising a word line, and each column comprising a bit line; a column select device that selects a bit line. The magnetoresistive device also includes a sense amplifier comprising a first input corresponding to a selected bit line, a second input corresponding to a reference bit line, and a data output. The plurality of columns comprise a reference column, the reference column comprising a conductive element coupled to the magnetic tunnel junctions in the reference column.

Abstract: Various devices are described (along with methods for making them), where the device has a tunnel barrier sandwiched between two magnetic layers (one of the magnetic layers functioning as a free layer and the other of the magnetic layers functioning as a reference layer). One magnetic layer underlies the tunnel barrier and the other magnetic layer overlies the tunnel barrier, thereby permitting spin-polarized current to pass across the magnetic layers and through the tunnel barrier. At least one of the magnetic layers includes a metal oxide sublayer (e.g., an MgO sublayer) sandwiched between magnetic material.

Abstract: Numerous embodiments of circuitry for a set-while-verify operation and a reset-while verify operation for resistive random access memory cells are disclosed. In one embodiment, a set-while-verify circuit for performing a set operation on a selected RRAM cell in the array applies a combination of voltages or current to a bit line, word line, and source line associated with the selected RRAM cell and stops said applying when the set operation is complete. In another embodiment, a reset-while-verify circuit for performing a reset operation on a selected RRAM cell in the array applies a combination of voltages or current to a bit line, word line, and source line associated with the selected RRAM cell and stops said applying when the reset operation is complete.

Abstract: Disclosed herein are related to a memory cell including one or more programmable resistors and a control transistor. In one aspect, a programmable resistor includes a gate structure and one or more source/drain structures for forming a transistor. A resistance of the programmable resistor may be set by applying a voltage to the gate structure, while the control transistor is enabled. Data stored by the programmable resistor can be read by sensing current through the programmable resistor, while the control transistor is disabled. In one aspect, the one or more programmable resistors and the control transistor are implemented by same type of components, allowing the memory cell to be formed in a compact manner through a simplified the fabrication process.

Abstract: A method of programming a resistive memory device, and a corresponding resistive memory device, which includes the resistive memory device, in response to a write command, applying a write pulse to a selected memory cell arranged in a region where a selected word line intersects with a selected bit line; and after the applying the write pulse, applying a dummy pulse to at least one unselected memory cell. The at least one unselected memory cell is connected to at least one of the selected word line, the selected bit line, a first word line adjacent to the selected word line, and a first bit line adjacent to the selected bit line.

Abstract: This spin current magnetization rotational type magnetoresistive element includes a magnetoresistive effect element having a first ferromagnetic metal layer having a fixed magnetization orientation, a second ferromagnetic metal layer having a variable magnetization orientation, and a non-magnetic layer sandwiched between the first ferromagnetic metal layer and the second ferromagnetic metal layer, and spin-orbit torque wiring which extends in a direction that intersects the stacking direction of the magnetoresistive effect element, and is connected to the second ferromagnetic metal layer, wherein the electric current that flows through the magnetoresistive effect element and the electric current that flows through the spin-orbit torque wiring merge or are distributed in the portion where the magnetoresistive effect element and the spin-orbit torque wiring are connected.

Abstract: The present disclosure is drawn to, among other things, a magnetoresistive device and a magnetoresistive memory comprising a plurality of such magnetoresistive devices. In some aspects, a magnetoresistive device may include a magnetically fixed region, a magnetically free region above or below the magnetically fixed region, and an intermediate region positioned between the magnetically fixed region and the magnetically free region, wherein the intermediate region includes a first dielectric material. The magnetoresistive device may also include encapsulation layers formed on opposing side walls of the magnetically free region, wherein the encapsulation layers include the first dielectric material.

Abstract: A spin-orbit torque magnetoresistance effect element according to the present embodiment includes an element part including a first ferromagnetic layer, a second ferromagnetic layer, and a nonmagnetic layer positioned between the first ferromagnetic layer and the second ferromagnetic layer, a spin-orbit torque wiring positioned in a first direction with respect to the element part, facing the first ferromagnetic layer of the element part, and extending in a second direction, a first conductive part and a second conductive part facing the spin-orbit torque wiring at positions sandwiching the element part when viewed from the first direction, and a gate part positioned between the first conductive part and the second conductive part when viewed from the first direction, facing a second surface of the spin-orbit torque wiring on a side opposite to a first surface which faces the element part, and including a gate insulating layer and a gate electrode in order from a position near the spin-orbit torque wiring, in

Abstract: The energy consumed by data transfer in a computing device may be reduced by transferring data that has been encoded in a manner that reduces the number of one “1” data values, the number of signal level transitions, or both. A data destination component of the computing device may receive data encoded in such a manner from a data source component of the computing device over a data communication interconnect, such as an off-chip interconnect. The data may be encoded using minimum Hamming weight encoding, which reduces the number of one “1” data values. The received data may be decoded using minimum Hamming weight decoding. For other computing devices, the data may be encoded using maximum Hamming weight encoding, which increases the number of one “1” data values while reducing the number of zero “0” values, if reducing the number of zero values reduces energy consumption.

Abstract: In one aspect, a linear sensor includes at least one magnetoresistance element that includes a first spin valve and a second spin valve positioned on the first spin valve. The first spin valve includes a first set of reference layers having a magnetization direction in a first direction and a first set of free layers having a magnetization direction in a second direction orthogonal to the first direction. The second spin valve includes a second set of reference layers having a magnetization direction in the first direction and a second set of free layers having a magnetization direction in a third direction orthogonal to the first direction and antiparallel to the second direction. The first direction is neither parallel nor antiparallel to a direction of an expected magnetic field.

Abstract: A storage device performs a read operation by restoring an ON cell count (OCC) from a power loss protection (PLP) area of a nonvolatile memory. The nonvolatile memory includes a memory blocks, a buffer memory and a controller. The buffer memory stores a first ON cell count (OCC1) indicating a number of memory cells turned ON by a first read voltage and a second ON cell count (OCC2) indicating a number of memory cells turned ON by a second read voltage among the memory cells connected to a reference word line. The controller stores the OCC1 for each of the memory blocks in the PLP area when a sudden power off occurs in the storage device.

Abstract: A semiconductor device for internet of things (IoT) device includes a substrate having an array region defined thereon and a ring of dummy pattern surrounding the array region. Preferably, the ring of dummy pattern includes a plurality of magnetic tunneling junctions (MTJs) and a ring of metal interconnect pattern overlapping the MTJs and surrounding the array region. The semiconductor device further includes a gap between the array region and the ring of dummy pattern.

Abstract: A method of controlling a trajectory of a perpendicular magnetization switching of a ferromagnetic layer using spin-orbit torques in the absence of any external magnetic field includes: injecting a charge current Je through a heavy-metal thin film disposed adjacent to a ferromagnetic layer to produce spin torques which drive a magnetization M out of an equilibrium state towards an in-plane of a nanomagnet; turning the charge current Je off after te seconds, where an effective field experienced by the magnetization of the ferromagnetic layer Heff is significantly dominated by and in-plane anisotropy Hkx, and where M passes a hard axis by precessing around the Heff; and passing the hard axis, where Heff is dominated by a perpendicular-to-the-plane anisotropy Hkz, and where M is pulled towards the new equilibrium state by precessing and damping around Heff, completing a magnetization switching.

Abstract: A spin element includes an element portion including a first ferromagnetic layer, a conducting portion that extends in a first direction as viewed in a lamination direction of the first ferromagnetic layer and faces the first ferromagnetic layer, and a current path extending from the conducting portion to a semiconductor circuit and having a resistance adjusting portion between the conducting portion and the semiconductor circuit, wherein the resistance value of the resistance adjusting portion is higher than the resistance value of the conducting portion, and the temperature coefficient of the volume resistivity of a material forming the resistance adjusting portion is lower than the temperature coefficient of the volume resistivity of a material forming the conducting portion.

Abstract: A method for compensating for external magnetic fields in memory devices that includes positioning at least one external magnetic field sensing element adjacent to at least one array of memory cells, wherein a write driver is in electrical communication with at least one external magnetic field sensing element and at least one array of memory cells. The at least one external magnetic field sensing element is monitored for signals indicative of the present of an external magnetic field. The write current to the at least one array of memory cells can be adjusted by trimming the write driver to operate the memory device while compensating for the external magnetic field.

Abstract: The present disclosure relates to inductor structures and fabricating methods. One example inductor structure includes a first magnetic material layer, an insulation layer, where the insulation layer comprises a polymer structure with longitudinal length which greater than lateral length, the polymer structure comprises an arched upper surface, a first side surface, a second side surface, a bottom surface in a longitudinal direction, at least one of a corner between the arched upper surface and the first side surface and a corner between the arched upper surface and the second side surface is a rounded corner, and at least one of an angle formed between the first side surface and the bottom surface and an angle formed between the second side surface and the bottom surface is less than 90 degree, at least one conductive wire structure passing through the insulation layer, and a second magnetic material layer.

Abstract: A circuit includes an array of OTP cells, an array of NVM cells, an amplifier coupled to each of the array of OTP cells and the array of NVM cells, and a control circuit configured to generate one or more control signals. Responsive to the one or more control signals, the amplifier is configured to generate an output voltage based on a current received from the array of OTP cells in a first configuration, and generate the output voltage based on a voltage received from the array of NVM cells in a second configuration.

Abstract: This spin current magnetization rotational type magnetoresistive element includes a magnetoresistive effect element having a first ferromagnetic metal layer having a fixed magnetization orientation, a second ferromagnetic metal layer having a variable magnetization orientation, and a non-magnetic layer sandwiched between the first ferromagnetic metal layer and the second ferromagnetic metal layer, and spin-orbit torque wiring which extends in a direction that intersects the stacking direction of the magnetoresistive effect element, and is connected to the second ferromagnetic metal layer, wherein the electric current that flows through the magnetoresistive effect element and the electric current that flows through the spin-orbit torque wiring merge or are distributed in the portion where the magnetoresistive effect element and the spin-orbit torque wiring are connected.

Abstract: A magnetic memory according to an embodiment includes: a first wiring and a second wiring; a first magnetic member having a first portion electrically connected to the first wiring and a second portion electrically connected to the second wiring, the first magnetic member extending in a first direction from the first portion to the second portion; a third wiring that is electrically insulated from the first magnetic member; and a control circuit electrically connected to the first wiring, the second wiring, and the third wiring, the control circuit supplying a current pulse, in which a trailing time is longer than a rising time, to the third wiring.

Abstract: Amorphous multi-component metallic films can be used to improve the performance of electronic components such as resistors, diodes, and thin film transistors. Interfacial properties of AMMFs are superior to those of crystalline metal films, and therefore electric fields at the interface of an AMMF and an oxide film are more uniform. An AMMF resistor (AMNR) can be constructed as a three-layer structure including an amorphous metal, a tunneling insulator, and a crystalline metal layer. By modifying the order of the materials, the patterns of the electrodes, and the size and number of overlap areas, the I-V performance characteristics of the AMNR are adjusted. A non-coplanar AMNR has a five-layer structure that includes three metal layers separated by metal oxide tunneling insulator layers, wherein an amorphous metal thin film material is used to fabricate the middle electrodes.

Abstract: A neural network computation circuit that outputs output data according to a result of a multiply-accumulate operation between input data and connection weight coefficients, the neural network computation circuit includes computation units in each of which a non-volatile semiconductor memory element and a cell transistor are connected in series between data lines, a non-volatile semiconductor memory element and a cell transistor are connected in series between data lines, and gates of the transistors are connected to word lines. The connection weight coefficients are stored into the non-volatile semiconductor memory elements. A word line selection circuit places the word lines in a selection state or a non-selection state according to the input data. A determination circuit determines current values flowing in data lines to output output data.

Abstract: A metamagnetic tunneling-based spin valve device for multistate magnetic memory comprising an electronic memory logic element with four stable resistance states. A metamagnetic tunneling-based spin valve device for multistate magnetic memory comprising a layer of a metamagnetic material, a layer of a nonmagnetic material on the layer of a metamagnetic material, and a layer of a ferromagnetic material on the layer of a nonmagnetic material. A method of making a metamagnetic tunneling-based spin valve device for multistate magnetic memory.

Abstract: A magnetic domain device is provided in which a magnetic free layer (i.e., the storage layer) of a magnetic tunnel junction (MTJ) pillar is in close proximity to a conductive write line that is disposed beneath the MTJ pillar. The magnetic domain device further includes a pair of spaced apart bottom electrodes located beneath the conductive write line, and a top electrode located on the MTJ pillar. The magnetic domain device can be used in analog memories including multi-bit storage, analog memory for artificial intelligence (AI) applications.

Abstract: A machine learning system and method. The machine learning system includes at least one computation circuit that performs a weighted summation of incoming signals and provides a resulting signal. The weighted summation is carried out at least in part by a magnetic element in which weights are adjusted based on changes in effective magnetic susceptibility of the magnetic element.

Abstract: An apparatus for performing in-memory processing includes a memory cell array of memory cells configured to output a current sum of a column current flowing in respective column lines of the memory cell array based on an input signal applied to row lines of the memory cells, a sampling circuit, comprising a capacitor connected to each of the column lines, configured to be charged by a sampling voltage of a corresponding current sum of the column lines, and a processing circuit configured to compare a reference voltage and a currently charged voltage in the capacitor in response to a trigger pulse generated at a timing corresponding to a quantization level, among quantization levels, time-sectioned based on a charge time of the capacitor, and determine the quantization level corresponding to the sampling voltage by performing time-digital conversion when the currently charged voltage reaches the reference voltage.

Abstract: A synapse memory and a method for reading a weight value stored in a synapse memory are provided. The synapse memory includes a memory device configured to store a weight value. The memory device includes a read terminal, a write terminal, and a common terminal, the read terminal being configured to receive a read signal, the write terminal being configured to receive a write signal, and the common terminal being configured to output an output signal from the memory device. The synapse memory also includes a write transistor provided between the write terminal of the memory device and a write signal line configured to send the write signal. The synapse memory further includes a common transistor provided between the common terminal of the memory device and one of the dendrite lines.

Abstract: A magnetic memory device may include a perpendicular magnetic structure, an in-plane magnetic structure, a free magnetic pattern between the perpendicular magnetic structure and the in-plane magnetic structure, and a tunnel barrier pattern between the perpendicular magnetic structure and the free magnetic pattern. The perpendicular magnetic structure may include at least one pinned pattern which has a perpendicular magnetization direction that is pinned to a specific direction, and the free magnetic pattern may have a switchable perpendicular magnetization direction. The in-plane magnetic structure may include a first magnetic pattern and a second magnetic pattern, and each of the first and second magnetic patterns may have a different respective in-plane magnetization direction.

Abstract: A resistive random access memory includes a memory cell including a resistive element having a resistance which varies according to a write operation and stores data according to the resistance of the resistive element, a reference resistive element having a resistance set to a first value, a voltage line set to a first voltage during a first write operation in which the resistance of the resistive element is varied from a second value higher than the first value to the first value, and a voltage control circuit arranged between first ends of the two resistive elements. The voltage control circuit adjusts a value of the first voltage supplied from the voltage line so as to reduce a difference between currents flowing through the two resistive elements during the first write operation, and supply the adjusted first voltage to the first ends of the two resistive elements.

Abstract: A semiconductor device that writes data to, instead of a defective memory cell, another memory cell is provided. The semiconductor device includes a first circuit and a second circuit over the first circuit; the first circuit corresponds to a memory portion and includes a memory cell and a redundant memory cell; a second circuit corresponds to a control portion and includes a third circuit and a fourth circuit. The memory cell is electrically connected to the third circuit, the redundant memory cell is electrically connected to the third circuit, and the third circuit is electrically connected to the fourth circuit.

Abstract: An integrated circuit is disclosed. The integrated circuit includes a transistor, a first fuse element and a second fuse element. The transistor is formed in a first conductive layer. The first fuse element is formed in a second conductive layer disposed above the first conductive layer. The second fuse element is formed in the second conductive layer and is coupled to the first fuse element. The transistor is coupled through the first fuse element to a first data line for receiving a first data signal, and the transistor is coupled through the second fuse element to a second data line for receiving a second data signal. A method of fabricating an integrated circuit (IC) is also disclosed herein.

Abstract: There is provided a magnetoresistance effect element includes: a channel layer that extends in a first direction; a recording layer which includes a film formed from a ferromagnetic material, of which a magnetization state is changed to one of two or greater magnetization states, and which is formed on the channel layer; a non-magnetic layer that is provided on a surface of the recording layer; a reference layer which is provided on a surface of the non-magnetic layer, which includes a film formed from a ferromagnetic material, and of which a magnetization direction is fixed; a terminal pair that includes a first terminal and a second terminal which are electrically connected to the channel layer with an interval in the first direction, and to which a current pulse for bringing the recording layer to any one magnetization state with a plurality of pulses is input by flowing a current to the channel layer between the first terminal and the second terminal; and a third terminal that is electrically connected to

Abstract: A circuit may include a memory cell. The memory cell may include a first memory element, a second memory element, a first transistor, and a second transistor. The first memory element may be connected to a bit line. The second memory element may be connected to a select line. The first transistor may be connected to a first word line. The second transistor may be connected to a second word line. The first memory element may be programmed by applying a first write voltage to the bit line, applying a second write voltage to the second word line, applying a first intermediate voltage to the select line, and applying a second intermediate voltage to the first word line. The select line may be connected to a high impedance. The first write voltage may be a positive supply voltage, the second write voltage may be a negative supply voltage.

Abstract: In some examples, a device includes a magnetic tunnel junction including a first Weyl semimetal layer, a second Weyl semimetal layer, and a dielectric layer positioned between the first and second Weyl semimetal layers. The magnetic tunnel junction may have a large tunnel magnetoresistance ratio, which may be greater than five hundred percent or even greater than one thousand percent.

Abstract: Various embodiments of the present disclosure are directed towards a memory device. The memory device has a first transistor having a first source/drain and a second source/drain, where the first source/drain and the second source/drain are disposed in a semiconductor substrate. A dielectric structure is disposed over the semiconductor substrate. A first memory cell is disposed in the dielectric structure and over the semiconductor substrate, where the first memory cell has a first electrode and a second electrode, where the first electrode of the first memory cell is electrically coupled to the first source/drain of the first transistor. A second memory cell is disposed in the dielectric structure and over the semiconductor substrate, where the second memory cell has a first electrode and a second electrode, where the first electrode of the second memory cell is electrically coupled to the second source/drain of the first transistor.