Josephson Patents (Class 365/162)
  • Patent number: 9699266
    Abstract: A computer system employs a network that between a data programming system and one or more superconducting programmable devices of a superconducting processor chip. Routers on the network, such as first-, second- and third-stage routers direct communications with the superconducting programmable devices. A superconducting memory register may load data signals received from a first-stage router into corresponding superconducting programmable devices. The system may employ additional superconducting chips, first-, second- or third-stage routers.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: July 4, 2017
    Assignee: D-Wave System Inc.
    Inventors: Geordie Rose, Paul I. Bunyk
  • Patent number: 9397283
    Abstract: A method for fabricating a chip surface base includes preparing a first substrate, preparing a plurality of vias in the first substrate, depositing metal fillings into the plurality of vias, preparing a second substrate, bonding the first and second substrates and exposing the metal fillings. A method for fabricating a chip surface base includes preparing a first and second substrate, depositing a metal on at least one of the first and second substrates, bonding the first and second substrates, preparing a plurality of vias in the first substrate, depositing metal fillings into the plurality of vias and exposing the metal fillings. A chip surface base device includes a first substrate, a second substrate, a metal layer disposed between the first and second substrates and a plurality of vias disposed on the first substrate.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: July 19, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David W. Abraham, George A. Keefe, Christian Lavoie, Mary E. Rothwell
  • Patent number: 9385159
    Abstract: A device includes at least one superconducting tunnel junction having a junction region comprising a junction barrier material responsive to electromagnetic fields within the MHz to THz range. The junction may be contained within a bi-SQUID loop having two main junctions and a center junction. The junction barrier material for the main junctions may have different electromagnetic-responsive properties than the junction barrier material for the center junction. The junction barrier material may include type-I multiferroics, type-II multiferroics, a composite multiferroic including layers of magnets and ferroelectrics, or piezoelectric materials. An array of connected bi-SQUID loops may be formed, where the main junctions of each bi-SQUID loop in each row are connected. The electromagnetic-responsive properties of the junction barrier material for center junctions of each bi-SQUID loop may vary by each array column or row. The center/main junctions of each bi-SQUID loop may be connected to an input signal line.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: July 5, 2016
    Assignee: The United States of America as represented by the Sercretary of the Navy
    Inventor: Benjamin J. Taylor
  • Publication number: 20150111754
    Abstract: A quantum processor is operable as a universal adiabatic quantum computing system. The quantum processor includes physical qubits, with at least a first and second communicative coupling available between pairs of qubits via an in-situ tunable superconducting capacitive coupler and an in-situ tunable superconducting inductive coupler, respectively. Tunable couplers provide diagonal and off-diagonal coupling. Compound Josephson junctions (CJJs) of the tunable couplers are responsive to a flux bias to tune a sign and magnitude of a sum of a capacitance of a fixed capacitor and a tunable capacitance which is mediated across a pair of coupling capacitors. The qubits may be hybrid qubits, operable in a flux regime or a charge regime. Qubits may include a pair of CJJs that interrupt a loop of material and which are separated by an island of superconducting material which is voltage biased with respect to a qubit body.
    Type: Application
    Filed: October 21, 2014
    Publication date: April 23, 2015
    Inventors: Richard G. Harris, Mohammad H.S. Amin, Anatoly Smirnov
  • Patent number: 9013916
    Abstract: One aspect of the present invention includes a Josephson magnetic memory system. The system includes a superconducting electrode that conducts a read current. The system also includes a hysteretic magnetic Josephson junction (HMJJ). The HMJJ can store a binary value and convert superconducting pairs associated with the read current flowing through the HMJJ from a singlet-state to a triplet-state. The system further includes a write circuit magnetically coupled to the HMJJ and configured to write the binary value into the at HMJJ in response to at least one write current and a read circuit configured to determine the binary value stored in the HMJJ in response to application of the read current to the HMJJ.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: April 21, 2015
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Ofer Naaman, Donald L. Miller, Anna Y. Herr, Norman O. Birge
  • Publication number: 20150094207
    Abstract: One embodiment describes a memory cell. The memory cell includes a phase hysteretic magnetic Josephson junction (PHMJJ) that is configured to store one of a first binary logic state corresponding to a binary logic-1 state and a second binary logic state corresponding to a binary logic-0 state in response to a write current and to generate a superconducting phase based on the stored digital state. The memory cell also includes at least one Josephson junction having a critical current that is based on the superconducting phase of the PHMJJ and being configured to provide an output corresponding to the stored digital state in response to a read current.
    Type: Application
    Filed: October 1, 2013
    Publication date: April 2, 2015
    Applicant: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Anna Y. Herr, Quentin P. Herr, Ofer Naaman
  • Patent number: 8971977
    Abstract: A superconducting memory cell includes a magnetic Josephson junction (MJJ) with a ferromagnetic material, having at least two switchable states of magnetization. The binary state of the MJJ manifests itself as a pulse appearing, or not appearing, on the output. A superconducting memory includes an array of memory cells. Each memory cell includes a comparator with at least one MJJ. Selected X and Y-directional write lines in their combination are capable of switching the magnetization of the MJJ. A superconducting device includes a first and a second junction in a stacked configuration. The first junction has an insulating layer barrier, and the second junction has an insulating layer sandwiched in-between two ferromagnetic layers as barrier. An electrical signal inputted across the first junction is amplified across the second junction.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: March 3, 2015
    Assignee: Hypres, Inc.
    Inventors: Oleg A. Mukhanov, Alan M. Kadin, Ivan P. Nevirkovets, Igor V. Vernik
  • Publication number: 20150043273
    Abstract: One aspect of the present invention includes a Josephson magnetic memory system. The system includes a superconducting electrode that conducts a read current. The system also includes a hysteretic magnetic Josephson junction (HMJJ). The HMJJ can store a binary value and convert superconducting pairs associated with the read current flowing through the HMJJ from a singlet-state to a triplet-state. The system further includes a write circuit magnetically coupled to the HMJJ and configured to write the binary value into the at HMJJ in response to at least one write current and a read circuit configured to determine the binary value stored in the HMJJ in response to application of the read current to the HMJJ.
    Type: Application
    Filed: May 31, 2012
    Publication date: February 12, 2015
    Inventors: OFER NAAMAN, DONALD L. MILLER, ANNA Y. HERR, NORMAN O. BIRGE
  • Patent number: 8755220
    Abstract: In one embodiment, the invention is a hybrid superconducting-magnetic memory cell and array. One embodiment of a memory cell includes a magnetoresistive element and at least one superconducting element wired in parallel with the magnetoresistive element. In a further embodiment, memory cells of the disclosed configuration are arranged to form a memory array.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: June 17, 2014
    Assignee: International Business Machines Corporation
    Inventors: John F. Bulzacchelli, William J. Gallagher, Mark B. Ketchen
  • Patent number: 8654578
    Abstract: Methods and apparatuses are provided for storing a quantum bit. One apparatus includes a first phase qubit, a second phase qubit, and a common bias circuit configured to provide a first bias to the first phase qubit and a second bias to the second phase qubit, such that noise within the first bias is anti-correlated to noise within the second bias.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: February 18, 2014
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Rupert M. Lewis, Ofer Naaman
  • Patent number: 8611974
    Abstract: A switching cell for a demultiplexer circuit includes a superconducting input signal path, at least two superconducting output signal paths, and transformers located between an intersection node and respective ends of the output signal paths. Flux applied via the transformers can influence which direction a signal propagates. The switching cell may also include power input nodes. Switching cells may be arranged in various configurations, for example a binary tree or H-tree. A superconducting inductor ladder circuit can perform a digital-to-analog conversion. Flux storage structures may be used with individual switching cells. Latching qubits may be employed. Buffer rows of switching cells may be used to reduce or eliminate cascade error.
    Type: Grant
    Filed: June 2, 2009
    Date of Patent: December 17, 2013
    Assignee: D-Wave Systems Inc.
    Inventors: Felix Maibaum, Paul I. Bunyk, Thomas Mahon
  • Patent number: 8553451
    Abstract: Techniques are provided for programming a spin torque transfer magnetic random access memory (STT-MRAM) cell using a unidirectional and/or symmetrical programming current. A unidirectional programming current flows through the free region of the STT-MRAM cell in one direction to switch the magnetization of the free region in at least two different directions. A symmetrical programming current switches the magnetization of the free region to either of the two different directions using a substantially similar current magnitude. In some embodiments, the STT-MRAM cell includes two fixed regions, each having fixed magnetizations in opposite directions and a free region configured to be switched in magnetization to be either parallel with or antiparallel to the magnetization of one of the fixed regions. Switching the free region to different magnetization directions may involve directing the programming current through one of the two oppositely magnetized fixed regions.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: October 8, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Jun Liu
  • Patent number: 8547732
    Abstract: In one embodiment, the invention is a hybrid superconducting-magnetic memory cell and array. One embodiment of a memory cell includes a magnetoresistive element and at least one superconducting element wired in parallel with the magnetoresistive element. In a further embodiment, memory cells of the disclosed configuration are arranged to form a memory array.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: October 1, 2013
    Assignee: International Business Machines Corporation
    Inventors: John F Bulzacchelli, William J Gallagher, Mark B Ketchen
  • Publication number: 20130107617
    Abstract: A quantum memory component including a quantum dot molecule having first and second quantum dots provided in respective first and second layers separated by a barrier layer; an exciton comprising an electron and hole bound state in said quantum dot molecule, the spin state of said exciton forming a qubit; first and second electrical contacts respectively provided below the first quantum dot and above the second quantum dot; a voltage source to apply an electric field across said quantum dot molecule; a controller to modulate the electric field across the quantum dot molecule, including an information acquiring circuit to acquire information concerning the relationship between fine structure splitting of the exciton and the applied electric field and a timing circuit to allow switching of the exciton from an indirect configuration to a direct configuration at predetermined times derived from the fine structure splitting.
    Type: Application
    Filed: July 30, 2012
    Publication date: May 2, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Niklas Adam Bilbo Skold, Anthony John Bennett, Andrew James Shields
  • Publication number: 20120320668
    Abstract: Methods and apparatuses are provided for storing a quantum bit. One apparatus includes a first phase qubit, a second phase qubit, and a common bias circuit configured to provide a first bias to the first phase qubit and a second bias to the second phase qubit, such that noise within the first bias is anti-correlated to noise within the second bias.
    Type: Application
    Filed: June 17, 2011
    Publication date: December 20, 2012
    Inventors: Rupert M. Lewis, Ofer Naaman
  • Patent number: 8270209
    Abstract: One aspect of the present invention includes a Josephson magnetic random access memory (JMRAM) system. The system includes an array of memory cells arranged in rows and columns. Each of the memory cells includes an HMJJD that is configured to store a digital state corresponding to one of a binary logic-1 state and a binary logic-0 state in response to a word-write current that is provided on a word-write line and a bit-write current that is provided on a bit-write line. The HMJJD is also configured to output the respective digital state in response to a word-read current that is provided on a word-read line and a bit-read current that is provided on a bit-read line.
    Type: Grant
    Filed: April 30, 2010
    Date of Patent: September 18, 2012
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Anna Y. Herr, Quentin P. Herr
  • Publication number: 20120184445
    Abstract: A superconducting memory cell includes a magnetic Josephson junction (MJJ) with a ferromagnetic material, having at least two switchable states of magnetization. The binary state of the MJJ manifests itself as a pulse appearing, or not appearing, on the output. A superconducting memory includes an array of memory cells. Each memory cell includes a comparator with at least one MJJ. Selected X and Y-directional write lines in their combination are capable of switching the magnetization of the MJJ. A superconducting device includes a first and a second junction in a stacked configuration. The first junction has an insulating layer barrier, and the second junction has an insulating layer sandwiched in-between two ferromagnetic layers as barrier. An electrical signal inputted across the first junction is amplified across the second junction.
    Type: Application
    Filed: January 13, 2012
    Publication date: July 19, 2012
    Applicant: HYPRES, INC.
    Inventors: Oleg A. Mukhanov, Alan M. Kadin, Ivan P. Nevirkovets, Igor V. Vernik
  • Patent number: 8208288
    Abstract: In one embodiment, the invention is a hybrid superconducting-magnetic memory cell and array. One embodiment of a memory cell includes a magnetoresistive element and at least one superconducting element wired in parallel with the magnetoresistive element. In a further embodiment, memory cells of the disclosed configuration are arranged to form a memory array.
    Type: Grant
    Filed: March 27, 2008
    Date of Patent: June 26, 2012
    Assignee: International Business Machines Corporation
    Inventors: John F. Bulzacchelli, William J. Gallagher, Mark B. Ketchen
  • Patent number: 8200304
    Abstract: A novel Josephson junction and a novel Josephson junction device are provided which eliminates the need to form an insulating barrier layer. The Josephson junction (1) comprises a superconductor layer (2) and a ferromagnetic layer (3) formed on a middle part (2C) of the superconductor layer (2). The ferromagnetic layer (3) may consist of an electrically conductive or insulating ferromagnetic layer, and may be an electrically conductive ferromagnetic layer formed via an insulating layer. With the superconductor layer (2) formed of a high temperature superconductor, a Josephson junction (1) is provided having large IcRN product. The Josephson junction (1) can be used as a junction for a variety of Josephson devices.
    Type: Grant
    Filed: July 20, 2007
    Date of Patent: June 12, 2012
    Assignee: Japan Science and Technology Agency
    Inventors: Atsutaka Maeda, Espinoza Luis Beltran Gomez
  • Patent number: 8174886
    Abstract: A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; a gate positioned between said first and second regions; and a back-bias region configured to inject charge into or extract charge out of said floating body region to maintain said state of the memory cell. Application of back bias to the back bias region offsets charge leakage out of the floating body and performs a holding operation on the cell. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device.
    Type: Grant
    Filed: September 26, 2011
    Date of Patent: May 8, 2012
    Assignee: Zeno Semiconductor, Inc.
    Inventors: Yuniarto Widjaja, Zvi Or-Bach
  • Patent number: 8003410
    Abstract: A method of operating a quantum system comprising computational elements, including an insulated ring of superconductive material, and semi-closed rings used as an interface between the computational elements and the external world, is disclosed. In one aspect, the method comprises providing an electrical signal, e.g. a current, in an input ring magnetically coupled to a computational element, which generates a magnetic field in the computational element and sensing the change in the current and/or voltage of an output element magnetically coupled to the computational element. The electrical input signal can be an AC signal or a DC signal. The computational element is electromagnetically coupled with other adjacent computational elements and/or with the interface elements. The corresponding magnetic flux between the computational elements and/or the interface elements acts as an information carrier. Ferromagnetic cores are used to improve the magnetic coupling between adjacent elements.
    Type: Grant
    Filed: September 25, 2008
    Date of Patent: August 23, 2011
    Assignees: IMEC, Katholieke Universiteit Leuven
    Inventors: Christoph Kerner, Wim Magnus, Dusan Golubovic
  • Patent number: 7903456
    Abstract: A high-speed lookup table is designed using Rapid Single Flux Quantum (RSFQ) logic elements and fabricated using superconducting integrated circuits. The lookup table is composed of an address decoder and a programmable read-only memory array (PROM). The memory array has rapid parallel pipelined readout and slower serial reprogramming of memory contents. The memory cells are constructed using standard non-destructive reset-set flip-flops (RSN cells) and data flip-flops (DFF cells). An n-bit address decoder is implemented in the same technology and closely integrated with the memory array to achieve high-speed operation as a lookup table. The circuit architecture is scalable to large two-dimensional data arrays.
    Type: Grant
    Filed: October 27, 2008
    Date of Patent: March 8, 2011
    Assignee: Hypres, Inc.
    Inventors: Alexander F. Kirichenko, Timur V. Filippov, Deepnarayan Gupta
  • Patent number: 7830695
    Abstract: A capacitive operation method for quantum computing is disclosed where providing a sequence of write pulses above a threshold voltage induces a single charge population, forming a quantum dot (Q-dot). Determining if the single charge population was induced in the Q-dot occurs by monitoring capacitance changes while the writing is performed. Q-bits (Q-dot pairs) are formed without requiring a separate transistor for each Q-dot by multiplexing the calibration. A device which is able to perform the above method is also disclosed. The device utilizes the ability of cryogenic capacitance bridge circuits to measure the capacitance change caused by the introduction of a single charge population to a Q-dot. The device also permits swapping of Q-dot and Q-bit pairs utilizing a signal multiplexed with the voltage pulses that write (e.g. change the charge population) to the Q-dots.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: November 9, 2010
    Assignee: HRL Laboratories
    Inventor: Jeong-Sun Moon
  • Publication number: 20090244958
    Abstract: In one embodiment, the invention is a hybrid superconducting-magnetic memory cell and array. One embodiment of a memory cell includes a magnetoresistive element and at least one superconducting element wired in parallel with the magnetoresistive element. In a further embodiment, memory cells of the disclosed configuration are arranged to form a memory array.
    Type: Application
    Filed: March 27, 2008
    Publication date: October 1, 2009
    Inventors: JOHN F. BULZACCHELLI, William J. Gallagher, Mark B. Ketchen
  • Publication number: 20090121215
    Abstract: A system employs a plurality of physical qubits, each having a respective bias operable to up to six differentiable inputs to solve a Quadratic Unconstrained Binary Optimization problem. Some physical qubit couplers are operated as intra-logical qubit couplers to ferromagnetically couple respective pairs of the physical qubits as a logical qubit, where each logical qubit represents a variable from the Quadratic Unconstrained Binary Optimization problem.
    Type: Application
    Filed: November 6, 2008
    Publication date: May 14, 2009
    Inventor: Vicky Choi
  • Publication number: 20090033369
    Abstract: A quantum logic gate is formed from multiple qubits coupled to a common resonator, wherein quantum states in the qubits are transferred to the resonator by transitioning a classical control parameter between control points at a selected one of slow and fast transition speeds, relative to the characteristic energy of the coupling, whereby a slow transition speed exchanges energy states of a qubit and the resonator, and a fast transition speed preserves the energy states of a qubit and the resonator.
    Type: Application
    Filed: August 3, 2007
    Publication date: February 5, 2009
    Inventors: James E. Baumgardner, Aaron A. Pesetski
  • Patent number: 7480185
    Abstract: A split NROM flash memory cell is comprised of source/drain regions in a substrate. The split nitride charge storage regions are insulated from the substrate by a first layer of oxide material and from a control gate by a second layer of oxide material. The nitride storage regions are isolated from each other by a depression in the control gate. In a vertical embodiment, the split nitride storage regions are separated by an oxide pillar. The cell is programmed by creating a positive charge on the nitride storage regions and biasing the drain region while grounding the source region. This creates a virtual source/drain region near the drain region such that the hot electrons are accelerated in the narrow pinched off region. The electrons become ballistic and are directly injected onto the nitride storage region that is adjacent to the pinched off channel region.
    Type: Grant
    Filed: March 27, 2007
    Date of Patent: January 20, 2009
    Assignee: Micron Technology, Inc.
    Inventor: Leonard Forbes
  • Patent number: 7459927
    Abstract: A superconductor crossbar switch for connecting a plurality of inputs with a plurality of outputs, including a switching cell having an input, an output and a circuit for connecting the input with the output for bidirectionally transmitting data therebetween. The connection of the retaining and releasing circuitry of a plurality of cells enables the switch to simultaneously retain a selected cell or cells of a group of cells and disable the remaining cells of that group, whereby a subsequent query on a disabled cell is inoperative until the selected cell or cells is released. The crossbar switch is characterized by latency on the order of nanoseconds, a data rate per channel on the order of gigabits per second, essentially zero crosstalk, and detection of contention in nanoseconds or less and resolution of contention in nanoseconds or less.
    Type: Grant
    Filed: August 24, 2005
    Date of Patent: December 2, 2008
    Inventor: Fernand D. Bedard
  • Patent number: 7443720
    Abstract: A single electron-transistor is used to read out charge states of two coupled qubits formed by two Cooper pair boxes. Detection is made about a gate voltage shift of the peak of the current that flows in the single electron transistor in accordance with the charge states. Since the current peak position varies depending on the particular charge state, all four charge states can be independently measured, or read out.
    Type: Grant
    Filed: August 15, 2005
    Date of Patent: October 28, 2008
    Assignees: Riken, NEC Corporation
    Inventors: Oleg Astafiev, Yuri Pashkin, Jaw-Shen Tsai
  • Patent number: 7382678
    Abstract: A methodology is disclosed that enables the delay stages of an analog delay locked loop (DLL) or phase locked loop (PLL) to be programmed according to the operating condition, which may depend on the frequency of the input reference clock. The resulting optimized delay stages allow for a broad frequency range of operation, fast locking time over a wide range of input clock frequencies, and a lower current consumption at high clock frequencies. Better performance is achieved by allowing the number of analog delay stages active during a given operation to be flexibly set. The deactivation or turning off of unused delay stages conserves power at higher frequencies. The high frequency range of operation is increased by using a flexible number of delay stages for various input clock frequencies. Because of the rules governing abstracts, this abstract should not be used to construe the claims.
    Type: Grant
    Filed: December 8, 2005
    Date of Patent: June 3, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Kang Yong Kim, Dong Myung Choi
  • Patent number: 7268576
    Abstract: A first qubit having a superconducting loop interrupted by a plurality of Josephson junctions is provided. Each junction interrupts a different portion of the superconducting loop and each different adjacent pair of junctions in the plurality of Josephson junctions defines a different island. An ancillary device is coupled to the first qubit. In a first example, the ancillary device is a readout mechanism respectively capacitively coupled to a first and second island in the plurality of islands of the first qubit by a first and second capacitance. Quantum nondemolition measurement of the first qubit's state may be performed. In a second example, the ancillary device is a second qubit. The second qubit's first and second islands are respectively capacitively coupled to the first and second islands of the first qubit by a capacitance. In this second example, the coupling is diagonal in the physical basis of the qubits.
    Type: Grant
    Filed: November 4, 2005
    Date of Patent: September 11, 2007
    Assignee: D-Wave Systems Inc.
    Inventor: Mohammad H. S. Amin
  • Patent number: 7253654
    Abstract: A first qubit having a superconducting loop interrupted by a plurality of Josephson junctions is provided. Each junction interrupts a different portion of the superconducting loop and each different adjacent pair of junctions in the plurality of Josephson junctions defines a different island. An ancillary device is coupled to the first qubit. In a first example, the ancillary device is a readout mechanism respectively capacitively coupled to a first and second island in the plurality of islands of the first qubit by a first and second capacitance. Quantum nondemolition measurement of the first qubit's state may be performed. In a second example, the ancillary device is a second qubit. The second qubit's first and second islands are respectively capacitively coupled to the first and second islands of the first qubit by a capacitance. In this second example, the coupling is diagonal in the physical basis of the qubits.
    Type: Grant
    Filed: November 4, 2005
    Date of Patent: August 7, 2007
    Assignee: D-Wave Systems Inc.
    Inventor: Mohammad H. S. Amin
  • Patent number: 7135701
    Abstract: A method for computing using a quantum system comprising a plurality of superconducting qubits is provided. Quantum system can be in any one of at least two configurations including (i) an initialization Hamiltonian H0 and (ii) a problem Hamiltonian HP. The plurality of superconducting qubits are arranged with respect to one another, with a predetermined number of couplings between respective pairs of superconducting qubits in the plurality of qubits, such that the plurality of superconducting qubits, coupled by the predetermined number of couplings, collectively define a computational problem to be solved. In the method, quantum system is initialized to the initialization Hamiltonian HO. Quantum system is then adiabatically changed until it is described by the ground state of the problem Hamiltonian HP. The quantum state of quantum system is then readout thereby solving the computational problem to be solved.
    Type: Grant
    Filed: March 28, 2005
    Date of Patent: November 14, 2006
    Assignee: D-Wave Systems Inc.
    Inventors: Mohammad H. S. Amin, Miles F. H. Steininger
  • Patent number: 6960929
    Abstract: A superconductor crossbar switch for connecting a plurality of inputs with a plurality of outputs, including a switching cell having an input, an output and a circuit for connecting the input with the output for bidirectionally transmitting data therebetween. The connection of the retaining and releasing circuitry of a plurality of cells enables the switch to simultaneously retain a selected cell or cells of a group of cells and disable the remaining cells of that group, whereby a subsequent query on a disabled cell is inoperative until the selected cell or cells is released. The crossbar switch is characterized by latency on the order of nanoseconds, a data rate per channel on the order of gigabits per second, essentially zero crosstalk, and detection of contention in nanoseconds or less and resolution of contention in nanoseconds or less.
    Type: Grant
    Filed: July 23, 2002
    Date of Patent: November 1, 2005
    Inventor: Fernand D. Bedard
  • Patent number: 6943368
    Abstract: A method for quantum computing with a quantum system comprising a first energy level, a second energy level, and a third energy level. The first energy level and said second energy level are capable of being degenerate with respect to each other. In the method a signal is applied to the quantum system. The signal has an alternating amplitude at an associated frequency such that (i) the frequency of the signal correlates with an energy level separation between the first energy level and the third energy level or (ii) the frequency of the signal correlates with an energy level separation between the second energy level and the third energy level. The signal induces an oscillation in the state of the quantum system between the first energy level and the second energy level.
    Type: Grant
    Filed: November 20, 2003
    Date of Patent: September 13, 2005
    Assignee: D-Wave Systems, Inc.
    Inventors: Mohammad H. S. Amin, Anatoly Yu. Smirnov, Alexander Maassen van den Brink, Jeremy P. Hilton, Miles F. H. Steininger
  • Patent number: 6847546
    Abstract: There is provided a high sensitive magnetic field sensor which has a Josephson junction section (2) using a bismuth 2212 oxide high-temperature superconductor single-crystal (1) and is operated based on a periodical variation in a Josephson vortex flow resistance and in which the variation is caused by an electric current which is passed vertical to a Josephson junction surface and, at the same time, a magnetic field which is applied approximately parallel to the Josephson junction surface. The sensor detects a corresponding magnetic field, using a curve which represents a relation between a Josephson vortex flow resistance and a magnetic field and has been obtained beforehand by measurements, and a resistance value which is measured in a state in which an electric current is passed, and can observe a little change of magnetic field in a high magnetic field area.
    Type: Grant
    Filed: January 24, 2003
    Date of Patent: January 25, 2005
    Assignee: National Institute for Materials Science
    Inventors: Kazuto Hirata, Shuichi Ooi
  • Patent number: 6836141
    Abstract: A superconductor memory array (10) has a high associated throughput with low power dissipation and a simple architecture. The superconductor memory array (10) includes memory cells (12a-12d) arranged in a row-column format and each including a storage loop (14a-14d) with a Josephson junction (16a-16d) for storing a binary value. Row address lines (24a, 24b) each are magnetically coupled in series to a row of the memory cells (12a-12d), and column address lines (26a, 26b) each are connected in series to a column of the memory cells (12a-12d). A sense amplifier (38a, 38b) is located on each of the column address lines (26a, 26b) for sensing state changes in the memory cells (12a-12d) located in the columns during a READ operation initiated by row address line READ signals.
    Type: Grant
    Filed: April 11, 2003
    Date of Patent: December 28, 2004
    Assignee: Northrop Grumman Corporation
    Inventor: Quentin P. Herr
  • Patent number: 6803599
    Abstract: A control system for an array of qubits is disclosed. The control system according to the present invention provides currents and voltages to qubits in the array of qubits in order to perform functions on the qubit. The functions that the control system can perform include read out, initialization, and entanglement. The state of a qubit can be determined by grounding the qubit, applying a current across the qubit, measuring the resulting potential drop across the qubit, and interpreting the potential drop as a state of the qubit. A qubit can be initialized by grounding the qubit and applying a current across the qubit in a selected direction for a time sufficient that the quantum state of the qubit can relax into the selected state. In some embodiments, the qubit can be initialized by grounding the qubit and applying a current across the qubit in a selected direction and then ramping the current to zero in order that the state of the qubit relaxes into the selected state.
    Type: Grant
    Filed: June 1, 2001
    Date of Patent: October 12, 2004
    Assignee: D-Wave Systems, Inc.
    Inventors: Mohammad H. S. Amin, Geordie Rose, Alexandre Zagoskin, Jeremy P. Hilton
  • Publication number: 20040160815
    Abstract: There is provided a high sensitive magnetic field sensor which has a Josephson junction section (2) using a bismuth 2212 oxide high-temperature superconductor single-crystal (1) and is operated based on a periodical variation in a Josephson vortex flow resistance and in which the variation is caused by an electric current which is passed vertical to a Josephson junction surface and, at the same time, a magnetic field which is applied approximately parallel to the Josephson junction surface. The sensor detects a corresponding magnetic field, using a curve which represents a relation between a Josephson vortex flow resistance and a magnetic field and has been obtained beforehand by measurements, and a resistance value which is measured in a state in which an electric current is passed, and can observe a little change of magnetic field in a high magnetic field area.
    Type: Application
    Filed: January 14, 2004
    Publication date: August 19, 2004
    Inventors: Kazuto Hirata, Shuichi Ooi
  • Publication number: 20040095803
    Abstract: A method and apparatus for inserting fluxons into an annular Josephson junction is disclosed. Fluxon injection according to the present invention is based on local current injection into one of the superconducting electrodes of the junction. By choosing an appropriate value for the injection current, which depends upon the spacing between injecting leads among other factors, the residual fluxon pinning can be reduced to a very small level. Fluxon injection according to the present invention provides for fully controlling the trapping of individual fluxons in annular Josephson junctions and is reversible to a state of zero fluxons without heating the Josephson above its critical temperature. Fluxon injection according to the present invention can be used for preparing the working state of fluxon oscillators, clock references, radiation detectors, and shaped junctions that may be used as qubits for quantum computing.
    Type: Application
    Filed: September 26, 2003
    Publication date: May 20, 2004
    Applicant: D-Wave Systems, Inc.
    Inventor: Alexey V. Ustinov
  • Patent number: 6734454
    Abstract: A Josephson junction has inherent resistance which effectively shunts the junction and thereby obviates a separate shunt resistor and thus reduces surface area in an integrated circuit including a plurality of Josephson junctions. The Josephson junction comprises a stacked array of layers of Nb and a superconductor with Tc>9° K having a penetration depth greater than that of Nb, for example NbyTil-yN, with a layer of a conducting material having a resistivity between 200 &mgr;&OHgr;-cm, 1 &OHgr;-cm, such as TaxN in the stack. The Josephson junction can be formed on a supporting substrate such as silicon with a ground plane such as Nb on the substrate and an insulating layer such as SiO2 separating the ground plane from the stacked array.
    Type: Grant
    Filed: August 26, 2002
    Date of Patent: May 11, 2004
    Assignees: The Regents of the University of California, The Arizona Board of Regents
    Inventors: Theodore Van Duzer, Xiaoxan Meng, Nathan Newman, Lei Yu, Anupama Bhat Kaul
  • Patent number: 6728131
    Abstract: A method for inserting fluxons into an annular Josephson junction is disclosed. Fluxon injection according to the present invention is based on local current injection into one of the superconducting electrodes of the junction. By choosing an appropriate value for the injection current, which depends upon the spacing between injecting leads among other factors, the residual fluxon pinning can be reduced to a very small level. Fluxon injection according to the present invention provides for fully controlling the trapping of individual fluxons in annular Josephson junctions and is reversible to a state of zero fluxons without heating the Josephson above its critical temperature. Fluxon injection according to the present invention can be used for preparing the working state of fluxon oscillators, clock references, radiation detectors and shaped junctions that may be used as qubits for quantum computing.
    Type: Grant
    Filed: April 4, 2002
    Date of Patent: April 27, 2004
    Assignee: D-Wave Systems, Inc.
    Inventor: Alexey V. Ustinov
  • Publication number: 20030039138
    Abstract: A rapid SFQ one-way buffer (13, 1, 4, 5, 15, 2 & 9), is combined with a Josephson transmission line (17,3, 19, 16, 21 & 4) that is lightly loaded (RL) to provide a superconductor driver capable of producing double flux quantum output pulses. Each SFQ pulse applied to the input of the one-way buffer propagates through the Josephson transmission line to generate a double flux quantum pulse at the transmission line output.
    Type: Application
    Filed: August 22, 2001
    Publication date: February 27, 2003
    Inventor: Quentin P. Herr
  • Patent number: 6452831
    Abstract: A memory device includes a plurality of cells, each having a first electrode coupled to a first location on semiconductor material, a second electrode coupled to a second location disposed away from the first location on the semiconductor material and a plurality of islands of semiconductor material. The islands have a maximum dimension of three to five nanometers and are surrounded by an insulator having a thickness of between five and twenty nanometers. The islands and the surrounding insulator are formed in pores extending into the semiconductor material between the first and second electrodes. As a result, the memory cells are able to provide consistent, externally observable changes in response to the presence or absence of a single electron on the island.
    Type: Grant
    Filed: August 29, 2001
    Date of Patent: September 17, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 6242939
    Abstract: A superconducting circuit device of a voltage-type logic device is large in current driving capability and, accordingly, electric power consumption; however, the switching speed is not so fast, and a superconducting circuit device of a fluxoid-type logic device is small in current driving capability and, accordingly, the electric power consumption; however the switching speed is faster than that of the superconducting circuit device of the voltage-type logic device, wherein the superconducting circuit device of the voltage-type logic device and the superconducting circuit device of the fluxoid-type logic device are selectively used in a superconducting circuit such as a superconducting random access memory, a superconducting NOR circuit and a superconducting signal converting circuit so as to realize small electric power consumption and high-speed switching action.
    Type: Grant
    Filed: March 2, 2000
    Date of Patent: June 5, 2001
    Assignees: NEC Corporation, International Superconductivity Technology Center
    Inventors: Shuichi Nagasawa, Kazunori Miyahara, Youichi Enomoto
  • Patent number: 6229332
    Abstract: The present invention is a superconductive logic gate assembly (50, 100), a superconductive NOR gate assembly (10), and a superconductive random access memory (150). A superconductive logic gate assembly in accordance with the invention includes a plurality of logic inputs (INPUTS 1-N), each logic input being coupled to a SQUID (16) and each SQUID including at least one resistance (22) which eliminates hysteresis in an output of the SQUID produced in responding to a change in signal level at the logic inputs to the SQUID, a DC bias (20) coupled to each SQUID, and an output circuit (14) coupled to each SQUID for providing a logic output (OUTPUT) in response to the logic inputs.
    Type: Grant
    Filed: November 2, 2000
    Date of Patent: May 8, 2001
    Assignee: TRW Inc.
    Inventor: Quentin P. Herr
  • Patent number: 6060664
    Abstract: A prior-art electronic circuit component comprising an insulating film and a circuit conductive layer made of a superconducting metal suffers low reliability resulting from insufficient adhesion between these layers. An electronic circuit component of the invention comprises an insulating film made of a high polymer material having a dielectric constant of 2.5 or less, a base metal layer formed of copper on the insulating film, having a thickness of 0.01 to 0.3 .mu.m, and a circuit conductive layer formed of at least one of niobium and niobium nitride on the base metal layer. The electronic circuit component of the invention can accomplish an increased adhesion between the insulating film and the circuit conductive layer.
    Type: Grant
    Filed: June 26, 1998
    Date of Patent: May 9, 2000
    Assignee: Kyocera Corporation
    Inventors: Shigeo Tanahashi, Tokuichi Yamaji
  • Patent number: 5942765
    Abstract: In the random access memory utilizing an oxide high-temperature superconductor, a first high-temperature superconductor layer 1, a non-superconductor layer 2, a second high-temperature superconductor layer 3 and a non-superconductor layer 4 are formed on an insulated substrate. The first high-temperature superconductor layer 1 is formed in a first loop, forming a memory storage superconductor quantum interference device by two Josephson junctions and a control current line I.sub.WX (6) and a bias current line I.sub.WY (8) in order to store the flux quantum. The second high-temperature superconductor layer 3 is formed in a second loop, forming a reading superconducting quantum interference device by two Josephson junctions and a control current line I.sub.RX (5) and a bias current line I.sub.RY (7).
    Type: Grant
    Filed: November 20, 1997
    Date of Patent: August 24, 1999
    Assignee: International Superconductivity Technology Center
    Inventors: Kazunori Miyahara, Yoichi Enomoto, Shoji Tanaka
  • Patent number: 5930165
    Abstract: The instant invention is a switch, comprising: (1) a pathway of a superconductive material; and (2) a ferromagnet, where the ferromagnet is adapted for having at least a first magnetization state and a second magnetization state, where fringe fields from the ferromagnet in the first magnetization state do not exceed a predetermined magnetic field in the superconductive pathway to convert at least a portion of the superconductive pathway to the normal state; where fringe fields from the ferromagnet in the second magnetization state exceed the predetermined magnetic field in the superconductive pathway to convert at least a portion of the superconductive pathway to the normal state.
    Type: Grant
    Filed: October 31, 1997
    Date of Patent: July 27, 1999
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Mark B. Johnson, Thomas W. Clinton
  • Patent number: 5872731
    Abstract: A multi-state Josephson memory in a superconductor integrated circuit includes a plurality of superconductive quantum interference device (SQUID) memory cells 2 each having a SQUID 4 characterized by a SQUID loop inductance L and a junction critical current I.sub.c, which determine the number of memory states that can be stored in the SQUID 4. A gate current I.sub.g is transmitted to the superconductive inductors 6 and 8 of the SQUID 4 to perform a read operation by crossing a designated number of current threshold boundaries corresponding to the memory state stored in the SQUID, so that the Josephson junction 12 of the SQUID 4 generates a number of pulses corresponding to the memory state. A control current I.sub.con writes data to the SQUID 4 through a control current input 16, and is preferably magnetically coupled to the SQUID 4 through superconductive inductor pairs 18, 6 and 20, 8. In a preferred embodiment, a plurality of SQUID memory cells 70a, 70b, . . .
    Type: Grant
    Filed: October 10, 1997
    Date of Patent: February 16, 1999
    Assignee: TRW Inc.
    Inventors: Hugo W-K. Chan, Arnold H. Silver, Robert D. Sandell