Abstract: Quantum processors having qubits with tunable capacitance are provided. The qubits include Josephson junctions shunted by capacitors and are tunably coupled to capacitance loops such that the resonant frequencies of the qubits and capacitance loops avoid entanglement with each other. Methods for tuning the capacitance of such qubits by varying the coupler's coupling strength are provided. These methods include methods for calibrating qubits' capacitance.

Abstract: Methods, systems and apparatus for targeting many-body states on a quantum computer. In one aspect, a method includes an adaptive phase shift method that includes preparing the quantum system in an initial state, wherein the initial state has non-zero overlap with the target eigenstate; preparing an ancilla qubit in a zero computational basis state; and iteratively applying a quantum eigenstate locking circuit to the quantum system and ancilla qubit until the state of the quantum system approximates the target eigenstate, wherein the quantum eigenstate locking circuit comprises a phase gate that, at each n-th iteration, is updated using a current average energy estimate of the quantum system.

Abstract: Disclosed is a neuron circuit which electronically applies the working principle of the neurons in the human brain. The neuron circuit controls an input signal according to a set threshold value, and enables provision of an output signal above the threshold value.

Abstract: A memory cell having a Josephson junction and a magnetic junction situated in a close proximity to the Josephson junction. The two junctions may be vertically integrated. The magnetic junction has at least two magnetic layers with different coercive forces and a non-magnetic layer therebetween, to form a spin valve or pseudo-spin valve. A magnetization direction of a magnetic layer with lower coercive force can be rotated with respect to the larger coercive force magnetic layer(s). Magnetic fields produced by appropriately configured control lines carrying electric current, or spin-polarized current through the magnetic junction, can result in rotation. The magnetic junction influences the Josephson critical current of the Josephson junction, leading to distinct values of critical current which can serve as digital logic states. The so obtained memory cell can be integrated into the large arrays containing a plurality of the cells, to enable the selective READ and WRITE operations.

Abstract: A system and method for high-speed, low-power cryogenic computing are presented, comprising ultrafast energy-efficient RSFQ superconducting computing circuits, and hybrid magnetic/superconducting memory arrays and interface circuits, operating together in the same cryogenic environment. An arithmetic logic unit and register file with an ultrafast asynchronous wave-pipelined datapath is also provided. The superconducting circuits may comprise inductive elements fabricated using both a high-inductance layer and a low-inductance layer. The memory cells may comprise superconducting tunnel junctions that incorporate magnetic layers. Alternatively, the memory cells may comprise superconducting spin transfer magnetic devices (such as orthogonal spin transfer and spin-Hall effect devices). Together, these technologies may enable the production of an advanced superconducting computer that operates at clock speeds up to 100 GHz.

Abstract: A technique relates to a trilayer Josephson junction structure. A dielectric layer is on a base electrode layer that is on a substrate. A counter electrode layer is on the dielectric layer. First and second counter electrodes are formed from the counter electrode layer. First and second dielectric layers are formed from the dielectric layer. First and second base electrodes are formed from base electrode layer. The first counter electrode, first dielectric layer, and first base electrode form a first stack. The second counter electrode, second dielectric layer, and second base electrode form a second stack. A shunting capacitor is between first and second base electrodes. An ILD layer is deposited on the substrate, the first and second counter electrodes, and the first and second base electrodes. A contact bridge connects the first and second counter electrodes. An air gap is formed underneath the contact bridge by removing ILD.

Abstract: Superconducting switch having a persistent and a non-persistent state and its use as a driver in a memory system are described. An example superconducting switch includes a first superconducting layer and a second superconducting layer. The superconducting switch includes a first magnetic layer having a fixed magnetization state. The superconducting switch includes a second magnetic layer capable of being at least in a first or a second magnetization state. The superconducting switch is capable of being in a first state or a second state, and the superconducting switch is configured such that an application of a magnetic field to the second magnetic layer changes a magnetization of the second magnetic layer from the first magnetization state to the second magnetization state placing the superconducting switch in the second state and a removal of the magnetic field automatically returns the superconducting switch from the second state to the first state.

Abstract: Magnetic Josephson junction driven flux-biased superconductor memory cell and methods are provided. A memory cell may include a magnetic Josephson junction (MJJ) superconducting quantum interference device (SQUID) comprising a first MJJ device and a second MJJ device, arranged in parallel to each other, where the MJJ SQUID is configured to generate a first flux-bias or a second flux-bias, where the first flux-bias corresponds to a first direction of current flow in the MJJ SQUID and the second flux-bias corresponds to a second direction of current flow in the MJJ SQUID. The memory cell may further include a superconducting metal-based superconducting quantum interference device (SQUID) including a first Josephson junction (JJ) and a second JJ, arranged in parallel to each other, where each of the first JJ and the second JJ has a critical current responsive to any flux-bias generated by the MJJ SQUID.

Abstract: A computer system employs a network that between a data programming system and one or more superconducting programmable devices of a superconducting processor chip. Routers on the network, such as first-, second- and third-stage routers direct communications with the superconducting programmable devices. A superconducting memory register may load data signals received from a first-stage router into corresponding superconducting programmable devices. The system may employ additional superconducting chips, first-, second- or third-stage routers.

Abstract: A method for fabricating a chip surface base includes preparing a first substrate, preparing a plurality of vias in the first substrate, depositing metal fillings into the plurality of vias, preparing a second substrate, bonding the first and second substrates and exposing the metal fillings. A method for fabricating a chip surface base includes preparing a first and second substrate, depositing a metal on at least one of the first and second substrates, bonding the first and second substrates, preparing a plurality of vias in the first substrate, depositing metal fillings into the plurality of vias and exposing the metal fillings. A chip surface base device includes a first substrate, a second substrate, a metal layer disposed between the first and second substrates and a plurality of vias disposed on the first substrate.

Abstract: A device includes at least one superconducting tunnel junction having a junction region comprising a junction barrier material responsive to electromagnetic fields within the MHz to THz range. The junction may be contained within a bi-SQUID loop having two main junctions and a center junction. The junction barrier material for the main junctions may have different electromagnetic-responsive properties than the junction barrier material for the center junction. The junction barrier material may include type-I multiferroics, type-II multiferroics, a composite multiferroic including layers of magnets and ferroelectrics, or piezoelectric materials. An array of connected bi-SQUID loops may be formed, where the main junctions of each bi-SQUID loop in each row are connected. The electromagnetic-responsive properties of the junction barrier material for center junctions of each bi-SQUID loop may vary by each array column or row. The center/main junctions of each bi-SQUID loop may be connected to an input signal line.

Abstract: A quantum processor is operable as a universal adiabatic quantum computing system. The quantum processor includes physical qubits, with at least a first and second communicative coupling available between pairs of qubits via an in-situ tunable superconducting capacitive coupler and an in-situ tunable superconducting inductive coupler, respectively. Tunable couplers provide diagonal and off-diagonal coupling. Compound Josephson junctions (CJJs) of the tunable couplers are responsive to a flux bias to tune a sign and magnitude of a sum of a capacitance of a fixed capacitor and a tunable capacitance which is mediated across a pair of coupling capacitors. The qubits may be hybrid qubits, operable in a flux regime or a charge regime. Qubits may include a pair of CJJs that interrupt a loop of material and which are separated by an island of superconducting material which is voltage biased with respect to a qubit body.

Abstract: One aspect of the present invention includes a Josephson magnetic memory system. The system includes a superconducting electrode that conducts a read current. The system also includes a hysteretic magnetic Josephson junction (HMJJ). The HMJJ can store a binary value and convert superconducting pairs associated with the read current flowing through the HMJJ from a singlet-state to a triplet-state. The system further includes a write circuit magnetically coupled to the HMJJ and configured to write the binary value into the at HMJJ in response to at least one write current and a read circuit configured to determine the binary value stored in the HMJJ in response to application of the read current to the HMJJ.

Abstract: One embodiment describes a memory cell. The memory cell includes a phase hysteretic magnetic Josephson junction (PHMJJ) that is configured to store one of a first binary logic state corresponding to a binary logic-1 state and a second binary logic state corresponding to a binary logic-0 state in response to a write current and to generate a superconducting phase based on the stored digital state. The memory cell also includes at least one Josephson junction having a critical current that is based on the superconducting phase of the PHMJJ and being configured to provide an output corresponding to the stored digital state in response to a read current.

Abstract: A superconducting memory cell includes a magnetic Josephson junction (MJJ) with a ferromagnetic material, having at least two switchable states of magnetization. The binary state of the MJJ manifests itself as a pulse appearing, or not appearing, on the output. A superconducting memory includes an array of memory cells. Each memory cell includes a comparator with at least one MJJ. Selected X and Y-directional write lines in their combination are capable of switching the magnetization of the MJJ. A superconducting device includes a first and a second junction in a stacked configuration. The first junction has an insulating layer barrier, and the second junction has an insulating layer sandwiched in-between two ferromagnetic layers as barrier. An electrical signal inputted across the first junction is amplified across the second junction.

Abstract: One aspect of the present invention includes a Josephson magnetic memory system. The system includes a superconducting electrode that conducts a read current. The system also includes a hysteretic magnetic Josephson junction (HMJJ). The HMJJ can store a binary value and convert superconducting pairs associated with the read current flowing through the HMJJ from a singlet-state to a triplet-state. The system further includes a write circuit magnetically coupled to the HMJJ and configured to write the binary value into the at HMJJ in response to at least one write current and a read circuit configured to determine the binary value stored in the HMJJ in response to application of the read current to the HMJJ.

Abstract: In one embodiment, the invention is a hybrid superconducting-magnetic memory cell and array. One embodiment of a memory cell includes a magnetoresistive element and at least one superconducting element wired in parallel with the magnetoresistive element. In a further embodiment, memory cells of the disclosed configuration are arranged to form a memory array.

Abstract: Methods and apparatuses are provided for storing a quantum bit. One apparatus includes a first phase qubit, a second phase qubit, and a common bias circuit configured to provide a first bias to the first phase qubit and a second bias to the second phase qubit, such that noise within the first bias is anti-correlated to noise within the second bias.

Abstract: A switching cell for a demultiplexer circuit includes a superconducting input signal path, at least two superconducting output signal paths, and transformers located between an intersection node and respective ends of the output signal paths. Flux applied via the transformers can influence which direction a signal propagates. The switching cell may also include power input nodes. Switching cells may be arranged in various configurations, for example a binary tree or H-tree. A superconducting inductor ladder circuit can perform a digital-to-analog conversion. Flux storage structures may be used with individual switching cells. Latching qubits may be employed. Buffer rows of switching cells may be used to reduce or eliminate cascade error.

Abstract: Techniques are provided for programming a spin torque transfer magnetic random access memory (STT-MRAM) cell using a unidirectional and/or symmetrical programming current. A unidirectional programming current flows through the free region of the STT-MRAM cell in one direction to switch the magnetization of the free region in at least two different directions. A symmetrical programming current switches the magnetization of the free region to either of the two different directions using a substantially similar current magnitude. In some embodiments, the STT-MRAM cell includes two fixed regions, each having fixed magnetizations in opposite directions and a free region configured to be switched in magnetization to be either parallel with or antiparallel to the magnetization of one of the fixed regions. Switching the free region to different magnetization directions may involve directing the programming current through one of the two oppositely magnetized fixed regions.

Abstract: In one embodiment, the invention is a hybrid superconducting-magnetic memory cell and array. One embodiment of a memory cell includes a magnetoresistive element and at least one superconducting element wired in parallel with the magnetoresistive element. In a further embodiment, memory cells of the disclosed configuration are arranged to form a memory array.

Abstract: A quantum memory component including a quantum dot molecule having first and second quantum dots provided in respective first and second layers separated by a barrier layer; an exciton comprising an electron and hole bound state in said quantum dot molecule, the spin state of said exciton forming a qubit; first and second electrical contacts respectively provided below the first quantum dot and above the second quantum dot; a voltage source to apply an electric field across said quantum dot molecule; a controller to modulate the electric field across the quantum dot molecule, including an information acquiring circuit to acquire information concerning the relationship between fine structure splitting of the exciton and the applied electric field and a timing circuit to allow switching of the exciton from an indirect configuration to a direct configuration at predetermined times derived from the fine structure splitting.

Abstract: Methods and apparatuses are provided for storing a quantum bit. One apparatus includes a first phase qubit, a second phase qubit, and a common bias circuit configured to provide a first bias to the first phase qubit and a second bias to the second phase qubit, such that noise within the first bias is anti-correlated to noise within the second bias.

Abstract: One aspect of the present invention includes a Josephson magnetic random access memory (JMRAM) system. The system includes an array of memory cells arranged in rows and columns. Each of the memory cells includes an HMJJD that is configured to store a digital state corresponding to one of a binary logic-1 state and a binary logic-0 state in response to a word-write current that is provided on a word-write line and a bit-write current that is provided on a bit-write line. The HMJJD is also configured to output the respective digital state in response to a word-read current that is provided on a word-read line and a bit-read current that is provided on a bit-read line.

Abstract: A superconducting memory cell includes a magnetic Josephson junction (MJJ) with a ferromagnetic material, having at least two switchable states of magnetization. The binary state of the MJJ manifests itself as a pulse appearing, or not appearing, on the output. A superconducting memory includes an array of memory cells. Each memory cell includes a comparator with at least one MJJ. Selected X and Y-directional write lines in their combination are capable of switching the magnetization of the MJJ. A superconducting device includes a first and a second junction in a stacked configuration. The first junction has an insulating layer barrier, and the second junction has an insulating layer sandwiched in-between two ferromagnetic layers as barrier. An electrical signal inputted across the first junction is amplified across the second junction.

Abstract: In one embodiment, the invention is a hybrid superconducting-magnetic memory cell and array. One embodiment of a memory cell includes a magnetoresistive element and at least one superconducting element wired in parallel with the magnetoresistive element. In a further embodiment, memory cells of the disclosed configuration are arranged to form a memory array.

Abstract: A novel Josephson junction and a novel Josephson junction device are provided which eliminates the need to form an insulating barrier layer. The Josephson junction (1) comprises a superconductor layer (2) and a ferromagnetic layer (3) formed on a middle part (2C) of the superconductor layer (2). The ferromagnetic layer (3) may consist of an electrically conductive or insulating ferromagnetic layer, and may be an electrically conductive ferromagnetic layer formed via an insulating layer. With the superconductor layer (2) formed of a high temperature superconductor, a Josephson junction (1) is provided having large IcRN product. The Josephson junction (1) can be used as a junction for a variety of Josephson devices.

Abstract: A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; a gate positioned between said first and second regions; and a back-bias region configured to inject charge into or extract charge out of said floating body region to maintain said state of the memory cell. Application of back bias to the back bias region offsets charge leakage out of the floating body and performs a holding operation on the cell. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device.

Abstract: A method of operating a quantum system comprising computational elements, including an insulated ring of superconductive material, and semi-closed rings used as an interface between the computational elements and the external world, is disclosed. In one aspect, the method comprises providing an electrical signal, e.g. a current, in an input ring magnetically coupled to a computational element, which generates a magnetic field in the computational element and sensing the change in the current and/or voltage of an output element magnetically coupled to the computational element. The electrical input signal can be an AC signal or a DC signal. The computational element is electromagnetically coupled with other adjacent computational elements and/or with the interface elements. The corresponding magnetic flux between the computational elements and/or the interface elements acts as an information carrier. Ferromagnetic cores are used to improve the magnetic coupling between adjacent elements.

Abstract: A high-speed lookup table is designed using Rapid Single Flux Quantum (RSFQ) logic elements and fabricated using superconducting integrated circuits. The lookup table is composed of an address decoder and a programmable read-only memory array (PROM). The memory array has rapid parallel pipelined readout and slower serial reprogramming of memory contents. The memory cells are constructed using standard non-destructive reset-set flip-flops (RSN cells) and data flip-flops (DFF cells). An n-bit address decoder is implemented in the same technology and closely integrated with the memory array to achieve high-speed operation as a lookup table. The circuit architecture is scalable to large two-dimensional data arrays.

Abstract: A capacitive operation method for quantum computing is disclosed where providing a sequence of write pulses above a threshold voltage induces a single charge population, forming a quantum dot (Q-dot). Determining if the single charge population was induced in the Q-dot occurs by monitoring capacitance changes while the writing is performed. Q-bits (Q-dot pairs) are formed without requiring a separate transistor for each Q-dot by multiplexing the calibration. A device which is able to perform the above method is also disclosed. The device utilizes the ability of cryogenic capacitance bridge circuits to measure the capacitance change caused by the introduction of a single charge population to a Q-dot. The device also permits swapping of Q-dot and Q-bit pairs utilizing a signal multiplexed with the voltage pulses that write (e.g. change the charge population) to the Q-dots.

Abstract: In one embodiment, the invention is a hybrid superconducting-magnetic memory cell and array. One embodiment of a memory cell includes a magnetoresistive element and at least one superconducting element wired in parallel with the magnetoresistive element. In a further embodiment, memory cells of the disclosed configuration are arranged to form a memory array.

Abstract: A system employs a plurality of physical qubits, each having a respective bias operable to up to six differentiable inputs to solve a Quadratic Unconstrained Binary Optimization problem. Some physical qubit couplers are operated as intra-logical qubit couplers to ferromagnetically couple respective pairs of the physical qubits as a logical qubit, where each logical qubit represents a variable from the Quadratic Unconstrained Binary Optimization problem.

Abstract: A quantum logic gate is formed from multiple qubits coupled to a common resonator, wherein quantum states in the qubits are transferred to the resonator by transitioning a classical control parameter between control points at a selected one of slow and fast transition speeds, relative to the characteristic energy of the coupling, whereby a slow transition speed exchanges energy states of a qubit and the resonator, and a fast transition speed preserves the energy states of a qubit and the resonator.

Abstract: A split NROM flash memory cell is comprised of source/drain regions in a substrate. The split nitride charge storage regions are insulated from the substrate by a first layer of oxide material and from a control gate by a second layer of oxide material. The nitride storage regions are isolated from each other by a depression in the control gate. In a vertical embodiment, the split nitride storage regions are separated by an oxide pillar. The cell is programmed by creating a positive charge on the nitride storage regions and biasing the drain region while grounding the source region. This creates a virtual source/drain region near the drain region such that the hot electrons are accelerated in the narrow pinched off region. The electrons become ballistic and are directly injected onto the nitride storage region that is adjacent to the pinched off channel region.

Abstract: A superconductor crossbar switch for connecting a plurality of inputs with a plurality of outputs, including a switching cell having an input, an output and a circuit for connecting the input with the output for bidirectionally transmitting data therebetween. The connection of the retaining and releasing circuitry of a plurality of cells enables the switch to simultaneously retain a selected cell or cells of a group of cells and disable the remaining cells of that group, whereby a subsequent query on a disabled cell is inoperative until the selected cell or cells is released. The crossbar switch is characterized by latency on the order of nanoseconds, a data rate per channel on the order of gigabits per second, essentially zero crosstalk, and detection of contention in nanoseconds or less and resolution of contention in nanoseconds or less.

Abstract: A single electron-transistor is used to read out charge states of two coupled qubits formed by two Cooper pair boxes. Detection is made about a gate voltage shift of the peak of the current that flows in the single electron transistor in accordance with the charge states. Since the current peak position varies depending on the particular charge state, all four charge states can be independently measured, or read out.

Abstract: A methodology is disclosed that enables the delay stages of an analog delay locked loop (DLL) or phase locked loop (PLL) to be programmed according to the operating condition, which may depend on the frequency of the input reference clock. The resulting optimized delay stages allow for a broad frequency range of operation, fast locking time over a wide range of input clock frequencies, and a lower current consumption at high clock frequencies. Better performance is achieved by allowing the number of analog delay stages active during a given operation to be flexibly set. The deactivation or turning off of unused delay stages conserves power at higher frequencies. The high frequency range of operation is increased by using a flexible number of delay stages for various input clock frequencies. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Abstract: A first qubit having a superconducting loop interrupted by a plurality of Josephson junctions is provided. Each junction interrupts a different portion of the superconducting loop and each different adjacent pair of junctions in the plurality of Josephson junctions defines a different island. An ancillary device is coupled to the first qubit. In a first example, the ancillary device is a readout mechanism respectively capacitively coupled to a first and second island in the plurality of islands of the first qubit by a first and second capacitance. Quantum nondemolition measurement of the first qubit's state may be performed. In a second example, the ancillary device is a second qubit. The second qubit's first and second islands are respectively capacitively coupled to the first and second islands of the first qubit by a capacitance. In this second example, the coupling is diagonal in the physical basis of the qubits.

Abstract: A first qubit having a superconducting loop interrupted by a plurality of Josephson junctions is provided. Each junction interrupts a different portion of the superconducting loop and each different adjacent pair of junctions in the plurality of Josephson junctions defines a different island. An ancillary device is coupled to the first qubit. In a first example, the ancillary device is a readout mechanism respectively capacitively coupled to a first and second island in the plurality of islands of the first qubit by a first and second capacitance. Quantum nondemolition measurement of the first qubit's state may be performed. In a second example, the ancillary device is a second qubit. The second qubit's first and second islands are respectively capacitively coupled to the first and second islands of the first qubit by a capacitance. In this second example, the coupling is diagonal in the physical basis of the qubits.

Abstract: A method for computing using a quantum system comprising a plurality of superconducting qubits is provided. Quantum system can be in any one of at least two configurations including (i) an initialization Hamiltonian H0 and (ii) a problem Hamiltonian HP. The plurality of superconducting qubits are arranged with respect to one another, with a predetermined number of couplings between respective pairs of superconducting qubits in the plurality of qubits, such that the plurality of superconducting qubits, coupled by the predetermined number of couplings, collectively define a computational problem to be solved. In the method, quantum system is initialized to the initialization Hamiltonian HO. Quantum system is then adiabatically changed until it is described by the ground state of the problem Hamiltonian HP. The quantum state of quantum system is then readout thereby solving the computational problem to be solved.

Abstract: A superconductor crossbar switch for connecting a plurality of inputs with a plurality of outputs, including a switching cell having an input, an output and a circuit for connecting the input with the output for bidirectionally transmitting data therebetween. The connection of the retaining and releasing circuitry of a plurality of cells enables the switch to simultaneously retain a selected cell or cells of a group of cells and disable the remaining cells of that group, whereby a subsequent query on a disabled cell is inoperative until the selected cell or cells is released. The crossbar switch is characterized by latency on the order of nanoseconds, a data rate per channel on the order of gigabits per second, essentially zero crosstalk, and detection of contention in nanoseconds or less and resolution of contention in nanoseconds or less.

Abstract: A method for quantum computing with a quantum system comprising a first energy level, a second energy level, and a third energy level. The first energy level and said second energy level are capable of being degenerate with respect to each other. In the method a signal is applied to the quantum system. The signal has an alternating amplitude at an associated frequency such that (i) the frequency of the signal correlates with an energy level separation between the first energy level and the third energy level or (ii) the frequency of the signal correlates with an energy level separation between the second energy level and the third energy level. The signal induces an oscillation in the state of the quantum system between the first energy level and the second energy level.

Abstract: There is provided a high sensitive magnetic field sensor which has a Josephson junction section (2) using a bismuth 2212 oxide high-temperature superconductor single-crystal (1) and is operated based on a periodical variation in a Josephson vortex flow resistance and in which the variation is caused by an electric current which is passed vertical to a Josephson junction surface and, at the same time, a magnetic field which is applied approximately parallel to the Josephson junction surface. The sensor detects a corresponding magnetic field, using a curve which represents a relation between a Josephson vortex flow resistance and a magnetic field and has been obtained beforehand by measurements, and a resistance value which is measured in a state in which an electric current is passed, and can observe a little change of magnetic field in a high magnetic field area.

Abstract: A superconductor memory array (10) has a high associated throughput with low power dissipation and a simple architecture. The superconductor memory array (10) includes memory cells (12a-12d) arranged in a row-column format and each including a storage loop (14a-14d) with a Josephson junction (16a-16d) for storing a binary value. Row address lines (24a, 24b) each are magnetically coupled in series to a row of the memory cells (12a-12d), and column address lines (26a, 26b) each are connected in series to a column of the memory cells (12a-12d). A sense amplifier (38a, 38b) is located on each of the column address lines (26a, 26b) for sensing state changes in the memory cells (12a-12d) located in the columns during a READ operation initiated by row address line READ signals.

Abstract: A control system for an array of qubits is disclosed. The control system according to the present invention provides currents and voltages to qubits in the array of qubits in order to perform functions on the qubit. The functions that the control system can perform include read out, initialization, and entanglement. The state of a qubit can be determined by grounding the qubit, applying a current across the qubit, measuring the resulting potential drop across the qubit, and interpreting the potential drop as a state of the qubit. A qubit can be initialized by grounding the qubit and applying a current across the qubit in a selected direction for a time sufficient that the quantum state of the qubit can relax into the selected state. In some embodiments, the qubit can be initialized by grounding the qubit and applying a current across the qubit in a selected direction and then ramping the current to zero in order that the state of the qubit relaxes into the selected state.

Abstract: There is provided a high sensitive magnetic field sensor which has a Josephson junction section (2) using a bismuth 2212 oxide high-temperature superconductor single-crystal (1) and is operated based on a periodical variation in a Josephson vortex flow resistance and in which the variation is caused by an electric current which is passed vertical to a Josephson junction surface and, at the same time, a magnetic field which is applied approximately parallel to the Josephson junction surface. The sensor detects a corresponding magnetic field, using a curve which represents a relation between a Josephson vortex flow resistance and a magnetic field and has been obtained beforehand by measurements, and a resistance value which is measured in a state in which an electric current is passed, and can observe a little change of magnetic field in a high magnetic field area.

Abstract: A method and apparatus for inserting fluxons into an annular Josephson junction is disclosed. Fluxon injection according to the present invention is based on local current injection into one of the superconducting electrodes of the junction. By choosing an appropriate value for the injection current, which depends upon the spacing between injecting leads among other factors, the residual fluxon pinning can be reduced to a very small level. Fluxon injection according to the present invention provides for fully controlling the trapping of individual fluxons in annular Josephson junctions and is reversible to a state of zero fluxons without heating the Josephson above its critical temperature. Fluxon injection according to the present invention can be used for preparing the working state of fluxon oscillators, clock references, radiation detectors, and shaped junctions that may be used as qubits for quantum computing.

Abstract: A Josephson junction has inherent resistance which effectively shunts the junction and thereby obviates a separate shunt resistor and thus reduces surface area in an integrated circuit including a plurality of Josephson junctions. The Josephson junction comprises a stacked array of layers of Nb and a superconductor with Tc>9° K having a penetration depth greater than that of Nb, for example NbyTil-yN, with a layer of a conducting material having a resistivity between 200 &mgr;&OHgr;-cm, 1 &OHgr;-cm, such as TaxN in the stack. The Josephson junction can be formed on a supporting substrate such as silicon with a ground plane such as Nb on the substrate and an insulating layer such as SiO2 separating the ground plane from the stacked array.

Abstract: A method for inserting fluxons into an annular Josephson junction is disclosed. Fluxon injection according to the present invention is based on local current injection into one of the superconducting electrodes of the junction. By choosing an appropriate value for the injection current, which depends upon the spacing between injecting leads among other factors, the residual fluxon pinning can be reduced to a very small level. Fluxon injection according to the present invention provides for fully controlling the trapping of individual fluxons in annular Josephson junctions and is reversible to a state of zero fluxons without heating the Josephson above its critical temperature. Fluxon injection according to the present invention can be used for preparing the working state of fluxon oscillators, clock references, radiation detectors and shaped junctions that may be used as qubits for quantum computing.