Abstract: A superconducting circuit device of a voltage-type logic device is large in current driving capability and, accordingly, electric power consumption; however, the switching speed is not so fast, and a superconducting circuit device of a fluxoid-type logic device is small in current driving capability and, accordingly, the electric power consumption; however the switching speed is faster than that of the superconducting circuit device of the voltage-type logic device, wherein the superconducting circuit device of the voltage-type logic device and the superconducting circuit device of the fluxoid-type logic device are selectively used in a superconducting circuit such as a superconducting random access memory, a superconducting NOR circuit and a superconducting signal converting circuit so as to realize small electric power consumption and high-speed switching action.

Abstract: The present invention is a superconductive logic gate assembly (50, 100), a superconductive NOR gate assembly (10), and a superconductive random access memory (150). A superconductive logic gate assembly in accordance with the invention includes a plurality of logic inputs (INPUTS 1-N), each logic input being coupled to a SQUID (16) and each SQUID including at least one resistance (22) which eliminates hysteresis in an output of the SQUID produced in responding to a change in signal level at the logic inputs to the SQUID, a DC bias (20) coupled to each SQUID, and an output circuit (14) coupled to each SQUID for providing a logic output (OUTPUT) in response to the logic inputs.

Abstract: A prior-art electronic circuit component comprising an insulating film and a circuit conductive layer made of a superconducting metal suffers low reliability resulting from insufficient adhesion between these layers. An electronic circuit component of the invention comprises an insulating film made of a high polymer material having a dielectric constant of 2.5 or less, a base metal layer formed of copper on the insulating film, having a thickness of 0.01 to 0.3 .mu.m, and a circuit conductive layer formed of at least one of niobium and niobium nitride on the base metal layer. The electronic circuit component of the invention can accomplish an increased adhesion between the insulating film and the circuit conductive layer.

Abstract: In the random access memory utilizing an oxide high-temperature superconductor, a first high-temperature superconductor layer 1, a non-superconductor layer 2, a second high-temperature superconductor layer 3 and a non-superconductor layer 4 are formed on an insulated substrate. The first high-temperature superconductor layer 1 is formed in a first loop, forming a memory storage superconductor quantum interference device by two Josephson junctions and a control current line I.sub.WX (6) and a bias current line I.sub.WY (8) in order to store the flux quantum. The second high-temperature superconductor layer 3 is formed in a second loop, forming a reading superconducting quantum interference device by two Josephson junctions and a control current line I.sub.RX (5) and a bias current line I.sub.RY (7).

Abstract: The instant invention is a switch, comprising: (1) a pathway of a superconductive material; and (2) a ferromagnet, where the ferromagnet is adapted for having at least a first magnetization state and a second magnetization state, where fringe fields from the ferromagnet in the first magnetization state do not exceed a predetermined magnetic field in the superconductive pathway to convert at least a portion of the superconductive pathway to the normal state; where fringe fields from the ferromagnet in the second magnetization state exceed the predetermined magnetic field in the superconductive pathway to convert at least a portion of the superconductive pathway to the normal state.

Abstract: A multi-state Josephson memory in a superconductor integrated circuit includes a plurality of superconductive quantum interference device (SQUID) memory cells 2 each having a SQUID 4 characterized by a SQUID loop inductance L and a junction critical current I.sub.c, which determine the number of memory states that can be stored in the SQUID 4. A gate current I.sub.g is transmitted to the superconductive inductors 6 and 8 of the SQUID 4 to perform a read operation by crossing a designated number of current threshold boundaries corresponding to the memory state stored in the SQUID, so that the Josephson junction 12 of the SQUID 4 generates a number of pulses corresponding to the memory state. A control current I.sub.con writes data to the SQUID 4 through a control current input 16, and is preferably magnetically coupled to the SQUID 4 through superconductive inductor pairs 18, 6 and 20, 8. In a preferred embodiment, a plurality of SQUID memory cells 70a, 70b, . . .

Abstract: A three-terminal device constructed from a Josephson junction with one or more asymmetric control lines is disclosed. The device is constructed with high temperature superconducting materials. The junction can be a bicrystal, SNS (Superconducting-Normal-Superconducting) or any other type of high temperature superconductor junction. The control line is either a conducting or superconducting material which is electrically isolated from the junction but inductively coupled into the junction. A portion of the control line is approximately directly above the junction and has current which at least partially flows parallel or nonparallel to current flowing across the junction. The control line current alters the magnetic field within the junction which changes the critical current of the junction. The junction is in a superconducting or resistive state depending on whether the bias current of the junction is greater than or less than the control current.

Abstract: A superconducting fault-tolerant programmable read-only memory (SFT-PROM) cell stores information in the phases of superconducting wires in a Josephson array. The information is addressable and retrievable in a fault-tolerant manner due to the non local nature of the information stored. The coding and decoding process is content-addressable and parallel due to the multitude of interconnections, resulting in picosecond data access time. The SFT-PROM cell comprises superposed WRITE/READ arrays and a reset circuit that ensures multiple non-destructive read-out of data.

Abstract: A memory element for multiple bit storage uses a plurality of Josephson junction devices coupled in parallel between a ground plane and a superconductive line. A gate current is directly coupled to the superconductive line at a midpoint, and a control current is magnetically coupled to the superconductive line along its length. The current trajectory of the gate and control currents from an initial value to a quiescent point in the threshold curve traces determines the states of the modes. All the modes have a stable operating point at the quiescent point. The control current in the absence of the gate current is used to maintain the memory element at the quiescent point, and the gate current is used to momentarily transition none, one or more of the Josephson junction devices to a voltage state to determine the states of the modes at the quiescent point via appropriate Josephson sensors.

Abstract: A superconducting device may include a superconducting weak link equipped with plural superconducting devices that are used as input-output terminals formed on the same plane and at least one current source for applying current to at least one of these superconducting electrodes. A superconducting device suitable for high integration can be realized as it enables structuring of a superconducting weak link 1 equipped with plural superconducting electrodes 101, 102, 103 and 104 that can be used as input-output terminals and changing symmetry of superconducting electrode arrangement through the form of a normal conductor 201 which is forming a superconducting weak link. In addition, when this superconducting device is used as a quasi-particle injection type device, a superconducting device with plural superconducting electrodes that can be used for a gate electrode, drain electrode or control electrode can be realized. Further, a superconducting device equipped with new functions (e.g.

Abstract: A hybrid superconducting-semiconducting field effect transistor-like circuit element comprised of a superconducting field effect transistor and a closely associated cryogenic semiconductor inverter for providing signal gain is described. The hybrid circuit functions nearly as an ideal pass gate in cryogenic cross-bar applications.

Abstract: Superconducting-semiconducting hybrid memories are disclosed. These superconducting-semiconducting hybrid memories utilize semiconductor circuits to store information, and either superconducting or semiconducting or combinations of superconducting and semiconducting circuits, with at least some superconducting circuitry used, to write and read information. The state of memory cells in the hybrid memories is determined by utilizing superconductor current sensing schemes to detect currents in the bit-line, thereby avoiding any bit-line charging delays and other problems associated with purely semiconductor memories. Additional features of the superconducting-semiconducting hybrid memories include wide margins, dense packing of memory cells, low power dissipation and fast access times. Interface curcuitry for converting superconducting signals to signals compatible with semiconductor circuits and for converting semiconductor signals to signals compatible with superconducting circuits is also disclosed.

Abstract: A new type of superconducting memory is described. The composition of superconducting ceramic material used in the memory has been altered in order to expedite the formation of non-superconducting regions formed of grain boundaries. Non-superconducting regions may also be formed of lattice defects. Magnetic flux is trapped within the non-superconducting regions (grain boundaries or lattice defects). Information can be stored in terms of whether or not magnetic flux is trapped.

Abstract: A three-port Josephson memory cell has one input port (a data line) and two output ports (first and second sense lines). The memory cell receives a write enable pulse on a write line to store a bit of data from the data line as circulating supercurrent. The memory cell also receives a first read enable pulse on a first read line to enable assertion of the stored data onto the first sense line, and receives a second read enable pulse on a second read line to enable assertion of the stored data onto the second sense line.

Abstract: A quantum memory device in which a memory operation is enabled even if the structure of a Josephson device is reduced in size. Each memory cell of the quantum memory device includes a superconducting quantum interference device having two Josephson junctions, a write word line for supplying a current to the superconducting quantum interference device, a write data line and a magnetic field detection line magnetically coupled with the superconducting quantum interference device, a three-terminal switching device for turning a signal of the magnetic field detection line on and off to transfer the signal to a read data line, and a read word line connected to a gate of the three-terminal switching device. The junction area of the Josephson junction is made small to oscillate a magnetic flux so that information is stored in accordance with the phase of oscillation of the magnetic flux.

Abstract: A polarity-convertible Josephson driver circuit includes first and second driving voltage generating circuits, a driven line, and a load resistor. Each of the first and second driving voltage generating circuits has a loop circuit for forming at least one loop, the loop circuit being constituted by inductances and Josephson junctions so that a plurality of series-connected circuits each constituted by the inductances and the Josephson junctions are parallelly connected between an output point and a reference point, and a control line which has one terminal connected to an input point and the other terminal connected to the output point and is arranged to magnetically coupled to the loop circuit. The driven line connects the output points of the first and second driving voltage generating circuits to each other. A load resistor is inserted in the driven line.

Abstract: A magnetic memory cell including an information storage unit of a three-layer structure having two magnetic thin films and a non-magnetic thin film interposed between the two thin films, an X-direction conductor and a Y-direction conductor intersecting each other at a position of the information storage unit, and a sense conductor located at a side of the X-direction conductor opposite to the Y-direction conductor. The sense conductor is separated from the X-direction conductor and extending to overlap the X-direction conductor. The two magnetic thin films have an equal saturation magnetic flux amount and an uniaxial magnetic anisotropy in the film plane, but are different from each other in either one of a magnetic anisotropy and a coercive force. The X-direction conductor, the Y-direction conductor and the sense conductor are formed of a superconductor material, and the sense conductor has a Josephson junction (superconduction weak link) positioned above the information storage unit.

Abstract: One or more superconducting memory cells capable of storing binary values as the presence or absence of a persisting loop current in their superconducting memory loops are connected in series by a circuit current line. This arrangement is provided with a set gate which switches to the voltage state and outputs circuit current from its output terminal to one end of the circuit current line when write command current is supplied to its control terminal and is further provided with a sense gate whose control terminal is series coupled though a capacitance element with the same one end of the circuit current line and whose ground side terminal is connected with the other end of the circuit control line thereby forming through the sense gate a read-out loop for receiving as differential current persisting loop current selectively discharged from the memory loop. The differential current causes the sense gate to switch itself to the voltage state and output a sense current.

Abstract: A digital data memory unit and memory unit array, each unit of which can be searched in accordance with the contents thereof and updated, utilizes a digital storage element in the form of a register, latch, or memory cell, a comparator and control logic. Data is presented to the units in parallel on data lines and compare data is supplied in parallel to the units along other data lines. Parallel search of data in each unit, with multiple updates in units where the stored data matches the compare data, occurs rapidly and in one clock cycle (e.g., approximately 50 nanoseconds). The control logic responds to a match output from the comparator and an update enable pulse to enable a new data word on the data lines to be written into the digital storage element of the unit. The memory unit array is useful in image processing for storing pixel values and searching and updating these values in the process of image analysis to recognize certain images.

Abstract: Apparatus for selecting memory cells in a MOS memory array and reading data contained therein. Superconducting Josephson junction devices switch between a superconducting and voltage gap mode for rapid selection of an addressed memory cell row and column, and then read out of the selected memory cell data contained therein.

Abstract: A superconducting memory circuit includes a superconducting loop composed of first and second superconducting lines, and bias lines are connected to connection points of the first and second lines. Inductance or critical current values of the first and second lines are different from each other. When a current is supplied to the bias lines, the current is divided and flows in the loop to maintain a magnetic flux thereof at zero. If the current is further increased, a current flowing in one superconducting line reaches the critical current value of itself prior to the other superconducting line, and a larger current flows in the other superconducting line such that a superconducting state is not destroyed. Therefore, a magnetic flux is generated in the loop. If the current of the bias lines is shut-off in this state, a persistent current flows in the loop to maintain the magnetic flux. Thus, "1" can be written.

Abstract: Push-pull flux quantum superconducting digital logic circuits are provided with a circuit branch having a pair of Josephson junctions electrically connected in series with each other. This circuit branch is connected between positive and negative bias voltage supplies which supply a bias current to the Josephson junctions. A dual polarity input voltage signal is applied to a node in the circuit branch and an output signal is extracted from a second node in the circuit branch. Various logic operations can be performed on the input signal by adding additional components and changing the points at which voltage is input to and output from the Josephson junction circuit branch.

Abstract: A buffered nondestructive-readout Josephson memory cell comprises only three gates and is free of the half-select problem associated with Josephson memories, for both write and read operations. The basic memory cell unit comprises a first interferometer gate and an associated inductor defining a memory storage loop and a second interferometer gate that, together with a second inductor, defines a second loop in which a current pulse can be established only when a circulating current exists in the first loop. A third gate, responsive to a sense line and to the current pulse in the second loop, provides a voltage output which changes based upon whether a "1" or a "0" has been stored in the storage loop. For fabricating a bit-accessible memory, the third gate is further connected in closed circuit relationship with a third inductor which is magnetically coupled with the first gate.

Abstract: A manufacturing method for the thin film superconductor is disclosed in which photons having energies larger than ultraviolet rays are irradiated to the thin film superconductor on or after formation of the thin film. Further, manufacturing methods for superconductive magnetic memory, Josephson device and superconductive transistor are disclosed.

Abstract: A superconductor storage device and a memory constructed by arranging a plurality of superconductor storage devices are disclosed. The superconductor storage device is comprised of a word line, a write-in line, a first loop of superconductor composed of two branch paths of superconductor connected to the word line so as to allow a current flowing in the word line to be retained in the first loop, a weakly coupling portion inserted in at least one of the two branch paths, the weakly coupling portion being subject to the influence of a magnetic field generated by the write-in line to control the retention of the current in the first loop, and a second loop of normal conductor provided so as to be magnetically coupled with the first loop, the second loop including an input path and an output path which allow the application of a voltage to the second loop and two branch paths of normal conductor which makes a loop-wise connection between the input path and the output path.

Abstract: A family of logic circuits using nonhysteretic superconducting quantum interference devices (SQUIDs) connected together to perform various functions using a common operating principle. Each circuit has an output line, first and second power supply lines having first and second voltage states, and input lines that can have one of the two voltage states. A pull-up circuit, having at least one SQUID, is connected between the output line and the first power supply line, and the input lines are coupled to the pull-up circuit in such a manner as to pull the output line to the first voltage state only if the input lines conform with a selected combination of voltage states. A pull-down circuit, also having at least one SQUID, is connected between the output line and the second power supply line, to pull the output line to the second voltage state only when input lines do not conform with the selected combination of voltage states.

Abstract: This invention relates to a magnetic memory including a first superconductor wire, a second superconductor wire disposed in such a manner as to cross the first superconductor wire substantially orthogonally, a first magnetic film disposed at the point of intersection between the first and second superconductor wires and a second magnetic film interposed between the first magnetic film and the first or second superconductor films, wherein at least one of the uniaxial magnetic anisotropy within the plane of the films and coercive force of the first and second magnetic films is mutually different. Furthermore, a superconductor film containing a large number of microscopic Josephson junctions is disposed between the first and second magnetic films or on the other side of the superconductor wire connected to the magnetic film, and a lead wire for applying a current is connected to the superconductor film.

Abstract: A noble unit cell structure in a magnetic memory is disclosed, in which a ferromagnetic film is sandwiched between first and second wires at a cross-over area, and third and fourth wires are provided so as to sandwich the first wire. The third wire is contacted with the first wire so as to form a ring portion surrounding the ferromagnetic film and the second wire. The fourth wire is isolated from the first wire. At least the first, second and third wires are made of superconductive material. The ferromagnetic film has a uniaxial anisotropy along the second wire and its magnetization direction can be reversed by applying pulse currents to the second and fourth wires in an information writing process. In a reading process, the magnetization direction of the ferromagnetic film can be recognized by detecting either one of a superconductive state or a normal conductive state at the ring portion of the first and third wires.

Abstract: A process is disclosed of producing on a crystalline silicon substrate a barrier layer triad capable of protecting a rare earth alkaline earth copper oxide conductive coating from direct interaction with the substrate. A silica layer of at least 2000 .ANG. in thickness is deposited on the silicon substrate, and followed by deposition on the silica layer of a Group 4 heavy metal to form a layer having a thickness in the range of from 1500 to 3000 .ANG.. Heating the layers in the absence of a reactive atmosphere to permit oxygen migration from the silica layer forms a barrier layer triad consisting of a silica first triad layer located adjacent the silicon substrate, a heavy Group 4 metal oxide third triad layer remote from the silicon substrate, and a Group 4 heavy metal silicide second triad layer interposed between the first and third triad layers.

Abstract: A Josephson memory circuit driven by first, second and third clock signals includes a write circuit which holds data as a circulating current circulating in a superconducting closed loop including a Josephson junction. The data to be held is supplied thereto through a data line with timing of the third clock signal. A first OR circuit is supplied with a bias from a read bias line with timing of the second clock signal and supplied with the circulating current. The first OR circuit has a Josephson junction which is switched to a finite resistance state by the circulating current. A second OR circuit is supplied as a bias with output data form the first OR circuit with timing of the second clock signal and supplied with a read address signal from a read address line with timing of the first clock signal. The second OR circuit has a Josephson junction which is switched to a finite resistance state by the read address signal.

Abstract: A method of producing a Josephson junction device consisting of thin films of superconducting materials such as niobium and niobium nitride that work at cryogenic temperatures, in which a base electrode layer, tunnel barrier layer and a counterelectrode layer constituting a Josephson junction are formed on a substrate. In order to form a desired electrode pattern on the counterelectrode layer, a resist pattern is used as a mask for dry etching, followed by a plasma ashing process for ablating part of the resist in order to form a terrace-shaped portion at the edges and corners of the counterelectrode pattern by reforming and shrinking the cross-sectional geometry of the resist. Then, a thin insulating film for covering the edged layers is deposited over the entire surface of substrate, followed by the removal of said resist pattern together with said insulating film deposited on said resist pattern in order to form a protecting layer around the counterelectrode pattern.

Abstract: A superconducting switching circuit comprises a DCFP circuit composed of two Josephson junction elements constituting two current paths, respectively. Each of the current paths includes a resistor for suppressing resonance. A memory cell constituted by the DCFP circuit includes three Josephson junction elements constituting three current paths, respectively. Each of the current paths includes a resistor for suppressing resonance. A memory circuit comprises a number of memory cells of such a structure.

Abstract: The superconducting memory device comprises a thin type-II superconductor film for storing an Abrikosov vortex, a write control line for generating the vortex in the superconductor film, and a vortex detector for detecting a polarity of the vortex stored in the film. The vortex detector includes a Josephson junction and a read control current line. The Josephson junction comprises a base electrode, a counter electrode and a tunnel barrier region sandwiched between the base electrode and the counter electrode. By utilizing a fact that a shift direction of the threshold characteristics of the vortex detector corresponds to the polarity of the vortex stored in the superconductor film, a flux crossing the tunnel barrier region of the Josephson junction due to the stored vortex is detected by the read control line.

Abstract: An A.C. powered type logic array of very high speed operations which employs Josephson devices and which can program any desired logic. The logic array comprises a first logic array which delivers AND logic signals of desired ones of input signals, and a second logic array which delivers OR logic signals of desired ones of the AND outputs. Each of the first and second logic arrays comprises a plurality of bit lines which connect a plurality of arrayed Josephson devices in series at respective rows and each of which has one end connected to a power source and the other end grounded through a resistor, and word lines which are arranged in the column direction of the Josephson device array and which are selectively coupled to the Josephson devices. Whether or not the word lines are coupled to the respective Josephson devices of the arrays, is determined by the patterns of the word lines or the patterns of the Josephson devices, thereby to program the desired logic.

Abstract: Disclosed is a fluxoid type superconducting logic element essentially comprising a pair of SQUIDs connected with each other so as to put one of said SQUIDs into its "firing state" and the other into its "extinction state" in response to an input signal in the form of magnetic flux, thereby representing a binary digit at its output terminals.

Abstract: A Josephson memory circuit comprises a closed superconducting loop having a first node and including a first Josephson gate therein, and a first line connected to the node. The circuit also includes a second line provided to electromagnetically couple to the first Josephson gate, a second Josephson gate provided so close to the superconducting loop as to electromagnetically couple to the superconducting loop, and a third line connected to the second Josephson gate and provided to electromagnetically couple to the first Josephson gate.

Abstract: The invention is an all-soliton sampler for accessing very high speed circuits. A soliton is switched in two parallel branches, one including the device-under-test and the other including a programmable delay line implemented in soliton devices. The outputs of these two branches are used as controls to a soliton comparator which, in turn, controls a Josephson detector gate. This circuit permits a relatively slow rise time external trigger pulse to initiate an extremely narrow sampling pulse.

Abstract: A superconductive Josephson junction high density memory array is provided. Each memory cell in the array comprises a two branch superconducting interferometer storage loop which has only a single Josephson junction device in one of the branches. The Josephson junction devices are mounted on a substrate having a patterned ground plane. The ground plane pattern is provided with holes or apertures which surround the Josephson junction devices so that the control current of the control lines couple with the tunnel junctions of the Josephson junction devices but not with the ground plane. This structural arrangement provides a threshold characteristic for the single Josephson junction device which is symmetrical to the gate current, thus, may be easily switched to two current states indicative of two logic states.

Abstract: This invention discloses a decoder circuit utilizing Josephson devices where Josephson AND gates, output lines connecting both terminals of each said Josephson device and an input signal line are provided in as many as 2.sup.n in number in the nth stage of plural stages. The Josephson AND gate turns ON with the logical product (AND) of the current flowing into the output line of said Josephson AND gate of the preceding stage and the current flowing into the input signal line of the pertinent stage and causes a current to flow into the respective output line.

Abstract: Described is a DC powered flip-flop logic or memory element (i.e., circuit) which comprises two Josephson junction gates J.sub.1 and J.sub.2 which operate individually in the latching mode. In one logic state, the gate J.sub.1 is at V.sub.1 =O while J.sub.2 is at V.sub.2 .noteq.O. In the other logic state, the roles of the two junctions are reversed. The two junctions are interconnected by a passive network such that the switching of J.sub.2, say, from V.sub.2 =O to V.sub.2 .noteq.O induces a current-voltage transient on J.sub.1 which returns it to V.sub.1 =O, and conversely.

Abstract: This superconductive latch circuit uses superconductive switching devices and can be powered by the same phase of AC power used to power other circuits with which the latch is used. The latch is comprised of a storage loop including a superconductive switch and an inductor. It is also comprised of another superconductive switch through which an AC gate current can flow and whose state determines whether or not the AC current is delivered to the superconductive storage loop. Information is stored in the loop as the presence and absence of a circulating current of either polarity. In a variation of this latch, an output of the sense circuit which detects the state of the storage loop if fed back as a control signal to the superconductive switch in the storage loop and also as one input to an AND gate to which a SET signal is also applied. AC power is switched to the storage loop when both inputs to the AND circuit are simultaneously present.

Abstract: A Programmable Logic Array (PLA) system which utilizes Josephson devices and the noninverting capabilities of these devices is disclosed. The disclosed PLA system includes a personalized Read Only Memory (ROM) which is adapted to store the applied input signals as well as the output signals which are a logic function of the input signals. As soon as outputs from the ROM are available, an interface circuit which may be timed or untimed, inverting or noninverting provides output signals which can be utilized to drive other logic circuits or to act as inputs to another personalized Read Only Memory (ROM). The latter provides another logic function of the inputs at its outputs. Again, the outputs may be used directly or applied to another interface circuit which itself may provide inverted or noninverted outputs.Like the first mentioned ROM, the second mentioned ROM is capable of storing its inputs and the resulting outputs which are some logic function of the inputs as a result of the ROM personalization.

Abstract: A polarity switch which utilizes Josephson interferometers and low drive currents is disclosed. Single ended and double ended polarity switches which are electrically the same include a pair of circuits interconnected so that the application of a pair of signals to the circuits applies a current of one polarity or the other to a utilization circuit connected to the pair of circuits. Each of the pair of circuits includes a Josephson device which carries gate current; a current path shunting the device having a transformer secondary disposed serially in the path and another Josephson device serially disposed in the same current path. The transformer secondary is coupled to a primary through which a current is passed at the outset of the memory cycle. A current is induced in the current path of one of the pair of circuits which is in opposition to the gate current flowing in the Josephson device carrying that current.

Abstract: Decoder circuit arrangements for use with Josephson memory device arrays are disclosed. In one circuit of N stages, an input circuit consists of a Josephson junction and a shunting impedance connected across the junction by means of a matched transmission line. The transmission line has two output portions each of which controls the actuation or nonactuation of a pair of devices of circuits similar to the above-described circuit which are disposed in series in a pair of branches of a serially disposed superconducting loop of a first stage. Each branch has a serially disposed address gate to which true and complement address signals are applied. Each succeeding stage is similar to the first stage except that each branch of each succeeding stage contains twice as many circuits similar to the above-mentioned first stage circuit.

Abstract: Disclosure is made of a film cryotron comprising a super-conductive ground plane and two superconductive electrodes arranged on said ground plane. The ground plane and electrodes are all insulated from one another. The electrodes are interconnected by an elongated distributed Josephson junction and have input lines and a control line arranged along the Josephson junction and above one of the electrodes. The electrode under the control line is shaped as a strip extending along the Josephson junction. The input line is connected to this electrode at a point spaced from the points at which the control line intersects the boundaries of this electrode and from the ends of the junction at a distance which is greater than the width of said electrode and the depth of the magnetic field penetration into the junction. At the point of connection to the electrode, the input line has a width which is less than that of the electrode.

Abstract: A number of memory array configurations which avoid a spurious half-select condition in unselected cells of a superconducting memory array is disclosed. The memory arrays incorporate memory cells which include at least single Josephson junction disposed in a superconducting loop wherein binary information is stored in the form of at least one circulating current. By providing means for applying a control magnetic field to only the selected memory cell, spurious writing of an unselected memory cell is avoided. This is accomplished in a number of embodiments by causing the application of the half-select current (which normally provides the control magnetic field to a memory cell) to divert a previously applied half-select or enabling current to the memory cell into another path so that the previously applied half-select or enabling current now acts as a control current for switching the storage gate of the selected memory cell.

Abstract: A superconducting memory cell which includes a single Josephson junction or write gate disposed in a superconducting loop having improved sense margins is disclosed. The improved sense margins are achieved by fabricating the superconducting loop so that first and second branches thereof have different inductances. In a specific example, a first branch containing the single Josephson junction has the higher inductance. Still more specifically, the inductance of the first branch containing the Josephson junction or write gate is twice as great as the inductance of the other branch when the I.sub.min of the write gate is zero. In addition, another Josephson junction or sense gate must be disposed in electromagnetically coupled relationship with the second branch of the loop, and binary information must be stored in the form of clockwise and counterclockwise circulating currents of equal magnitude. Writing and reading are accomplished by coincident currents being applied to the cell.