Abstract: A DRAM whose operation is sped up and power consumption is reduced is provided. A pair of precharge MOSFETs for supplying a precharge voltage to a pair of input/output nodes of a CMOS sense amplifier is provided; the pair of input/output nodes are connected to a complementary bit-line pair via a selection switch MOSFET; a first equalize MOSFET is provided between the complementary bit-line pair for equalizing them; a memory cell is provided between one of the complementary bit-line pair and a word line intersecting with it; gate insulators of the selection switch MOSFETs and first equalize MOSFET are formed by first film thickness; a gate insulator of the precharge MOSFET is formed by second film thickness thinner than the first film thickness; a precharge signal corresponding to a power supply voltage is supplied to the precharge MOSFET; and an equalize signal and a selection signal corresponding to a boost voltage are supplied to the first equalize MOSFET and the selection switch MOSFET, respectively.

Abstract: A multibit electro-mechanical memory device capable of increasing an integrated level of memory devices, and a method of manufacturing the same, are provided. The memory device includes a substrate, a bit line on the substrate; a lower word line and a trap site isolated from the bit line, a pad electrode isolated from a sidewall of the trap site and the lower word line and connected to the bit line, a cantilever electrode suspended over a lower void in an upper part of the trap site, and connected to the pad electrode and curved in a third direction vertical to the first and second direction by an electrical field induced by a charge applied to the lower word line, a contact part for concentrating a charge induced from the cantilever electrode thereon in response to the charge applied from the lower word line and the trap site, the contact part protruding from an end part of the cantilever electrode, and an upper word line formed with an upper void on the cantilever electrode.

Abstract: A microelectronic switch having a substrate layer, an electrically conductive switching layer formed on the substrate layer, an electrically conductive cavity layer formed on the switching layer, an electrically conductive cap layer formed on the cavity layer, the cap layer forming a first electrode and a second electrode that are physically and electrically separated one from another, and which both at least partially overlie the switching layer, and a cavity disposed between the switching layer and the second electrode, where the switching is layer is flexible to make electrical contact with the second electrode by flexing through the cavity upon selective application of an electrical bias.

Abstract: A non-volatile memory cell includes a volatile storage device that stores a corresponding logic state in response to electrical stimulus; and a shadow memory device coupled to the volatile storage device. The shadow memory device receives and stores the corresponding logic state in response to electrical stimulus. The shadow memory device includes a non-volatile nanotube switch that stores the corresponding state of the shadow device.

Abstract: There are provided a multi-bit electromechanical memory device capable of enhancing or maximizing a degree of integration of the memory device and a method of manufacturing the multi-bit electromechanical memory device which includes a substrate, a bit line on the substrate, and extending in a first direction; a word line on the bit line, insulated from the bit line, and extending in a second direction transverse to the first direction, and a cantilever electrode including a shape memory alloy. The cantilever electrode has a first portion electrically connected to the bit line and a second portion extending in the first direction, and spaced apart from the word line by an air gap, wherein the cantilever electrode, in a first state, is in electrical contact with the word line, and, in a second state, is spaced apart from the word line.

Abstract: A memory device includes a bit line, a first word line, a bit line contact, an electrode, a second word line and a contact tip. The bit line may extend along a first direction. The first word line is formed over the bit line and extends in a second direction. The bit line contact is formed between adjacent first word lines. The bit line contact may have an upper face substantially higher than the first word lines. The electrode contacting with the bit line contact may include an elastic material bending by an electric field among the electrode, the first word line and the second word line. The second word line is disposed over the electrode and corresponds to at least one of the first word lines. The contact tip formed at a lateral portion of the electrode may protrude toward the first and the second word lines.

Abstract: A nanomechanical device includes a nanostructure, such as a MWNT, located between two electrodes. The device switches from an OFF state to an ON state by extension of at least one inner shell of the nanostructure relative to at least one outer shell of the nanostructure upon an application of a voltage between the electrodes. If desired, the device may also switch from the ON state to the OFF state upon an application of a gate voltage to a gate electrode located adjacent to the nanostructure.

Abstract: Nanoelectromechanical (NEM) memory cells are provided by anchoring a conductive nanometer-scale beam (e.g., a nanotube) to a base and allowing a portion of the beam to move. A charge containment layer is provided in the vicinity of this free-moving portion. To read if a charge is stored in the charge containment layer, a charge is formed on the beam. If a charge is stored then forces between the charged beam and the charge containment layer will displace the free-moving portion of the beam. This movement may be sensed by a sense contact. Alternatively, the beam may contact a sense contact at an ambient frequency when no charge is stored. Changing the amount of charge stored may change this contact rate. The contract rate may be sensed to determine the amount of stored charge.

Abstract: A memory cell uses a pair of cantilevers to store a bit of information. Changing the relative position of the cantilevers determines whether they are electrically conducting or not. The on and off state of this mechanical latch is switched by using, for example, electrostatic, electromagnetic or thermal forces applied sequentially on the two cantilevers to change their relative position. The amount of power required to change the state of the cell is reduced by supporting at least one of the cantilevers with at least one lateral projection that is placed in torsion during cantilever displacement. After a bit of data is written, the cantilevers are locked by mechanical forces inherent in the cantilevers and will not change state unless a sequential electrical writing signal is applied. The sequential nature of the required writing signal makes inadvertent, radiation or noise related data corruption unlikely.

Abstract: In a memory device and a method of manufacturing the memory device, the memory device includes first and second electrode patterns formed on a substrate. An insulating layer pattern and a third electrode pattern are successively formed on the substrate. The third electrode pattern extends to be apart from upper faces of the first and second electrode patterns by a first distance. A fourth electrode pattern extending from a lower portion of the third electrode to inside an opening defined between the first and second electrode patterns is formed to be apart from the first and second electrode patterns, the insulating layer pattern and the substrate. The fourth electrode pattern is formed toward the substrate and includes a rounded end portion.

Abstract: An electromechanical storage device includes an input element that facilitates the input of data, a series of data elements, and a terminating element that facilitates the reading out of data. The data elements each have at least two stable mechanical orientations, and these orientations can be utilized to store data. Data may be entered into the device by applying a transient electromagnetic pulse to the data elements. The device is constructed such that as a data bit is entered into the series of data elements, any data bits that have been previously entered into the series are shifted towards the terminating element.

Abstract: A circuit includes a micro electro mechanical switch and a detection circuit. The micro electro mechanical switch has a movable portion positioned to form an electrical connection between a first electrical contact and a second electrical contact in response to an electrostatic force provided by a top activation electrode and a bottom activation electrode. The detection circuit is electrically coupled to the top and bottom activation electrodes and is for detecting a first capacitance value between the top and bottom activation electrodes when the movable portion is in a first position and for detecting a second capacitance value when the movable portion is in a second position. By detecting a change in the capacitance, it can be determined if the switch is open or closed.

Abstract: Circuit arrays having cells with combinations of transistors and nanotube switches. Under one embodiment, a circuit array includes a plurality of cells arranged in an organization of words, each word having a plurality of bits. Each cell is responsive to a bit line, word line, reference line, and release line. Bit lines are arranged orthogonally relative to word lines and each word line and bit line are shared among a plurality of cells. Each cell is selectable via the activation of the bit line and word line. Each cell includes a field effect transistor coupled to a nanotube switching element. The nanotube switching element is switchable to at least two physical positions at least in part in response to electrical stimulation via the reference line and release line. Information state of the cell is non-volatilely stored via the respective physical position of the nanotube switching element.

Abstract: Nanotube-based switching elements and logic circuits. Under one embodiment of the invention, a switching element includes an input node, an output node, a nanotube channel element having at least one electrically conductive nanotube, and a control electrode. The control electrode is disposed in relation to the nanotube channel element to controllably form an electrically conductive channel between the input node and the output node. The channel at least includes said nanotube channel element. The output node is constructed and arranged so that channel formation is substantially unaffected by the electrical state of the output node. Under another embodiment of the invention, the control electrode is arranged in relation to the nanotube channel element to form said conductive channel by causing electromechanical deflection of said nanotube channel element.

Abstract: To store information in a ferroelectric material, a sample probe is used to bring about mechanical action on individual domains and thereby to cause a reversal of polarization in the individual domains, with electrodes situated below the ferroelectric material being able to have a bias applied to them to stabilize the change/reversal of polarization. The reversal of polarization causes an alteration in the surface topography of the ferroelectric material, and this alteration can be used to read the information. The stored information is therefore obtained by ascertaining the surface topography of the ferroelectric material. The information is written and read using an AFM tip, with the tip being able to be operated in contact or tapping mode for the purpose of writing, and additionally in noncontact mode for the purpose of reading.

Abstract: A random access memory cell includes first and second nanotube switching elements and an electronic memory with cross-coupled first and second inverters. Each nanotube switching element includes a nanotube channel element having at least one electrically conductive nanotube, and a set electrode and a release electrode disposed in relation to the nanotube channel element to controllably form and unform an electrically conductive channel between a channel electrode and an output node. Input nodes of the first and second inverters are coupled to the set electrodes and the output nodes of the first and second nanotube switching elements. The cell can operate as a normal electronic memory, or in a shadow memory or store mode to transfer the electronic memory state to the nanotube switching elements. The device may later be operated in a recall mode to transfer the state of the nanotube switching elements to the electronic memory.

Abstract: As part of anti-fuse circuitry for a memory device, a preferred exemplary embodiment of the current invention provides a direct connection between an anti-fuse and a contact pad used to provide voltage to that anti-fuse. The contact pad also serves as a voltage source for at least one other part of the memory device. At least one circuit coupled to the anti-fuse is temporarily isolated from it in the event that a voltage present at the pad would damage the circuit or cause the circuit to improperly read the status of the anti-fuse. The contact pad is available during a probe stage of the in-process memory device, but once the device is packaged, access to that contact pad is prevented. At the back end of the production process, the anti-fuse may be accessed through a second pad, whose electrical communication with the anti-fuse is regulated.

Abstract: The present invention provides an organic bistable device for use in non-volatile memories. The organic bistable device comprises a first and a second metal electrode sandwiching a first and a second organic layer with a metal-nanocluster layer positioned between the first and second organic layers. The device further comprises a first electron blocking layer positioned between the metal-nanocluster layer and one of the metal electrodes. This structure provides an organic bistable device with improved charge retention characteristics.

Abstract: As part of anti-fuse circuitry for a memory device, a preferred exemplary embodiment of the current invention provides a direct connection between an anti-fuse and a contact pad used to provide voltage to that anti-fuse. The contact pad also serves as a voltage source for at least one other part of the memory device. At least one circuit coupled to the anti-fuse is temporarily isolated from it in the event that a voltage present at the pad would damage the circuit or cause the circuit to improperly read the status of the anti-fuse. The contact pad is available during a probe stage of the in-process memory device, but once the device is packaged, access to that contact pad is prevented. At the backend of the production process, the anti-fuse may be accessed through a second pad, whose electrical communication with the anti-fuse is regulated.

Abstract: Nanoelectromechanical (NEM) memory cells are provided by anchoring a conductive nanometer-scale beam (e.g., a nanotube) to a base and allowing a portion of the beam to move. A charge containment layer is provided in the vicinity of this free-moving portion. To read if a charge is stored in the charge containment layer, a charge is formed on the beam. If a charge is stored then forces between the charged beam and the charge containment layer will displace the free-moving portion of the beam. This movement may be sensed by a sense contact. Alternatively, the beam may contact a sense contact at an ambient frequency when no charge is stored. Changing the amount of charge stored may change this contact rate. The contract rate may be sensed to determine the amount of stored charge.

Abstract: A semiconductor memory device includes a plurality of MIS transistors arranged at intersections of first word lines and bit lines formed on an SOI substrate and each configuring a memory cell. Each of the plurality of MIS transistors includes a channel body formed in a semiconductor layer on an insulating film and set in an electrically floating state, a first extension region formed in contact with the channel body in the semiconductor layer and arranged in a first word line direction, a gate insulating film formed on the channel body, a gate electrode formed on the gate insulating film and electrically connected to a corresponding one of the first word lines, and source and drain regions separately formed in a bit line direction in the semiconductor layer to sandwich the channel body.

Abstract: In a semiconductor memory device composed of a semiconductor chip and overlaid to a surface of another semiconductor chip so as to connect together, a control circuit provided in the semiconductor memory device is provided with a chip connector portion having a plurality of pads. The chip connector portion is formed to have a configuration corresponding to the maximum capacity of the memory cell array provided in the semiconductor memory device, and the location and the number of the pads are invariably determined even when the memory cell array has a capacity less than the maximum capacity. The control circuit incorporating the chip connector portion is also invariably determined so as to control reading and writing data from and into the memory cell array having the maximum capacity, regardless of the capacity of the memory cell array provided.

Abstract: A phase change memory includes a temperature sensor having a resistance variable with temperature with the same law as a phase-change storage element. The temperature sensor is formed by a resistor of chalcogenic material furnishing an electrical quantity that reproduces the relationship between the resistance of a phase change memory cell and temperature; the electrical quantity is processed so as to generate reference quantities as necessary for writing and reading the memory cells. The chalcogenic resistor has the same structure as a memory cell and is programmed with precision, preferably in the reset state.

Abstract: A molecular light valve mechanism is used for imaging on an adjacent pixel-patterned construct. An electrical fringe field or through field is used to transform targeted pixels by switching light valve molecules between a first non-transparent state and transparent state, providing information content on the adjacent pixel-patterned imaging layer.

Abstract: A memory cell for magnetic random access memory devices based on a magnetic tunnel junction (MTJ) memory element with a perpendicular orientation of magnetization in pinned and free magnetic layers, and a tunnel barrier layer sandwiched between the pinned and free layers. The memory cell can include the MTJ memory element, a magnetic flux guide in series with selection devices, such as a bit line, a word line, and a transistor. The magnetic flux guide can have two electrically conductive magnetic portions with the MTJ memory element positioned between the magnetic portions. The MTJ memory element is magnetically isolated from the magnetic flux guide by thin non-magnetic conductive spacers. The MTJ memory element is arranged in a vertical space between the intersecting bit and word lines at their intersection region. The memory cell also includes write and excitation lines. The write line is parallel to the bit line and the excitation line is parallel to the word line.

Abstract: MTJ elements are accumulated in a plurality of portions on a semiconductor substrate. A first conductive line functioning as a read line and extending in the X direction is connected to pin layers of the MTJ elements. A second conductive line functioning as a write line and read line and extending in the X direction is connected to free layers of the MTJ elements. A write line extends in the Y direction and is shared with two MTJ elements present above and below the write line. The two MTJ elements present above and below the write line are arranged symmetric to the write line.

Abstract: A write circuit structure may be used to transfer data between global bit lines and local bit lines of a cache. The write circuit structure located between the hierarchical bit lines may be buffers in parallel with P-channel devices in one embodiment or cross-coupled P-channel and N-channel devices in another embodiment.

Abstract: A memory device wherein a diode is serially connected to a programmable resistor and is in electrical communication with a buried digit line. An electrically conductive plug is electrically interposed between the digit line and a strapping layer, thereby creating a double metal scheme wherein the strapping layer is a second metal layer overlying metal wordlines. In a method of a first embodiment the strapping material is electrically connected to the digit line through a planar landing pad overlying the conductive plug. An insulative material is sloped to the planar landing pad in order to provide a surface conducive to the formation of the strapping material.

Abstract: A micromechanical memory 100 element comprising a deflectable member 102 located between a first member 104 and a second member 106. The first member 104 is biased at a first member voltage, and the second member 106 is biased at a second member voltage. A bias voltage applied to the deflectable member will drive the deflectable member to either the first member 104 or the second member 106. A first contact 108 is positioned on the top, or end, of the first member 104. A second contact 110 is positioned on the top, or end, of the second member 106. These contacts are biased through resistors 112 and 114 with a first and second contact voltage sufficient to hold the deflectable member in place even after removal of the bias voltage applied to the deflectable member. The state of the micromechanical memory element can be determined by sensing the voltage of the deflectable member 102.

Abstract: A memory cell which provides a diffusion path for hydrogen to the transistor is disclosed. The diffusion path is provided by forming a contact in which the upper section overlaps the lower section, thus creating a gap that serve as a hydrogen diffusion path. The hydrogen diffusion path is necessary for annealing the damage to the gate oxide.

Abstract: A memory device wherein a diode is serially connected to a programmable resistor and is in electrical communication with a buried digit line. An electrically conductive plug is electrically interposed between the digit line and a strapping layer, thereby creating a double metal scheme wherein the strapping layer is a second metal layer overlying metal wordlines. In a method of a first embodiment the strapping material is electrically connected to the digit line through a planar landing pad overlying the conductive plug. An insulative material is sloped to the planar landing pad in order to provide a surface conducive to the formation of the strapping material.

Abstract: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

Abstract: A low power, nonvolatile microelectromechanical memory cell stores data. This memory cell uses a pair of cantilevers, to store a bit of information. The on and off state of this mechanical latch is switched by using, for example, electrostatic forces applied sequentially on the two cantilevers. The cantilevers are partially overlapping. Changing the relative position of the cantilevers determines whether they are electrically conducting or not. One state represents a logical “1”. The other state represents a logical “0”. After a bit of data is written, the cantilevers are locked by mechanical forces inherent in the cantilevers and will not change state unless a sequential electrical writing signal is applied. The sequential nature of the required writing signal makes inadvertent or noise related data corruption highly unlikely. This MEMS memory cell can be implemented, for example, using a three-polysilicon-layer surface micro-machining process.

Abstract: A memory device wherein a diode is serially connected to a programmable resistor and is in electrical communication with a buried digit line. An electrically conductive plug is electrically interposed between the digit line and a strapping layer, thereby creating a double metal scheme wherein the strapping layer is a second metal layer overlying metal wordlines. In a method of a first embodiment the strapping material is electrically connected to the digit line through a planar landing pad overlying the conductive plug. An insulative material is sloped to the planar landing pad in order to provide a surface conducive to the formation of the strapping material.

Abstract: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

Abstract: Main word lines are shifted in the width direction in a memory array to generate an empty region formed by a shift-aside region. The width of a conductive interconnection line transmitting a desired signal/voltage is increased in this region. Accordingly, the width of the signal/voltage interconnection line is increased to reduce the resistance without increase in the array occupation area.

Abstract: System and method for writing/reading data, the method including the steps of causing polarization inversion at domains of the ferroelectric thin film using a conductive nano tip for writing the data, and reading the data using a non-conductive nano tip.

Abstract: A method of fabricating a complex IC in two parts and making the electrical connections between them afterwards is described. By this method, a ferroelectric RAM is fabricated in two parts, where the first part has an array of unit cells each of those has a transistor or a group of transistors serving the purpose of selecting one address for data recording and has an array of electrically conductive pads facing upward, protruding out from the surface of the first part, where the second part consists of a data-recording layer on another substrate. The data-recording layer consists of ferroelectric material and is pressed on the first part during data writing and reading.

Abstract: A micro needle probe apparatus that includes a probe and its associated electronic circuit. The electronic circuit is formed in a substrate and includes at least one metal interconnection layer. The probe is cantilevered over the electronic circuit and is composed of a metal probe arm, a support post that anchors one end of the probe arm to the substrate, and a micro needle mounted adjacent the moveable end of the probe arm. The probe apparatus may be used as the read/write mechanism of the moving-medium type memory device.

Abstract: The read only memory has a plurality of conductor track planes one above the other. The conductor tracks in adjacent planes are oriented such that they intersect in intersecting regions. In these intersecting regions, either a VIA tunnel contact is provided, which represents a logic "1" or no VIA tunnel contact is provided, so that this intersecting region represents a logic "0". In this way, over the same surface area, a plurality of memory cells can be produced one above the other. The read only memory is produced with a defined sequence of process steps and it is operated by selectively applying predetermined voltages across the various conductor tracks.

Abstract: A memory device that comprises a planar memory medium and a probe device mounted opposite the planar memory medium. The probe device includes a substrate having a substrate surface and probe cells arrayed on the substrate surface. Each of the probe cells comprises a probe, an auxiliary electrode and a probe driving circuit. The probe is formed in the substrate, includes part of the substrate surface, and additionally includes a conductive needle projecting towards the memory medium. The conductive needle includes a needle tip adjacent the memory medium. The auxiliary electrode is mounted on the probe, and is located between the probe and the memory medium. The auxiliary electrode is disposed substantially parallel to, and spaced from, the substrate surface. The driving circuit is formed in the substrate and projects from the substrate surface towards the memory medium. The probe driving circuit has outputs electrically connected to the auxiliary electrode and the memory medium.

Abstract: The integrated circuit tolerant of large manufacturing defects comprising a first plurality of first conductors made of a first material with relatively low conductivity and each having a plurality of first electrical connection points arranged along itself and a second corresponding plurality of second conductors made of a second material with relatively high conductivity and each having a plurality of second electrical connection points arranged along itself and said plurality of first points are electrically connected to said plurality of second points respectively in such a manner as to reduce the series resistance of the first conductors and the second conductors are interrupted between some second consecutive points in such a manner as to leave relatively large areas of the integrated circuit not traversed by the second conductors.

Abstract: A PC card comprising a housing having side surfaces and a connector surface communicating with the side surfaces, contact holes mated with contact pins of a multipin connector and contact pins of a standard pin connector alike and formed on the connector surface, and additional contact holes mated with the contact pins of the multipin connector and formed on the contact surface. The PC card is usable for and interchangeable between a personal computer having a standard pin connector.