Ion Implantation Patents (Class 365/178)
  • Patent number: 8958234
    Abstract: An electronic device includes a first electrode, a second electrode and a solid electrolyte having a base of an ion conducting material. The device remains in the highly resistive state for as long as a first threshold voltage between the first electrode and the second electrode is not reached. The device switches from the state of high resistance to the state of low resistance when the potential difference between the first electrode and the second electrode is equal to or greater than the first threshold voltage. The device switches from the state of low resistance to the state of high resistance when the potential difference between the first electrode and the second electrode equal to or greater than this first threshold voltage is removed and as it decreases it reaches a second positive voltage threshold strictly lower than the first threshold voltage.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: February 17, 2015
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventor: Jean-Fran├žois Nodin
  • Patent number: 8735964
    Abstract: An apparatus is provided which includes an array of impurity ions disposed in an insulating region, a semiconductor region adjacent to the insulating region, an array of electrometers arranged to detect charge carriers in the semiconductor region and an array of sets of at least one control gate configured to apply an electric field to the insulating region and semiconductor region. Each control gate is operable to cause at least one charge carrier in the semiconducting material region to bind to the impurity ion without the at least one charge carrier leaving the semiconductor material region. The electrometers are operable to detect whether the at least one charge carrier is bound to the impurity ion.
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: May 27, 2014
    Assignee: Hitachi, Ltd.
    Inventor: Thierry Ferrus
  • Patent number: 8599608
    Abstract: The present disclosure includes GCIB-treated resistive devices, devices utilizing GCIB-treated resistive devices (e.g., as switches, memory cells), and methods for forming the GCIB-treated resistive devices. One method of forming a GCIB-treated resistive device includes forming a lower electrode, and forming an oxide material on the lower electrode. The oxide material is exposed to a gas cluster ion beam (GCIB) until a change in resistance of a first portion of the oxide material relative to the resistance of a second portion of the oxide material. An upper electrode is formed on the first portion.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: December 3, 2013
    Assignee: Micron Technology, Inc.
    Inventors: John A. Smythe, Jr., Gurtej S. Sandhu
  • Patent number: 8558332
    Abstract: A method of fabricating a spin-current switched magnetic memory element includes providing a wafer having a bottom electrode, forming a plurality of layers, such that interfaces between the plurality of layers are formed in situ, in which the plurality of layers includes a plurality of magnetic layers, at least one of the plurality of magnetic layers having a perpendicular magnetic anisotropy component and including a current-switchable magnetic moment, and at least one barrier layer formed adjacent to the plurality of magnetic layers, lithographically defining a pillar structure from the plurality of layers, and forming a top electrode on the pillar structure.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: October 15, 2013
    Assignee: International Business Machines Corporation
    Inventors: Jonathan Zanhong Sun, Rolf Allenspach, Stuart Stephen Papworth Parkin, John Casimir Slonczewski, Bruce David Terris
  • Patent number: 8498164
    Abstract: An integrated circuit can include at least one programmable metallization cell (PMC) comprising an ion conducting material and a metal dissolvable in the ion conducting material, selectively connected to a shunt node; and a biasing circuit comprising a current source coupled to the shunt node configurable to provide a first current in a first type operation, and a voltage regulator coupled to the shunt node configured to regulate a potential at the shunt node; wherein in the first type operation, the voltage regulator shunts current with respect to the shunt node in a same direction as a current flow of the at least one PMC.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: July 30, 2013
    Assignee: Adesto Technologies Corporation
    Inventors: Shane Charles Hollmer, Nad Edward Gilbert
  • Patent number: 8369132
    Abstract: A method can include programming a selected programmable metallization cell (PMC) by coupling the anodes of a group of PMCs to a first power supply voltage and connecting a cathode of one of PMCs of the group to a second power supply voltage with a select device; and erasing a selected PMC by coupling the anodes of a group of PMCs to the second power supply voltage and connecting the cathode of one of PMCs of the group to the first supply voltage with the select device.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: February 5, 2013
    Assignee: Adesto Technologies Corporation
    Inventors: Shane Charles Hollmer, Nad Edward Gilbert
  • Patent number: 8274842
    Abstract: An integrated circuit may include: access circuits that couple first electrodes of a plurality of programmable metallization cells (PMC) to access paths in parallel, each PMC comprising a solid ion conducting material formed between the first electrode and a second electrode; a plurality of write circuits, each coupled to a different access path, and each coupling the corresponding access path to a first voltage in response to input write data having a first value and to a second voltage in response to the input write data having a second value; and a node setting circuit that maintains second electrodes of the PMCs at a substantially constant third voltage while write circuits couple the access paths to the first or second voltages.
    Type: Grant
    Filed: September 25, 2009
    Date of Patent: September 25, 2012
    Assignee: Adesto Technologies Corporation
    Inventors: Shane Charles Hollmer, Nad Edward Gilbert, John Dinh
  • Patent number: 8223539
    Abstract: The present disclosure includes GCIB-treated resistive devices, devices utilizing GCIB-treated resistive devices (e.g., as switches, memory cells), and methods for forming the GCIB-treated resistive devices. One method of forming a GCIB-treated resistive device includes forming a lower electrode, and forming an oxide material on the lower electrode. The oxide material is exposed to a gas cluster ion beam (GCIB) until a change in resistance of a first portion of the oxide material relative to the resistance of a second portion of the oxide material. An upper electrode is formed on the first portion.
    Type: Grant
    Filed: January 26, 2010
    Date of Patent: July 17, 2012
    Assignee: Micron Technology, Inc.
    Inventors: John Smythe, Gurtej S. Sandhu
  • Patent number: 8107273
    Abstract: An integrated circuit may include multiple programmable metallization cells (PMCs) and a multiple bit lines. Each bit line may be connected to a anodes of a different set of PMCs, and provide a read data path from a selected one of the set of PMCs. Access devices may each provide a controllable impedance path between at least one cathode and a common source node.
    Type: Grant
    Filed: July 23, 2009
    Date of Patent: January 31, 2012
    Assignee: Adesto Technologies Corporation
    Inventors: Shane Charles Hollmer, Nad Edward Gilbert
  • Patent number: 7902611
    Abstract: An integrated circuit is provided with transistor body regions that may be independently biased. Some of the bodies may be forward body biased to lower threshold voltages and increase transistor switching speed. Some of the bodies may be reverse body biased to increase threshold voltages and decrease leakage current. The integrated circuit may be formed on a silicon substrate. Body bias isolation structures may be formed in the silicon substrate to isolate the bodies from each other. Body bias isolation structures may be formed from shallow trench isolation trenches. Doped regions may be formed at the bottom of the trenches using ion implantation. Oxide may be used to fill the trenches above the doped region. A deep well may be formed under the body regions. The deep well may contact the doped regions that are formed at the bottom of the trenches.
    Type: Grant
    Filed: November 27, 2007
    Date of Patent: March 8, 2011
    Assignee: Altera Corporation
    Inventors: Irfan Rahim, Bradley Jensen, Peter J. McElheny
  • Patent number: 7289350
    Abstract: The present invention relates to an electronic device comprising a memory cell with a resistive storage element having a first terminal and a second terminal. The resistive storage element can be switched between a first storage state with a first conductivity and a second storage state with a second conductivity. An access switch is coupled to the first terminal of the resistive storage element and to a node for connecting the first terminal of the resistive storage element to the node in an access state of the memory cell and for insulating the first terminal of the resistive storage element from the node in an idle state of the memory cell. A protecting switch is connected to the resistive storage element. The protecting switch, in the idle state of the memory cell, reduces the voltage across the resistive storage element produced by electromagnetic interference and, in the access state of the memory cell, enables the reading and the writing of the storage states of the resistive storage element.
    Type: Grant
    Filed: April 5, 2005
    Date of Patent: October 30, 2007
    Assignee: Infineon Technologies AG
    Inventor: Thomas Roehr
  • Patent number: 7221599
    Abstract: Systems and methodologies are provided for activating a polymer memory cell(s) after production by subjecting the polymer memory cell to an electrical field, for an initialization thereof. Such initialization can facilitate the distribution and mobility of metal ions (or charged metallic molecules) within an active layer of the polymer memory cell. The memory cell can include various layers of alternating passive and active media, which are sandwiched between conducting electrode layers.
    Type: Grant
    Filed: November 1, 2004
    Date of Patent: May 22, 2007
    Assignee: Spansion, LLC
    Inventors: David Gaun, Juri H Krieger, Stuart Spitzer
  • Patent number: 7164597
    Abstract: A two-transistor SRAM cell includes a first FET. The first FET is an ultrathin FET of a first polarity type and includes a control electrode, a first load electrode and a second electrode. The first load electrode is coupled to a first control line. The SRAM cell also includes a second FET. The second FET is an ultrathin FET of a second polarity type and includes a gate, a source and a drain. The second FET source is coupled to the first FET gate. The second FET gate is coupled to the first FET drain and the second FET source is coupled to a first potential. The SRAM cell further includes a first load device that is coupled between a second potential and the first FET gate. The SRAM cell additionally includes a second load device coupled between the second FET gate and a second control line.
    Type: Grant
    Filed: August 5, 2005
    Date of Patent: January 16, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Leonard Forbes
  • Patent number: 6780653
    Abstract: The invention includes a construction comprising an MRAM device between a pair of conductive lines. Each of the conductive lines can generate a magnetic field encompassing at least a portion of the MRAM device. Each of the conductive lines is surrounded on three sides by magnetic material to concentrate the magnetic fields generated by the conductive lines at the MRAM device. The invention also includes a method of forming an assembly containing MRAM devices. A plurality of MRAM devices are formed over a substrate. An electrically conductive material is formed over the MRAM devices, and patterned into a plurality of lines. The lines are in a one-to-one correspondence with the MRAM devices and are spaced from one another. After the conductive material is patterned into lines, a magnetic material is formed to extend over the lines and within spaces between the lines.
    Type: Grant
    Filed: June 6, 2002
    Date of Patent: August 24, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Hasan Nejad, James G. Deak
  • Patent number: 6777757
    Abstract: A programmable memory cell comprised of a transistor located at the crosspoint of a column bitline and a row wordline is disclosed. The transistor has its gate formed from the column bitline and its source connected to the row wordline. The memory cell is programmed by applying a voltage potential between the column bitline and the row wordline to produce a programmed n+ region in the substrate underlying the gate of the transistor.
    Type: Grant
    Filed: April 26, 2002
    Date of Patent: August 17, 2004
    Assignee: Kilopass Technologies, Inc.
    Inventors: Jack Zezhong Peng, David Fong
  • Publication number: 20040071014
    Abstract: A plurality of bit lines are divided into a plurality of groups each including Y (Y: integer of at least two) bit lines. Y data read data lines passing a data read current therethrough in data reading are provided along with Y connection control parts electrically coupling Y bit lines and the Y read data lines with each other every group. Therefore, the connection control parts electrically connected with the Y read data lines are uniformly divided so that parasitic capacitance applied to the read data lines following electrical connection with the connection control parts can be suppressed. Therefore, the time for charging the read data lines to a prescribed voltage level can be reduced for executing high-speed data reading.
    Type: Application
    Filed: March 27, 2003
    Publication date: April 15, 2004
    Applicants: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Engineering Company, Limited
    Inventors: Hiroaki Tanizaki, Takaharu Tsuji, Hideto Hidaka
  • Patent number: 6716727
    Abstract: Methods and apparatus are provided for plasma doping and ion implantation in an integrated processing system. The apparatus includes a process chamber, a beamline ion implant module for generating an ion beam and directing the ion beam into the process chamber, a plasma doping module including a plasma doping chamber that is accessible from the process chamber, and a wafer positioner. The positioner positions a semiconductor wafer in the path of the ion beam in a beamline implant mode and positions the semiconductor wafer in the plasma doping chamber in a plasma doping mode.
    Type: Grant
    Filed: October 26, 2001
    Date of Patent: April 6, 2004
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventor: Steven R. Walther
  • Patent number: 6636433
    Abstract: An electronic device of the present invention includes a memory core formed on an insulative substrate and implemented by a substance that performs, when a current flows therethrough, electromigration and varies in at least part of its shape or at least part of its element composition ratio. Two electrodes are directly bonded to opposite ends of the memory core. A sense electrode is spaced from the memory core by a thin insulative film in the vicinity of one of the two electrodes. A current flowing through the memory core causes a diffusion element to concentrate around either one of the two electrodes, whereby data is written in the memory core. Charge migration from the sense electrode caused by the migration of the diffusion element is sensed to thereby read the data out of the memory core.
    Type: Grant
    Filed: March 7, 2001
    Date of Patent: October 21, 2003
    Assignee: NEC Corporation
    Inventor: Akio Tanikawa
  • Patent number: 6351411
    Abstract: A memory cell provides point defect trap sites in an insulator for storing data charges. Single electrons are stored on respective point defect trap sites and a resulting parameter, such as transistor drain current, is detected. By adjusting the density of the point defect trap sites, more uniform step changes in drain current are obtained as single electrons are stored on or removed from respective trap sites. By also adjusting the trapping energy of the point defect trap sites, the memory cell provides either volatile data storage, similar to a dynamic random access memory (DRAM), or nonvolatile data storage, similar to an electrically erasable and programmable read only memory (EEPROM). The memory cell is used for storing binary or multi-state data.
    Type: Grant
    Filed: June 12, 2001
    Date of Patent: February 26, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Leonard Forbes, Joseph E. Geusic
  • Patent number: 6288942
    Abstract: High-concentrated impurity regions 24 for isolation of bit line contacts, having the same conduction type as that of a semiconductor substrate 10, are formed in the semiconductor substrate 10 under field oxide films 12 in locations between individual drain regions of selection transistors provided in a plurality of NAND memory cells, respectively. The high-concentrated impurity regions 24 for isolation of bit line contacts are made in a common step of making high-concentrated impurity regions 26 for isolation of memory transistors, by implanting impurities into the semiconductor substrate 10 through slits 20a, 20b made in a first conductive film 20. The high-concentrated impurity regions 24 prevent the punch-through phenomenon between bit line contacts 42a, and improve the resistivity to voltage between the bit line contacts 42a.
    Type: Grant
    Filed: August 4, 2000
    Date of Patent: September 11, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hirohisa Iizuka, Shinji Satoh, Riichiro Shirota
  • Patent number: 6278629
    Abstract: A read-only memory includes a semiconductor substrate; a memory cell matrix which is formed on the semiconductor substrate; and word and bit lines which define the locations of the memory cell matrix. The memory cell matrix includes field effect transistors, each of which turns off when accessed or addressed; and conducting regions, which keep conductive state all the time. Binary data stored in the memory cell matrix are determined by detecting current flowing through the selected bit line.
    Type: Grant
    Filed: March 21, 2000
    Date of Patent: August 21, 2001
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Hiroshi Mizuhashi, Teruo Katoh
  • Patent number: 6252797
    Abstract: A masked ROM of a flat cell structure has a plurality of bit-line diffusion layers formed in parallel in one direction in a semiconductor. substrate, a plurality of word lines formed on the bit-line diffusion layers orthogonally to the bit-line diffusion layers and channel regions between the bit-line diffusion layers beneath the word lines, wherein the word line is composed of a laminated layer of a first conductive layer and a second conductive layer on the channel regions and composed of the second conductive layer on the bit-line diffusion layers.
    Type: Grant
    Filed: February 23, 2000
    Date of Patent: June 26, 2001
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Masahiro Hasegawa
  • Publication number: 20010000336
    Abstract: Method for forming quantum dots using agglomeration of a conductive layer and a semiconductor device resulting therefrom are disclosed. The method includes the steps of forming a first insulating layer on a substrate, forming a conductive layer on the first insulating layer, forming a second insulating layer on the conductive layer, and annealing the conductive layer between the first, and second insulating layers to agglomerate the conductive layer.
    Type: Application
    Filed: December 14, 2000
    Publication date: April 19, 2001
    Applicant: Hyundai Electronics Industries Co., Ltd
    Inventors: Ki Bum Kim, Tae Sik Yoon, Jang Yeon Kwon
  • Patent number: 5790452
    Abstract: A memory cell having an asymmetrical transistor which provides access to a data storage circuit of the memory cell. The asymmetrical transistor exhibits a forward threshold voltage when forward biased and a reverse threshold voltage when reverse biased. The forward threshold voltage is less than the reverse threshold voltage. The asymmetrical transistor is connected such that during write-disturb mode, the asymmetrical transistor is reverse biased to provide a relatively high reverse threshold voltage. This high reverse threshold voltage minimizes subthreshold current leakage during write-disturb mode, thereby reducing the possibility of data corruption. During read mode, the asymmetrical transistor is forward biased to provide a relatively low forward threshold voltage. This low forward threshold voltage maximizes the read voltage applied to the data storage circuit through the asymmetrical transistor, thereby improving the stability of the memory cell.
    Type: Grant
    Filed: May 2, 1996
    Date of Patent: August 4, 1998
    Assignee: Integrated Device Technology, Inc.
    Inventor: Chuen-Der Lien
  • Patent number: 5754464
    Abstract: A mask ROM with increased memory capacity is disclosed. Besides MOS transistors each comprising a memory cell, MOS field shield transistors for device isolation, originally provided for electrically isolating the memory cell transistors, are also used as additional memory cells in addition to providing their isolating function. To write data in one of the field shield transistor, the threshold voltage of the field shield transistor is lowered, compared to field shield transistors in other regions. This is done by ion implantation of an n-type impurity into a p-type silicon substrate in a region beneath a gate electrode of the field shield transistor (a channel region). Data is read by judging on/off of the transistors when an intermediate voltage, between a high threshold voltage and a low threshold voltage is applied to a field shield line.
    Type: Grant
    Filed: December 13, 1996
    Date of Patent: May 19, 1998
    Assignee: Nippon Steel Semiconductor Corporation
    Inventor: Yugo Tomioka
  • Patent number: 5732012
    Abstract: A ROM cell array in which the drains are more lightly doped than the sources. This reduces the worst-case capacitance seen by the bitlines, and consequently reduces the access time of the memory.
    Type: Grant
    Filed: March 17, 1994
    Date of Patent: March 24, 1998
    Assignee: SGS-Thomson Microelectronics, S.r.l.
    Inventors: Paolo Cappelletti, Silvia Lucherini, Bruno Vajana
  • Patent number: 5579279
    Abstract: A memory system having an input buffer, an address counter, an address decoder, and a memory-cell array. Address signals are supplied to the memory-cell array. In the system, a true-address data determining section has wires or a circuit storing an internal address specific to the system. A false-data generating circuit generates false data when the internal address is in a false data area, and the false data is input to an output selecting circuit. A true-address data area detecting circuit compares the true-address data EAi with the internal address consisting of the address signals supplied from an address counter, and generates a signal REAL when the internal address is in a true-address data area. The output-selecting circuit selects the false data or the data read from the memory-cell array through a sense amplifier, in accordance with whether the signal REAL is at high level or low level. The data stored in the memory-cell array consists of true data items and false data items.
    Type: Grant
    Filed: September 26, 1995
    Date of Patent: November 26, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshio Mochizuki, Hideo Kato, Nobutake Sugiura
  • Patent number: 5541876
    Abstract: A memory cell and a process for making it are disclosed. The ROM code is not implanted in the floating gate for cells selected to be "off". This memory cell has a much lower threshold voltage than conventional cells and the implantation induced crystal damage is avoided.
    Type: Grant
    Filed: June 1, 1994
    Date of Patent: July 30, 1996
    Assignee: United Microelectronics Corporation
    Inventors: Chen-Chin Hsue, Ming-Tzong Yang, Chung-Cheng Wu
  • Patent number: 5517634
    Abstract: An array of dynamic memory cells and method for programming that array with initial information, as well as a disk drive system incorporating such an array, are disclosed. The array includes dynamic memory cells formed on an integrated circuit substrate. The array is modified by a programming step to contain nonvolatile initial information which may be retrieved immediately following a reset sequence. The array includes storage cells arranged as a matrix of bit line columns and row selects, each cell including a pass transistor having a predetermined threshold voltage characteristic Vth and being associated with a storage capacitor. Predetermined ones of the pass transistors are modified by a programming step, either during or following fabrication, so as to have a different predetermined threshold voltage characteristic Vthm, so that the array is comprised of unmodified cells and modified cells in a manner defining nonvolatile initial information in the array.
    Type: Grant
    Filed: June 23, 1992
    Date of Patent: May 14, 1996
    Assignee: Quantum Corporation
    Inventor: Michael S. Ehrlich
  • Patent number: 5422844
    Abstract: A nonvolatile semiconductor memory, which includes an array of programmable transistor cells, such as EPROM or EEPROM cells, provides electrical isolation without the use of field oxide islands. The cells are arranged in X number of rows and Y number of columns with the cells in at least two of the rows being designated as select cells and the remaining cells being designated as memory cells. Control circuitry is provided for causing the select cells to supply programming voltages to selected ones of the memory cells. Alternate ones of the select cells are formed as implanted-channel select cells to provide electrical isolation for adjacent select cells which remain in the low threshold (active) state. The implanted-channel select cells are formed by implanting a material into the channel region of each of the implanted-channel select cells to increase the threshold voltage of the cells, thereby preventing the implanted channel select cells from conducting when normal operational voltages are applied.
    Type: Grant
    Filed: September 24, 1993
    Date of Patent: June 6, 1995
    Assignee: National Semiconductor Corporation
    Inventors: Graham Wolstenholme, Albert Bergemont, Etan Shacham
  • Patent number: 5422841
    Abstract: A semiconductor memory device, which has a memory cell comprising the following transistors: a transistor for selecting; and a bipolar transistor for memorizing, which has a base region whose base concentration as either lower than an ordinary base concentration or higher than an ordinary base concentration and which is constructed so as to generate a reverse base current.
    Type: Grant
    Filed: December 20, 1993
    Date of Patent: June 6, 1995
    Assignee: Texas Instruments Incorporated
    Inventor: Osamu Nakayama
  • Patent number: 5403764
    Abstract: In a method for producing a semiconductor device having a nonvolatile memory capable of electrically writing, reading and erasing, and a read only memory; the improvement wherein the method includes a step of writing a state of "0" or "1" in the read only memory by doping said read only memory with an impurity for adjusting a threshold voltage of the read only memory, and steps for producing the read only memory other than the step of writing are the same as steps for producing the nonvolatile memory.
    Type: Grant
    Filed: March 26, 1993
    Date of Patent: April 4, 1995
    Assignee: Rohm Co., Ltd.
    Inventors: Hiroki Yamamoto, Hiroshi Oji
  • Patent number: 5383149
    Abstract: A ROM device provides a double density memory array. The word line array is composed of transversely disposed conductors sandwiched between two arrays of bit lines which are orthogonally disposed relative to the word line array. The two arrays of bit lines are stacked with one above and with one below the word line array. A first gate oxide layer is located between the word line array and a first one of the array of bit lines and a second gate oxide layer is located between the word line array and a the other of the arrays of bit lines. The two parallel sets of polysilicon thin, film transistors are formed with the word lines serving as gates for the transistors.
    Type: Grant
    Filed: August 29, 1994
    Date of Patent: January 17, 1995
    Assignee: United Microelectronics Corporation
    Inventor: Gary Hong
  • Patent number: 5317534
    Abstract: A method for manufacturing highly integrated NAND and NOR logic mask read only memory (MROM) devices is disclosed. Over the top surface of a semiconductor substrate, where a first polysilicon layer is formed, a pattern of a gate electrode is formed along a word line in the order of odd numbers or even numbers. Next, an insulation layer having a thickness of a submicron range is formed over the top surface of the substrate. And then a photoresist is covered and an etch back process is performed. Thereafter, the exposed insulation layer caused by the etch back process and the polysilicon layer are selectively etched to form a word line spacing corresponding to a thickness of the insulation layer. Thus, spacing between adjacent word lines can be minimized and a process margin can be sufficiently ensured.
    Type: Grant
    Filed: November 25, 1992
    Date of Patent: May 31, 1994
    Assignee: SamSung Electronics Co., Ltd.
    Inventors: Jeong-Hyeok Choi, Chul-Ho Shin
  • Patent number: 5272671
    Abstract: A nonvolatile semiconductor memory device comprises a memory cell array and a redundant circuit. The memory cell array comprises a plurality of cell lines for storing fixed data. The redundant circuit comprises redundancy memory cell rows of MOS transistors, and at least one redundancy spare decoder by which at least one of the redundancy memory cell rows is selectively determined and permuted with a memory cell to be repaired. At least one of the redundancy memory cell rows has data to be recovered stored therein. The data to be recovered is stored in the redundancy memory cell rows by selectively implanting channel regions of the memory cell rows with an impurity ion of high energy.
    Type: Grant
    Filed: April 2, 1991
    Date of Patent: December 21, 1993
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Jun Kudo, Tsutomu Ashida
  • Patent number: 5262987
    Abstract: A semiconductor nonvolatile memory has a base semiconductor region of one conductivity type. A first semiconductor region of the one conductivity type is formed in a surface portion of the base semiconductor region and has an impurity density higher than that of the base semiconductor region. A source region and a drain region of opposite conductivity than the first semiconductor region are formed in a surface portion of the first semiconductor region in spaced relation from each other. A second semiconductor region of the one conductivity type is formed in a surface portion of the first semiconductor region and contains an impurity of the opposite conductivity type. A floating gate electrode is formed over and electrically insulated from the second semiconductor region, and a control gate electrode is formed over and electrically insulated from the floating gate electrode.
    Type: Grant
    Filed: July 20, 1992
    Date of Patent: November 16, 1993
    Assignee: Seiko Instruments Inc.
    Inventor: Yoshikazu Kojima
  • Patent number: 5257230
    Abstract: There is disclosed an improved semiconductor memory device having a regular memory cell array and a spare memory cell array. Each spare memory cell constituting the spare memory cell array includes a first transistor selected by a read word line, whose drain is connected to a spare bit line and source is connected via a fuse to a power supply, and a second transistor connected between the interconnection between the first transistor and fuse and a ground. The fuse is selectively blown by flowing a blowing current through the fuse by selecting the second transistor through a write line to thereby disconnect a discharge current path of the spare bit line. The threshold voltage of the second transistor of the spare memory cell which is made conductive upon selection by the write line when the blowing current flows through the fuse is higher than a potential difference between a potential generated at the write line connected with another spare memory cell and a ground potential.
    Type: Grant
    Filed: August 13, 1990
    Date of Patent: October 26, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuhiko Nobori, Taira Iwase, Masamichi Asano, Makoto Takizawa, Shigefumi Ishiguro, Kazuo Yonehara, Satoshi Nikawa, Koji Saito
  • Patent number: 5117389
    Abstract: A flat-cell ROM array reduces the number of block select transistors utilized, allows for the layout of straight metal lines, while sharing the metal lines between even and odd banks, and achieves very high density and high performance. Parallel buried diffusion regions are deposited in the substrate. A gate oxide is laid over the substrate. A plurality of polysilicon word lines are laid over the gate oxide perpendicular to the buried diffusion regions, so that the areas between the respective pairs of buried diffusion regions and under the polysilicon word lines, form columns of flat cell field effect transistors. An insulating layer is laid over the polysilicon word lines, and a plurality of metal bit lines and virtual ground lines is deposited. These metal lines are shared by even and odd columns of field effect transistors. Access to the metal lines is made through a plurality of LOCOS block select transistors connected to every other buried diffusion bit line.
    Type: Grant
    Filed: September 5, 1990
    Date of Patent: May 26, 1992
    Assignee: Macronix International Co., Ltd.
    Inventor: Tom D. H. Yiu
  • Patent number: 5099451
    Abstract: To avoid differentiation, in manufacture, between the random-access memory cells and read-only memory cells of the same memory array, the memory cells are all made by the same technology. These memory cells employ essentially floating gate transistors. The random-access memory cells are programmed, in a stand way, by injecting or not electronic charges in the floating gates of the transistors. The read-only memory cells are put in a programmed or an unprogrammed state by the selective implantation of impurities or not in the conduction channels of the floating gate transistors of these memory cells. There is an improved concealment of the content, which is designed to remain concealed, of these memory cells, at the same time, the conditions for making prototypes to order are improved.
    Type: Grant
    Filed: November 16, 1988
    Date of Patent: March 24, 1992
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventors: Laurent Sourgen, Gilles Lisimaque, Jean Devin
  • Patent number: 4744054
    Abstract: A semiconductor device has a first ROM and a second ROM on a single semiconductor chip. To write information in the first ROM, a contact mask pattern is used by which wirings are formed on the chip, while information is written in the second ROM when memory transistors are formed on the chip. The first ROM stores the non-commonly used information of the program to be stored, or a specific user supplied program, and the second ROM stores predetermined and commonly used information of the program to be stored. Thus, a semiconductor device having a fixed memory in which a large capacity of information is stored can be provided to a user within a short period of time.
    Type: Grant
    Filed: February 15, 1985
    Date of Patent: May 10, 1988
    Assignee: NEC Corporation
    Inventors: Kazuhide Kawata, Hiroyuki Suzuki
  • Patent number: 4618943
    Abstract: A combined read-only and static read/write semiconductor memory is achieved by modifying the normal threshold voltage of some of the transfer FETs in an otherwise conventional static-memory cell. A read/write data bit is recovered from an addressed cell by applying a word-line voltage higher than both the threshold voltages. Read-only data is read from the same addressed cell by using a word-line voltage higher than one of the thresholds but lower than the other, then decoding the resulting bit-line voltages. An extension allows multiple read-only bits in a single cell by lowering the cell supply voltage when read-only data are addressed.
    Type: Grant
    Filed: January 9, 1984
    Date of Patent: October 21, 1986
    Assignee: International Business Machines Corporation
    Inventors: Anthony G. Aipperspach, Joseph M. Fitzgerald, Philip T. Wu
  • Patent number: 4541074
    Abstract: A ROM including memory cells having characteristics corresponding to the "1" or "0" information to be stored, the correspondence to "1" or "0" information being achieved by changing the conductivity type of at least a portion of a semiconductor layer in the semiconductor devices of the memory cells.
    Type: Grant
    Filed: June 28, 1982
    Date of Patent: September 10, 1985
    Assignee: Fujitsu Limited
    Inventor: Motoo Nakano
  • Patent number: 4534017
    Abstract: In response to a periodic pulse on a lead (21) an FET (47) connected gate-to-drain is driven in a low current circuit, producing a threshold potential on node F. This is connected through switch FETs (61) to the word lines (1) of a memory. This holds the gates of memory access switches (5) at threshold. A higher voltage on the bit line (7) takes off charge in memory cells (40) which have drifted from zero charge stored toward the substrate voltage. Absence of the periodic signal activates an FET (59) which grounds node F. High voltage applied to a word line (1) switches off the FET (61) connecting that line to node F.
    Type: Grant
    Filed: October 29, 1981
    Date of Patent: August 6, 1985
    Assignee: International Business Machines Corporation
    Inventors: David R. Thomas, Paul C. Tien
  • Patent number: 4525812
    Abstract: A semiconductor memory device included memory cells each including two PNPN cells cross-coupled with each other, the PNPN cells each including a load transistor and a multi-emitter transistor, the multi-emitter transistor comprising a read/write transistor and a data holding transistor. The read/write transistor has means for decreasing the current amplification factor of the read/write transistor when it operates inversely, whereby the operating speed of the device is improved.
    Type: Grant
    Filed: November 18, 1982
    Date of Patent: June 25, 1985
    Assignee: Fujitsu Limited
    Inventors: Kazuhiro Toyoda, Chikai Ono
  • Patent number: 4525810
    Abstract: A single-FET-per cell read/write memory having capacitor storage elements also contains a pattern of fixed, latent data represented by ion implants in some of the FETs. This pattern is loaded into the capacitors by addressing the cells with a voltage between the thresholds of the normal and the implant-modified FETs, so that some of the capacitors are discharged and others are not. Thereafter, the data may be read out, or overwritten with variable data, by addressing the cells with a voltage higher than both thresholds.
    Type: Grant
    Filed: May 9, 1983
    Date of Patent: June 25, 1985
    Assignee: International Business Machines Corporation
    Inventors: William H. Cochran, Philip T. Wu
  • Patent number: 4481527
    Abstract: High density, simplified fabrication and the elimination of sidewalk leakage effects are achieved by the implementation of a self-aligned ion-implantation step during the fabrication of the MNOS transistor wherein, after the formation of the gate electrode of the transistor, low energy ions are implanted within the nitride layer of the MNOS transistor in the regions of the nitride layer adjacent to the gate electrode.
    Type: Grant
    Filed: May 26, 1983
    Date of Patent: November 6, 1984
    Assignee: McDonnell Douglas Corporation
    Inventors: Yung J. Chen, Rick K. Hodgman
  • Patent number: 4476545
    Abstract: A RAM memory cell in double polysilicon technology having improved packing density is attained by insulating neighboring active memory regions under a first polysilicon plane by ion implantation to increase the substrate doping of the surface of the semiconductor body whereby field shield insulation regions are generated by a transistor in the off-state and the memory regions are rendered self-conducting by the ion implantation so that with a voltage at the polysilicon-1-electrode of 0 volts, the full operating voltage can be written into the memory capacitor.
    Type: Grant
    Filed: October 27, 1981
    Date of Patent: October 9, 1984
    Assignee: Siemens Aktiengesellschaft
    Inventor: Wolfgang Mueller
  • Patent number: 4371955
    Abstract: In a semiconductor layer of either conductivity type, a central region having a low threshold voltage and side regions having a high threshold voltage are formed between a source regio
    Type: Grant
    Filed: February 15, 1980
    Date of Patent: February 1, 1983
    Assignee: Fujitsu Limited
    Inventor: Nobuo Sasaki
  • Patent number: 4342100
    Abstract: An MOS read only memory or ROM is formed by a process compatible with standard P or N channel metal gate manufacturing methods. The ROM is programmed at a late stage of the process after the metal level of contacts and interconnections has been deposited and patterned. Address lines and gates are polysilicon with an overlying patterned metal layer and output and ground lines are defined by elongated heavily doped regions. Thin gate oxide is formed for every gate position, rather than for only the selected gates as in the prior standard programming method. Each potential MOS transistor in the array is programmed to be a logic "1" or "0" by ion implanting through the polysilicon gates where metal has been removed, using photoresist as a mask.
    Type: Grant
    Filed: January 19, 1981
    Date of Patent: July 27, 1982
    Assignee: Texas Instruments Incorporated
    Inventor: Chang-Kiang Kuo
  • Patent number: RE32401
    Abstract: A quaternary FET read only memory is disclosed wherein each FET storage element in the array has its threshold adjusted by ion-implantation to one of four values. Each FET element in the array has its drain connected to a drain potential V.sub.DD. A binary input signal from a conventional binary, true/complement generator will then enable the gate of a selected FET storage cell and the output potential at the source of that selected storage cell will be V.sub.DD minus the customized threshold voltage of that storage cell, which is output at an output node. The signal on the output node is a quaternary signal which may be amplified by a quaternary sense amplifier circuit and then converted from quaternary to binary signal by means of a converter. The quaternary read only memory is capable of storing twice as much information per unit area as is a conventional FET binary read only memory. The concept may be expanded to N levels of information storage, using FET array devices with N different threshold voltages.
    Type: Grant
    Filed: February 27, 1981
    Date of Patent: April 14, 1987
    Assignee: International Business Machines Corporation
    Inventors: Kenneth E. Beilstein, Jr., Harish N. Kotecha