Semiconductive Patents (Class 365/174)
  • Patent number: 10546630
    Abstract: According to an embodiment, there is provided a semiconductor memory device comprising: a global bit line; a local bit line to which a plurality of cell transistors are connected; a switch connected to the local bit line; signal lines connected to the plurality of cell transistors; and a control circuit, wherein the control circuit selects a cell transistor to be selected by setting a potential of the signal line of the cell transistor to be selected to a first potential, changes a potential of the global bit line, changes a potential of the local bit line, and turns on the switch to connect the local bit line to the global bit line after changing the potential of the global bit line and the potential of the local bit line.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: January 28, 2020
    Assignees: KABUSHIKI KAISHA TOSHIBA, Toshiba Electronic Devices & Storage Corporation
    Inventor: Toshiaki Dozaka
  • Patent number: 10490253
    Abstract: A semiconductor system may include a controller and a semiconductor device. The controller may be configured to output a command. The semiconductor device may be configured to receive and decode the command and generate an internal command to perform a preset operation. The semiconductor device may be configured to update a synchronization temperature code with a temperature code when the temperature code changes. The semiconductor device may be configured to apply the synchronization temperature code to the controller in synchronization with the internal command.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: November 26, 2019
    Assignee: SK hynix Inc.
    Inventor: Haengseon Chae
  • Patent number: 10236036
    Abstract: Apparatuses for signal boost are disclosed An example apparatus includes: first and second digit lines coupled to memory cells; a sense amplifier including: first and second transistors having gates operatively coupled to the first digit line and drains coupled to a first node, sources of the first and second transistors coupled to first and second control lines providing first and second power supply voltage respectively; and third and fourth transistors having gates coupled to the second digit line and drains coupled to a second node, sources of the third and fourth transistors coupled to the first and second control lines respectively; a power line coupled to the first node and the second node; and a power switch providing either the first power supply voltage or a third power supply voltage smaller than the first power supply voltage to the power line.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: March 19, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Charles Ingalls, Christopher Kawamura
  • Patent number: 10212496
    Abstract: A high port count switching module includes a plurality of switching circuits disposed on a glass interposer, wherein the plurality of switching circuits each include cross-point switches configured to perform switching at a full signal rate; and a plurality of optical transceivers disposed on the glass interposer and communicatively coupled to the plurality of switching circuits. The glass interposer has i) a low dielectric loss, relative to a silicon, organic, or ceramic interposer, to allow wideband data transmission, ii) a smooth surface, resulting in smooth metal traces to minimize high-frequency skin effect loss, iii) a coefficient of thermal expansion that is matched to the plurality of switching circuits to minimize stresses, and iv) thermal isolation among the plurality of switching circuits due to low thermal conductivity of glass.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: February 19, 2019
    Assignee: Ciena Corporation
    Inventors: Michael Y. Frankel, John P. Mateosky, Vladimir Pelekhaty
  • Patent number: 10204684
    Abstract: A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a gate positioned between said first and second regions. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device. Methods of operating memory cells are also provided.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: February 12, 2019
    Inventor: Yuniarto Widjaja
  • Patent number: 10134744
    Abstract: A semiconductor memory device includes a first inverter, a second inverter, a first and second inner access transistors, and a first and second outer access transistors. The first inverter includes a first pull-up transistor and a first pull-down transistor, the second inverter includes a second pull-up transistor (PL2) and a second pull-down transistor, and the first inverter and the second inverter forms a latch circuit. The first and second inner access transistors and the first and second outer access transistors are electrically connected to the latch circuit, and channel widths of the second inner access transistor and the second outer access transistor are different from each other.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: November 20, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Han Chen, Wei-Chi Chen, Ching Chang, Ming-Shing Chen, Chao-Hsien Wu, Chia-Hui Hwang, Lu-Ran Huang
  • Patent number: 10083734
    Abstract: Some embodiments include an assembly having active material structures arranged in an array having rows and columns. Each of the active material structures has a first side which includes a bit contact region, and has a second side which includes a cell contact region. Each of the bit contact regions is coupled with a first redistribution pad. Each of the cell contact regions is coupled with a second redistribution pad. The first redistribution pads are coupled with bitlines, and the second redistribution pads are coupled with programmable devices. Some embodiments include methods of forming memory arrays.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: September 25, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Kuo-Chen Wang, Martin C. Roberts, Diem Thy N. Tran, Hideki Gomi, Fredrick D. Fishburn, Srinivas Pulugurtha, Michel Koopmans, Eiji Hasunuma
  • Patent number: 9922685
    Abstract: A semiconductor device includes: a source line; a bit line; a word line; a memory cell connected to the bit line and the word line; a driver circuit which drives a plurality of second signal lines and a plurality of word lines so as to select the memory cell specified by an address signal; a potential generating circuit which generates a writing potential and a plurality of reading potentials to supply to a writing circuit and a reading circuit; and a control circuit which selects one of a plurality of voltages for correction on a basis of results of the reading circuit comparing a potential of the bit line with the plurality of reading potentials.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: March 20, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Kiyoshi Kato
  • Patent number: 9859287
    Abstract: A semiconductor device may include a first active region including a first main region and a first protruding part. The semiconductor device may include a second active region including a second main region and a second protruding part. The semiconductor device may include a first transistor formed on the first active region. The semiconductor device may include a second transistor formed on the second active region. The semiconductor device may include a connecting structure connecting the first protruding part and the second protruding part to each other.
    Type: Grant
    Filed: October 5, 2016
    Date of Patent: January 2, 2018
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • Patent number: 9786363
    Abstract: A word-line enable pulse generator for a SRAM is provided. A delay unit receives an enable signal to provide an intermediate signal. A first inverter receives the intermediate signal to provide a word-line enable pulse signal to a plurality of word line drivers of the SRAM. The delay unit includes a first transistor coupled between an input terminal of the first inverter and a first power source, a resistor coupled between the input terminal of the first inverter and a second power source that is different from the first power source, and a second transistor coupled between the input terminal of the first inverter and the resistor. The first transistor and the second transistor form a second inverter. A specific edge of the word-line enable pulse signal is delayed from the specific edge of the enable signal by a delay time corresponding to resistance of the resistor.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: October 10, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Hyunsung Hong
  • Patent number: 9715907
    Abstract: An optimized method and apparatus for determining optimal DQS delay for DDR memory interfaces are disclosed. The method performs data eye training in a two dimensional space with time delay value as x-axis and reference voltage (Vref) as y-axis to determine a rectangular data eye within an overall data eye with Vref margin.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: July 25, 2017
    Assignee: Invecas, Inc.
    Inventors: Venkata N. S. N. Rao, Ravindra Kantamani, Prasad Chalasani
  • Patent number: 9653131
    Abstract: Apparatuses for voltage level control in a semiconductor device are described. An example apparatus includes: a plurality of circuits coupled in parallel between first and second nodes, the first node being supplied with a first voltage; and a voltage supply circuit that supplies the second node with one of second and third voltages, the first voltage being greater than the second voltage, and the second voltage being greater than the third voltage. The plurality of circuits includes a first circuit including a transistor coupled to the second node. The first circuit activates the transistor responsive to a first control signal and further sets a voltage level of the second node higher than the second voltage after the voltage supply circuit supplies the second nodes with the second voltage.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: May 16, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Satoshi Yamanaka
  • Patent number: 9633710
    Abstract: Provided is a highly reliable semiconductor device, a semiconductor device with a reduced circuit area, a memory element having favorable characteristics, a highly reliable memory element, or a memory element with increased storage capacity per unit volume. A semiconductor device includes a capacitor and a switching element. The capacitor includes a first electrode, a second electrode, and a dielectric. The dielectric is positioned between the first electrode and the second electrode. The switching element includes a first terminal and a second terminal. The first terminal is electrically connected to the first electrode. The following steps are sequentially performed: a first step of turning on the switching element in a first period, a second step of turning off the switching element in a second period, and a third step of turning on the switching element in a third period.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: April 25, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masashi Tsubuku, Masashi Fujita
  • Patent number: 9627376
    Abstract: A semiconductor device includes first and second memory cell regions adjacent to each other on a substrate. At least one active base and a shallow trench isolation may be sequentially laminated at a boundary between the first and second memory cell regions. First and second active fins are formed on respective sides of the shallow trench isolation, and the first and second active fins projecting from the active base. At least one deep trench isolation is formed on one side of the active base.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: April 18, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae-Joong Song, Jae-Ho Park, Kang-Hyun Baek
  • Patent number: 9600207
    Abstract: An integrated circuit with a patching function comprises a one-time programmable memory (OTP), a random access memory (RAM), and a control unit. The control unit copies data stored on the OTP into the RAM to obtain a copied image mirroring said data. It checks for presence of one or more patch instructions in the OTP, and, if a patch instruction is found in the OTP, modifies a portion of the copied image based on the patch instruction, to obtain a patched image stored in the RAM. The integrated circuit further comprises a processing unit configured to access the patched image in the RAM. The patch can be provided wirelessly.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: March 21, 2017
    Assignee: Dialog Semiconductor B.V.
    Inventors: Nikolaos Moschopoulos, Dimitris Chanos, Ioannis Sifnaios, Konstantinos Ninos, Dimitrios Papadopoulos
  • Patent number: 9520448
    Abstract: A push-pull resistive random access memory cell circuit includes an output node, a word line, a first bit line, and a second bit line. A first resistive random access memory device is connected between the first bit line and the output node and a second resistive random access memory device is connected between the output node and the second bit line. A first programming transistor has a gate connected to the word line, a drain connected to the output node, and a source. A second programming transistor has a gate connected to the word line, a drain connected to the source of the first programming transistor, and a source. The first and second programming transistors have the same pitch, the same channel length, and the same gate dielectric thickness, the gate dielectric thickness chosen to withstand programming and erase potentials encountered during operation of the push-pull ReRAM cell circuit.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: December 13, 2016
    Assignee: Microsemi SoC Corporation
    Inventors: John L. McCollum, Fethi Dhaoui
  • Patent number: 9484082
    Abstract: Methods of operating semiconductor memory devices with floating body transistors, using a silicon controlled rectifier principle are provided, as are semiconductor memory devices for performing such operations.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: November 1, 2016
    Assignee: Zeno Semiconductor, Inc.
    Inventor: Yuniarto Widjaja
  • Patent number: 9444464
    Abstract: A push-pull resistive random access memory cell circuit includes an output node, a word line, a first bit line, and a second bit line. A first resistive random access memory device is connected between the first bit line and the output node and a second resistive random access memory device is connected between the output node and the second bit line. A first programming transistor has a gate connected to the word line, a drain connected to the output node, and a source. A second programming transistor has a gate connected to the word line, a drain connected to the source of the first programming transistor, and a source. The first and second programming transistors have the same pitch, the same channel length, and the same gate dielectric thickness, the gate dielectric thickness chosen to withstand programming and erase potentials encountered during operation of the push-pull ReRAM cell circuit.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: September 13, 2016
    Assignee: Microsemi SoC Corporation
    Inventors: John L. McCollum, Fethi Dhaoui
  • Patent number: 9419006
    Abstract: A 3D NAND memory has vertical NAND strings across multiple memory planes above a substrate, with each memory cell of a NAND string residing in a different memory layer. Word lines in each memory plane each has a series of socket components aligned to embed respective floating gates of a group memory cells. In this way, the word line to floating gate capacitive coupling is enhanced thereby allowing a 4 to 8 times reduction in cell dimension as well as reducing floating-gate perturbations between neighboring cells. In one embodiment, each NAND string has source and drain switches that each employs an elongated polysilicon gate with metal strapping to enhance switching. The memory is fabricated by an open-trench process on a multi-layer slab that creates lateral grottoes for forming the socket components.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: August 16, 2016
    Assignee: SanDisk Technologies LLC
    Inventor: Raul Adrian Cernea
  • Patent number: 9293348
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate, a stacked structure, a dielectric layer, a conductive structure, a dielectric structure and a conductive plug. The stacked structure includes dielectric films and conductive films arranged alternately. The dielectric layer is between the conductive structure and a sidewall of the stacked structure. The dielectric structure is on the stacked structure and defining a through via. The conductive plug fills the through via and physically contacts one of the conductive films exposed by the through via and adjoined with the dielectric layer.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: March 22, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Erh-Kun Lai, Guan-Ru Lee, Yen-Hao Shih
  • Patent number: 9164149
    Abstract: This invention provide a testing device and method for a quantum battery by a semiconductor probe, whereby the electrical characteristics of the charging layer can be evaluated during the quantum battery manufacturing process. The testing device equipped with a semiconductor probe constituted by a conductive electrode and a metal oxide semiconductor layer including a metal oxide semiconductor which are laminated on a support, a source voltage for applying voltage across an electrode equipped to the semiconductor probe and a basic electrode laminated on a secondary battery charging layer, and an ammeter for measuring the current flowing between the electrode equipped on the semiconductor probe and the basic electrode of the secondary battery on which charging layer is laminated, and measures the current-voltage characteristics of the charging layer.
    Type: Grant
    Filed: October 30, 2011
    Date of Patent: October 20, 2015
    Assignees: Kabushiki Kaisha Nihon Micronics, Guala Technology Co., Ltd.
    Inventors: Harutada Dewa, Kiyoyasu Hiwada, Akira Nakazawa, Nobuaki Terakado
  • Patent number: 9153672
    Abstract: Some aspects of this disclosure relate to a memory device. The memory device includes a collector region having a first conductivity type and which is coupled to a source line of the memory device. A base region is formed over the collector region and has a second conductivity type. A gate structure is coupled to the base region and acts as a shared word line for first and second neighboring memory cells of the memory device. First and second emitter regions are formed over the base region and have the first conductivity type. The first and second emitter regions are arranged on opposite sides of the gate structure. First and second contacts extend upwardly from the first and second emitter regions, respectively, and couple the first and second emitter regions to first and second data storage elements, respectively, of the first and second neighboring memory cells, respectively.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: October 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Wei Ting, Chun-Yang Tsai, Kuo-Ching Huang
  • Patent number: 9118009
    Abstract: A method of fabricating a memory device includes defining a cell region on a substrate and defining a dummy region around the cell region, forming bit lines on a top surface of the substrate, the bit lines extending in one direction, forming cell vertical structures on top surfaces of the bit lines corresponding to the cell region, each cell vertical structure including a cell diode and a variable resistive element, forming dummy vertical structures on top surfaces of the bit lines corresponding to the dummy region, each dummy vertical structure including a dummy diode and a variable resistive element, and forming word lines in contact with top surfaces of the cell vertical structures and dummy vertical structures, the word lines intersecting the bit lines at right angles.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: August 25, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Masayuki Terai, In-Gyu Baek
  • Patent number: 9082970
    Abstract: A phase-change memory and a semiconductor recording reproducing device capable of reducing consumed power are provided. A SnxTe100-x/Sb2Te3 SL film obtained by depositing a SnxTe100-x film and a Sb2Te3 film layer by layer contains a SnTe/Sb2Te3 superlattice phase formed of SnTe and Sb2Te3, a SnSbTe alloy phase, and a Te phase. The SnTe/Sb2Te3 superlattice phase is diluted by the SnSbTe alloy phase and the Te phase. Here, X of the SnxTe100-x film is represented by 4 at. %?X?55 at. %.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: July 14, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Susumu Soeya, Takahiro Odaka, Toshimichi Shintani, Junji Tominaga
  • Patent number: 9054324
    Abstract: An organic molecular memory of an embodiment includes a first conductive layer, a second conductive layer, and an organic molecular layer interposed between the first conductive layer and the second conductive layer, the organic molecular layer including variable-resistance molecular chains or charge-storage molecular chains, the variable-resistance molecular chains or the charge-storage molecular chains having electron-withdrawing substituents.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: June 9, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideyuki Nishizawa, Shigeki Hattori, Masaya Terai, Satoshi Mikoshiba, Koji Asakawa, Tsukasa Tada
  • Patent number: 9030858
    Abstract: A semiconductor device, including: a first semiconductor layer including first transistors, wherein the first transistors are interconnected by at least one metal layer including aluminum or copper; and a second mono-crystallized semiconductor layer including second transistors and overlaying the at least one metal layer, wherein the at least one metal layer is in-between the first semiconductor layer and the second mono-crystallized semiconductor layer, wherein the second mono-crystallized semiconductor layer is less than 100 nm in thickness, and wherein the second transistors include horizontally oriented transistors.
    Type: Grant
    Filed: September 23, 2012
    Date of Patent: May 12, 2015
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak Sekar, Brian Cronquist, Paul Lim
  • Patent number: 9019767
    Abstract: A nonvolatile memory device includes a channel vertically extending from a substrate, a plurality of memory cells stacked along the channel; a source region connected to a first end portion of the channel, and a bit line connected to a second end portion of the channel, wherein the first end portion of the channel that adjoins the source region is formed as an undoped semiconductor layer or a semiconductor layer doped with P-type impurities.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: April 28, 2015
    Assignee: SK Hynix Inc.
    Inventors: Seiichi Aritome, Hyun-Seung Yoo, Sung-Jin Whang
  • Patent number: 9019759
    Abstract: Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell including a first region, a second region, and a body region capacitively coupled to at least one word line and disposed between the first region and the second region. Each memory cell also including a third region, wherein the third region may be doped differently than the first region, the second region, and the body region.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: April 28, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Srinivasa R. Banna, Michael A. Van Buskirk, Timothy Thurgate
  • Patent number: 9013918
    Abstract: A two-terminal memory cell includes a first P-type semiconductor layer, a first N-type semiconductor layer, a second P-type semiconductor layer, and a second N-type semiconductor layer arranged in sequence. A first data state may be stored in the memory cell by applying a forward bias, which is larger than a punch-through voltage VBO, between the first P-type semiconductor layer and the second N-type semiconductor layer. A second data state may be stored in the memory cell by applying a reverse bias, which is approaching to the reverse breakdown region of the memory cell, between the first P-type semiconductor layer and the second N-type semiconductor layer. In this way, the memory cell may be effectively used for data storage.
    Type: Grant
    Filed: August 10, 2011
    Date of Patent: April 21, 2015
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Qingqing Liang, Xiaodong Tong, Huicai Zhong, Huilong Zhu
  • Publication number: 20150092484
    Abstract: A plurality of memory blocks; and a control block configured to independently operate a part of the plurality of memory banks as a first sub-channel and a remainder of the plurality of memory banks as a second sub-channel according to whether a sub-channel is set.
    Type: Application
    Filed: May 2, 2014
    Publication date: April 2, 2015
    Applicant: SK hynix Inc.
    Inventors: Dong Uk LEE, Kyung Whan KIM, Dae Suk KIM
  • Patent number: 8995165
    Abstract: The present invention discloses a resistive memory cell, including a unipolar type RRAM and a MOS transistor as a selection transistor serially connected to the unipolar type RRAM, wherein the MOS transistor is fabricated over a partial depletion SOI substrate and provides a large current for program and erase of the RRAM by using an intrinsic floating effect of the SOI substrate. The present invention utilizes a floating effect of a SOI device, in which under the same width/length ratio, a MOS transistor over a SOI substrate can provide larger source/drain current than a MOS transistor over a bulk silicon, so that the area occupied by the selection transistor is reduced, which is advantageous to the integration of the RRAM array.
    Type: Grant
    Filed: February 22, 2012
    Date of Patent: March 31, 2015
    Assignee: Peking University
    Inventors: Yimao Cai, Zhenni Wan, Ru Huang
  • Patent number: 8994086
    Abstract: The invention provides a semiconductor device which is non-volatile, easily manufactured, and can be additionally written. A semiconductor device of the invention includes a plurality of transistors, a conductive layer which functions as a source wiring or a drain wiring of the transistors, and a memory element which overlaps one of the plurality of transistors, and a conductive layer which functions as an antenna. The memory element includes a first conductive layer, an organic compound layer and a phase change layer, and a second conductive layer stacked in this order. The conductive layer which functions as an antenna and a conductive layer which functions as a source wiring or a drain wiring of the plurality of transistors are provided on the same layer.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: March 31, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hiroko Abe, Yukie Nemoto, Ryoji Nomura, Mikio Yukawa
  • Patent number: 8982639
    Abstract: A nonvolatile memory device includes a plurality of memory blocks, and a pass transistor array transmitting a plurality of drive signals to a selected memory block among the plurality of memory blocks in response to a block select signal. The pass transistor array includes high voltage transistors including one common drain and two sources formed in one active region and one of the plurality of drive signals transmitted to the common drain is transmitted to different memory blocks through the two sources.
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: March 17, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Young Kim, Myung-Hoon Choi
  • Patent number: 8976601
    Abstract: A semiconductor memory apparatus includes a boundary circuit unit positioned between a low voltage page buffer and a high voltage page buffer and having circuits configured to electrically couple the low voltage page buffer and the high voltage page buffer. The boundary circuit unit includes: a first boundary circuit unit having first and second transistors configured to receive data of a corresponding memory cell area through a signal transmission line selected from a plurality of signal transmission lines extended and arranged along a first direction for each column; a second boundary circuit unit disposed adjacent in the first direction from the first boundary circuit unit and having the plurality of signal transmission lines extended and arranged thereon; and an active region where the first transistor is formed and an active region where the second transistor is formed are isolated from each other.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: March 10, 2015
    Assignee: SK Hynix Inc.
    Inventors: Sung Lae Oh, Byung Sub Nam, Go Hyun Lee
  • Patent number: 8971108
    Abstract: A semiconductor memory device includes a first semiconductor chip including a first pad group configured to input/output first data and a second pad group configured to input/output second data; and a second semiconductor chip in a stack with the first semiconductor chip and configured to be electrically connected to the first semiconductor chip by at least one chip through via, wherein the second semiconductor chip includes a first unit bank group including at least one first upper bank group and at least one first lower bank group, a second unit bank group including at least one second upper bank group and at least one second lower bank group, and a data path selector configured to electrically connect one among the first and second upper bank groups and the first and second lower bank groups with the chip through via.
    Type: Grant
    Filed: June 6, 2012
    Date of Patent: March 3, 2015
    Assignee: SK Hynix Inc.
    Inventor: Heat-Bit Park
  • Patent number: 8964453
    Abstract: Roughly described, the cell layout in an SRAM array is re-arranged such that the gate electrodes for transistors for which flexibility to use one channel length is desired, are formed along a different track from those for transistors for which flexibility to use a different channel length is desired. Not only does such a re-arrangement permit optimization of device ratios, but also in certain implementations can also reduce, rather than increase, cell area. Specific example layouts are described. The invention also involves layout files, macrocells, lithographic masks and integrated circuit devices incorporating these principles, as well as fabrication methods.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: February 24, 2015
    Assignee: Synopsys, Inc.
    Inventors: Xi-Wei Lin, Victor Moroz
  • Patent number: 8953358
    Abstract: A memory device in which one memory cell can operate in both a single-level cell mode and a multi-level cell mode includes a signal transmission path for a multi-level cell mode in which a multi-bit digital signal representing any of three or more states input to the memory circuit is converted by a D/A converter and stored in the memory cell and the stored data is read by converting a signal output from the memory cell into a multi-bit digital signal with an A/D converter and the multi-bit digital signal is output from the memory circuit, and a signal transmission path for a single-level cell mode in which a single-bit digital signal representing any of two states input to the memory circuit is directly stored in the memory cell and the signal stored in the memory cell is directly output from the memory cell.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: February 10, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tatsuji Nishijima, Hiroyuki Miyake
  • Patent number: 8953357
    Abstract: A semiconductor memory device according to an embodiment includes a memory cell array including memory cells each formed from a transistor formed over an active area of a well and disposed at intersections of a word line and a bit line group, the memory cell having different connection states including a state in which a source or a drain of the transistor is not electrically connected to any one of bit lines belonging to the bit line group and states in which the source or the drain is electrically connected only to a specific one of the bit lines, and an active area serving as a gate of the transistor being continuously formed in arrangement areas of the bit lines of the bit line group and spaces between the bit lines.
    Type: Grant
    Filed: March 6, 2012
    Date of Patent: February 10, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Toshiaki Dozaka
  • Patent number: 8948215
    Abstract: A deserializer circuit includes demultiplexer circuitry configured to receive serial data from an input and output a plurality of divided data outputs, and multiplexer circuitry configured to receive a first logic level at a first input of said multiplexer circuitry, and receive a second logic level at a second input of said multiplexer circuitry and receive one of said divided data outputs at a control input of said multiplexer circuitry. The outputs of the multiplexer circuitry produce the received serial data in a parallel form.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: February 3, 2015
    Assignees: STMicroelectronics SA, STMicroelectronics S.r.l.
    Inventors: Mounir Zid, Alberto Scandurra, Carmelo Pistritto, Rached Tourki
  • Patent number: 8934294
    Abstract: A semiconductor integrated circuit device, a method of manufacturing the same, and a method of driving the same are provided. The device includes a semiconductor substrate, an upper electrode extending from a surface of the semiconductor substrate; a plurality of switching structures extending from both sidewalls of the upper electrode in a direction parallel to the surface of the semiconductor substrate, and a phase-change material layer disposed between the plurality of switching structures and the upper electrode.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: January 13, 2015
    Assignee: SK Hynix Inc.
    Inventors: Myoung Sub Kim, Soo Gil Kim, Nam Kyun Park, Sung Cheoul Kim, Gap Sok Do, Joon Seop Sim, Hyun Jeong Lee
  • Patent number: 8934282
    Abstract: A method of forming a circuitry includes providing a substrate comprising a plurality of die. Each die includes a plurality of resistive random access memory (RRAM) storage cells. The method further includes concurrently initializing substantially all of the RRAM storage cells on the same wafer. Initializing can include applying a voltage potential across the RRAM storage cells.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: January 13, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Peter J. Kuhn, Feng Zhou
  • Patent number: 8923058
    Abstract: A nonvolatile memory device is provided. The device may include a plurality of cell strings that are configured to share a bit line, word lines, and selection lines. Each of the cell strings may include a plurality of memory cells connected in series to each other and a string selection device controlling connections between the memory cells and the bit line, and the string selection device may include a first string selection element with a first threshold voltage and a second string selection element connected in series to the first string selection element and having a second threshold voltage different from the first threshold voltage. At least one of the first and second string selection elements may include a plurality of switching elements connected in series to each other.
    Type: Grant
    Filed: October 17, 2012
    Date of Patent: December 30, 2014
    Assignee: Samsung Electronic Co., Ltd.
    Inventors: Changyun Lee, Yoocheol Shin, Jungdal Choi
  • Patent number: 8923062
    Abstract: A next read threshold is determined by determining a first number of solid state storage cells having a stored voltage which falls into a first voltage range and determining a second number of solid state storage cells having a stored voltage which falls into a second voltage range. A gradient is determine by taking a difference between the first number of solid state storage cells and the second number of solid state storage cells. The next read threshold is determined based at least in part on the gradient.
    Type: Grant
    Filed: July 5, 2013
    Date of Patent: December 30, 2014
    Assignee: SK hynix memory solutions inc.
    Inventors: Frederick K. H. Lee, Jason Bellorado, Arunkumar Subramanian, Lingqi Zeng, Xiangyu Tang, Ameen Aslam
  • Patent number: 8917546
    Abstract: A method of writing to a magnetic tunnel junction (MTJ) of a magnetic memory array includes an access transistor coupled to the MTJ for reading of and writing to the MTJ, where when the MTJ is written to, at times, by switching its magnetic orientation from an anti-parallel to a parallel magnetic orientation, a bit line that is coupled to one end of the MTJ is raised to Vcc and a voltage that is the sum of Vcc and Vx is applied to the gate of the access transistor, with Vx being approximately the voltage at an opposite end of the MTJ. Further, the voltage of a Source Line (SL), which is coupled to the MTJ using a first transistor of a write driver that is also coupled to the SL, is regulated such that SL remains sufficiently above 0 volts to avoid violation of Vgs exceeding Vcc where Vgs is the gate to source voltage of the access transistor.
    Type: Grant
    Filed: September 24, 2012
    Date of Patent: December 23, 2014
    Assignee: Avalanche Technology, Inc.
    Inventor: Ebrahim Abedifard
  • Patent number: 8891322
    Abstract: Systems and methods are disclosed that may include a first layer comprising a first redundant memory element, an input/output interface, a first layer fuse box, and a fuse blowing control. These systems and methods also may include a second layer coupled to the first layer through a first connection comprising a second layer memory element and a second layer fuse box coupled to the first redundant memory element. In addition, these systems and methods may further include a redundancy register coupled to the first layer, wherein upon the failure of part of the second layer memory element, the redundancy register provides information to the fuse blowing control that allocates part of the first redundant memory element to provide redundancy for the failed part of the second layer memory element by blowing elements in the first layer fuse box and the second layer fuse box.
    Type: Grant
    Filed: September 17, 2012
    Date of Patent: November 18, 2014
    Assignee: Conversant Intellectual Property Management Inc.
    Inventor: Hong Beom Pyeon
  • Patent number: 8891279
    Abstract: A mechanism is provided in a data processing system for enhancing wiring structure for a cache supporting an auxiliary data output. The mechanism splits the data cache into a first data portion and a second data portion. The first data portion provides a first set of data elements and the second data portion provides a second set of data elements. The mechanism connects a first data path to provide the first set of data elements to a primary output and connects a second data path to provide the second set of data elements to the primary output. The mechanism feeds the first data path back into the second data path and feeds the second data path back into the first data path. The mechanism connects a secondary output to the second data path.
    Type: Grant
    Filed: September 17, 2012
    Date of Patent: November 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Christian Habermann, Walter Lipponer, Martin Recktenwald, Hans-Werner Tast
  • Patent number: 8873280
    Abstract: A spin transfer torque random access memory includes a substance unit, a source line unit, an insulation unit, a transistor unit, a MTJ unit, and a bit line unit. The substance unit includes a substance layer. The source line unit includes a plurality of source lines formed inside the substance layer. The transistor unit includes a plurality of transistors respectively disposed on the source lines. Each transistor includes a source region formed on each corresponding source line, a drain region formed above the source region, a channel region formed between the source region and the drain region, and a surrounding gate region surrounding the source region, the drain region, and the channel region. The MTJ unit includes a plurality of MTJ structures respectively disposed on the transistors. The bit line unit includes at least one bit line disposed on the MTJ unit.
    Type: Grant
    Filed: October 27, 2011
    Date of Patent: October 28, 2014
    Assignee: Inotera Memories, Inc.
    Inventors: Tzung Han Lee, Chung-Lin Huang, Ron Fu Chu
  • Patent number: 8873282
    Abstract: A memory device includes a die package including a plurality of memory dies, an interface including an interface circuit, and a memory controller to control the interface with control data received from at least one die. The interface is to divide and multiplex an IO channel between the package and the controller into more than one channel using the data received from the at least one die. The interface includes a control input buffer to receive an enable signal through a control pad, a first input buffer to receive first data through a first IO pad in response to a first state of the enable signal, and a second input buffer to receive second data through a second IO pad in response to a second state of the enable signal. The interface further includes an input multiplexer to multiplex the first data and the second data to provide input data.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: October 28, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Oh Seung Min
  • Publication number: 20140307500
    Abstract: A device (e.g., an integrated circuit memory device such as a static random access memory device) includes word line drivers. Each of the word line drivers includes a pull-up device that is coupled to a node via a shared line. A precharge device is coupled between a power supply and the node. The precharge device and a pull-up device for a selected word line driver are controlled to allow the power supply to charge the node and then to allow the charge stored in the node to flow into a word line corresponding to the selected word line driver.
    Type: Application
    Filed: April 15, 2013
    Publication date: October 16, 2014
    Applicant: Applied Micro Circuits Corporation
    Inventors: Jason T SU, Jitendra KHARE
  • Publication number: 20140269047
    Abstract: An apparatus is disclosed for a memory cell having a floating body. A memory cell may include a transistor over an insulation layer, the transistor including a source, and a drain. The memory cell may also include a floating body including a first region positioned between the source and the drain, a second region positioned remote from each of the source and drain, and a passage extending through the insulation layer and coupling the first region to the second region. Additionally, the memory cell may include a bias gate at least partially surrounding the second region and configured for operably coupling to a bias voltage. Furthermore, the memory cell may include a plurality of dielectric layers, wherein each outer vertical surface of the second region has a dielectric layer of the plurality adjacent thereto.
    Type: Application
    Filed: May 28, 2014
    Publication date: September 18, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Mike N. Nguyen