Semiconductive Patents (Class 365/174)
  • Patent number: 12099849
    Abstract: An example computing device includes a non-volatile memory to store Basic Input/Output Systems (BIOS) data of the computing device, an audio codec, and a controller. The controller is to: receive a command from a provisioning device at the audio codec; and transfer a copy of the BIOS data between the controller and the memory based on the command.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: September 24, 2024
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Wei Ze Liu, Lan Wang, Chengkai Yeh, Christian Pena
  • Patent number: 12080704
    Abstract: A memory circuit includes a first and a second bit line, a first and a second inverter, a P-type pass gate transistor, a pre-charge circuit, a first transmission gate and a sense amplifier. The P-type pass gate transistor is coupled between the first storage node and the first bit line. The pre-charge circuit is coupled to at least the first bit line or the second bit line, and configured to charge at least the first or second bit line to a pre-charge voltage responsive to a first signal. The pre-charge voltage is between a voltage of a first logical level and a voltage of a second logical level. The first transmission gate is coupled to the first bit line, and configured to receive a first and a second control signal. The sense amplifier is coupled to the first bit line by the first transmission gate.
    Type: Grant
    Filed: April 3, 2023
    Date of Patent: September 3, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Shih-Lien Linus Lu
  • Patent number: 12058849
    Abstract: Described herein are IC devices that include semiconductor nanoribbons stacked over one another to realize high-density three-dimensional (3D) dynamic random-access memory (DRAM). An example device includes a first semiconductor nanoribbon, a second semiconductor nanoribbon, a first source or drain (S/D) region and a second S/D region in each of the first and second nanoribbons, a first gate stack at least partially surrounding a portion of the first nanoribbon between the first and second S/D regions in the first nanoribbon, and a second gate stack, not electrically coupled to the first gate stack, at least partially surrounding a portion of the second nanoribbon between the first and second S/D regions in the second nanoribbon. The device further includes a bitline coupled to the first S/D regions of both the first and second nanoribbons.
    Type: Grant
    Filed: November 9, 2021
    Date of Patent: August 6, 2024
    Assignee: Intel Corporation
    Inventors: Wilfred Gomes, Kinyip Phoa, Mauro J. Kobrinsky, Tahir Ghani, Uygar E. Avci, Rajesh Kumar
  • Patent number: 11983065
    Abstract: The present disclosure is directed to logic based read sample offset operations in a memory sub-system. A processing device performs a first read, a second read, and a third read of data from a memory devices using a first center value corresponding to a first read level threshold, a negative offset value, and a positive offset value, respectively. The processing device performs a XOR operation on results from the first and second reads to obtain a first value and a XOR operation on results from the second and third reads to obtain a second value. The processing device performs a first count operation on the first value to determine a first difference bit count and a second count operation on the second value to determine a second difference bit count. The processing device can store or output the first difference bit count and the second difference bit count.
    Type: Grant
    Filed: August 18, 2021
    Date of Patent: May 14, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Bruce A. Liikanen, Michael Sheperek
  • Patent number: 11914484
    Abstract: The NVDIMM (200) comprises a DRAM (201), a NAND flash memory (202) and a NVDIMM controller (100), the NVDIMM controller (100) controlling the NVDIMM (200) and comprising a DDR controller (101), a NAND flash memory controller (102), a data backup module (103) and a data recovery module (104), and the DDR controller (101) using and enabling DBI. The backup method comprises: reading, by the DDR controller (101), N-bit DQ and 1-bit DBI from the DRAM (201) and sending the same to the data backup module; encoding, by the data backup module (103), the N-bit DQ and the 1-bit DBI into N-bit EDQ according to the values of the N-bit DQ and the 1-bit DBI, and sending the N-bit EDQ to the NAND flash memory controller; and receiving, by the NAND flash memory controller (102), the N-bit EDQ and writing the N-bit EDQ into the NAND flash memory (202).
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: February 27, 2024
    Assignee: XI'AN UNIIC SEMICONDUCTORS CO., LTD.
    Inventors: Xiaofeng Zhou, Xiping Jiang
  • Patent number: 11849572
    Abstract: Embodiments disclosed herein include three-dimensional 3D arrays of memory cells and methods of forming such devices. In an embodiment a memory device comprises, a substrate surface, and a three-dimensional (3D) array of memory cells over the substrate surface. In an embodiment each memory cell comprises a transistor and a capacitor. In an embodiment the transistor of each memory cell comprises, a semiconductor channel, with a first end of the semiconductor channel electrically coupled to a bit line that runs substantially parallel to the substrate surface, and a second end of the semiconductor channel is electrically coupled to the capacitor. The transistor may also comprise a gate dielectric on a surface of the semiconductor channel between the first end and the second end of the semiconductor channel. In an embodiment, the gate dielectric is contacted by a word line that runs substantially perpendicular to the substrate surface.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: December 19, 2023
    Assignee: Intel Corporation
    Inventors: Aaron Lilak, Sean T. Ma, Abhishek Sharma
  • Patent number: 11728395
    Abstract: Some embodiments include an integrated transistor having an active region comprising semiconductor material. The active region includes a first source/drain region, a second source/drain region and a channel region between the first and second source/drain regions. A conductive gating structure is operatively proximate the channel region and comprises molybdenum. The integrated transistor may be incorporated into integrated memory, such as, for example, DRAM, FeFET memory, etc. Some embodiments include methods of forming integrated assemblies and devices, such as, for example, integrated transistors, integrated memory, etc.
    Type: Grant
    Filed: July 18, 2022
    Date of Patent: August 15, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Aaron Michael Lowe
  • Patent number: 11715509
    Abstract: A semiconductor device that enables lower power consumption and data storage imitating a human brain is provided. The semiconductor device includes a control unit, a memory unit, and a sensor unit. The memory unit includes a memory circuit and a switching circuit. The memory circuit includes a first transistor and a capacitor. The switching circuit includes a second transistor and a third transistor. The first transistor and the second transistor include a semiconductor layer including a channel formation region with an oxide semiconductor, and a back gate electrode. The control unit has a function of switching a signal supplied to the back gate electrode, in accordance with a signal obtained at the sensor unit.
    Type: Grant
    Filed: June 9, 2022
    Date of Patent: August 1, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hajime Kimura, Atsushi Miyaguchi, Yoshiaki Oikawa
  • Patent number: 11710728
    Abstract: A memory device includes a cell wafer having a first pad on one surface thereof; and a peripheral wafer bonded to the one surface of the cell wafer, and having a second pad coupled to the first pad. The cell wafer includes a memory cell array; first and second bit lines coupled to the memory cell array; and a bit line selection circuit configured to couple one of the first and second bit lines to the first pad. The peripheral wafer includes a page buffer low-voltage circuit including a first page buffer low-voltage unit corresponding to the first bit line and a second page buffer low-voltage unit corresponding to the second bit line; and a page buffer high-voltage circuit configured to couple one of the first and second page buffer low-voltage units to the second pad.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: July 25, 2023
    Assignee: SK hynix Inc.
    Inventors: Je Hyun Choi, Sung Lae Oh, Soo Yeol Chai
  • Patent number: 11600308
    Abstract: A semiconductor memory device may include a plurality of memory cells wherein identifiers may be provided to the memory cells. The semiconductor memory device may include a first circuit, a second circuit and a power control circuit. The first circuit may include a first power terminal and a second power terminal. The second circuit may include a third terminal and a fourth terminal. The power control circuit may be configured to apply a first power voltage or a ground voltage to the first power terminal and to apply the ground voltage to the second power terminal based on the identifiers.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: March 7, 2023
    Assignee: SK hynix Inc.
    Inventor: Chang Hyun Kim
  • Patent number: 11558018
    Abstract: Integrated circuits, such as power amplifier integrated circuits, are disclosed containing compact-footprint, vertically-integrated capacitor-avalanche diode (AD) structures. In embodiments, the integrated circuit includes a semiconductor substrate, a metal layer system, and a vertically-integrated capacitor-AD structure. The metal layer system includes, in turn, a body of dielectric material in which a plurality of patterned metal layers are located. The vertically-integrated capacitor-AD structure includes a first AD formed, at least in part, by patterned portions of the first patterned metal layer. A first metal-insulator-metal (MIM) capacitor is also formed in the metal layer system and at least partially overlaps with the first AD, as taken along a vertical axis orthogonal to the principal surface of the semiconductor substrate.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: January 17, 2023
    Assignee: NXP USA, Inc.
    Inventors: Joseph Gerard Schultz, Kevin Kim
  • Patent number: 11527623
    Abstract: Some embodiments include an integrated transistor having an active region comprising semiconductor material. The active region includes a first source/drain region, a second source/drain region and a channel region between the first and second source/drain regions. A conductive gating structure is operatively proximate the channel region and comprises molybdenum. The integrated transistor may be incorporated into integrated memory, such as, for example, DRAM, FeFET memory, etc. Some embodiments include methods of forming integrated assemblies and devices, such as, for example, integrated transistors, integrated memory, etc.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: December 13, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Aaron Michael Lowe
  • Patent number: 11488968
    Abstract: An IC structure comprises a substrate, a first SRAM cell, and a second SRAM cell. The first SRAM cell is formed over the substrate and comprises a first N-type transistor. The second SRAM cell is formed over the substrate and comprises a second N-type transistor. A gate structure of first N-type transistor of the first SRAM cell has a different work function metal composition than a gate structure of the second N-type transistor of the second SRAM cell.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: November 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon-Jhy Liaw
  • Patent number: 11482265
    Abstract: A memory device includes a command interface configured to receive a write command and internal write adjust (IWA) circuitry. The IWA circuitry is configured to receive the write command from the command interface, generate an internal write signal (IWS) based upon the received write command and train a data strobe (DQS) signal to generate a DQS signal having a set amount of phase alignment with a clock (CLK) of the memory device to capture a data signal (DQ) using the IWS.
    Type: Grant
    Filed: September 27, 2021
    Date of Patent: October 25, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Daniel B. Penney, Gary L. Howe
  • Patent number: 11379307
    Abstract: A magnetoresistive random-access memory (MRAM) device includes an array of MRAM bit cells grouped into words, each word having specified number of data bit cells, error correction code (ECC) bit cells, and at least two inversion indicator bit cells, the inversion indicator bit cells being redundant of each other; and a memory controller. The memory controller is configured to, for each of the words, set the inversion indicator bit cells to indicate whether the number of data bit cells in a word having a zero value is greater than the number of data bit cells having a one value, invert the zeroes and ones in the bit cells when the inversion indicator bit cells are set to indicate a greater number of zeroes than ones in the data bit cells of the word, and revert the data bit cells to their value before the zeroes and ones were inverted.
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: July 5, 2022
    Assignee: NXP USA, Inc.
    Inventors: Anirban Roy, Nihaar N. Mahatme
  • Patent number: 11205718
    Abstract: An integrated circuit includes one or more bipolar transistors, each including a first dielectric layer located over a semiconductor layer having a first conductivity type, the dielectric layer including an opening. A second dielectric layer is located between the first dielectric layer and the semiconductor layer. The second dielectric layer defines a first recess between the first dielectric layer and the semiconductor substrate at a first side of the opening, and a second recess between the first dielectric layer and the semiconductor substrate at a second opposite side of the opening. A first doped region of the semiconductor layer is located under the opening, the first doped region having a different second conductivity type and a first width. A second doped region of the semiconductor layer is also under the opening, the second doped region having the second conductivity type and underlying the first recess and the second recess.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: December 21, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Bernhard Benna, Berthold Staufer
  • Patent number: 11139008
    Abstract: A memory device includes a command interface configured to receive a write command and internal write adjust (IWA) circuitry. The IWA circuitry is configured to receive the write command from the command interface, generate an internal write signal (IWS) based upon the received write command and train a data strobe (DQS) signal to generate a DQS signal having a set amount of phase alignment with a clock (CLK) of the memory device to capture a data signal (DQ) using the IWS.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: October 5, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Daniel B. Penney, Gary L. Howe
  • Patent number: 11139007
    Abstract: A semiconductor storage device includes a sense amplifier configured to read and program data in memory cells, a first latch circuit to store read data or program data, a second latch circuit to store the first data transferred from the first latch circuit or the second data before the second data is transferred into the first latch circuit, an input/output circuit to output the first data stored in the second latch circuit and to transfer the second data received thereby to the second latch circuit, and a control circuit. Upon receiving a read command while the control circuit is performing a program operation on program data stored in second latch circuit, the control circuit interrupts the program operation to perform the read operation and resumes the program operation on the program data in response to a resume write command sequence that does not include the program data.
    Type: Grant
    Filed: January 19, 2021
    Date of Patent: October 5, 2021
    Assignee: KIOXIA CORPORATION
    Inventors: Junichi Sato, Akio Sugahara
  • Patent number: 11100980
    Abstract: An Orthogonal Dual Port Ram (ORAM) memory cell may be provided. The ORAM memory cell may comprise a data storage element, a first port bit line, and a second port bit line that may be substantially perpendicular to first port bit line. The ORAM memory cell may further comprise a first word line that may be substantially perpendicular to first port bit line wherein the ORAM memory cell may be configured to read data from the data storage element to the first port bit line when the first word line is enabled. The ORAM memory cell may further comprise a second word line being substantially perpendicular to the second port bit line wherein the ORAM memory cell may be configured to read data from the data storage element to the second port bit line when the second word line is enabled.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: August 24, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Cormac Michael O'Connell
  • Patent number: 11094385
    Abstract: Devices and techniques are disclosed herein to provide a high-voltage bias signal in a standby state of the storage system without exceeding a limited maximum standby current allowance of the storage system. The high-voltage bias signal can enable a string driver circuit in the standby state to couple a global word line to a local word line, to provide a bias to, or sink a voltage from, a pillar of a string of memory cells of the storage system in the standby state, such as to reduce read disturbances in the storage system.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: August 17, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Michele Piccardi, Xiaojiang Guo, Shigekazu Yamada
  • Patent number: 11095308
    Abstract: A check node processing unit configured to determine check node messages to decode a signal encoded using NB-LDPC code, the check node processing unit comprising: a data link to one or more message presorting units configured to determine permuted variable node messages by permuting variable node messages generated by one or more variable node processing units; a syndrome sub-check node configured to determine check node messages from a set of syndromes, the set of syndromes being determined from one or more intermediate messages computed from the permuted variable node messages; a forward-backward sub-check node configured to determine permuted check node messages from the intermediate messages; a switching unit configured to generate check node messages of given index from the check node messages or from the permuted check node messages depending on the giving index.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: August 17, 2021
    Assignee: UNIVERSITE DE BRETAGNE SUD
    Inventors: Cédric Marchand, Emmanuel Boutillon
  • Patent number: 11063048
    Abstract: Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory cell. The multi-port semiconductor memory cells include a plurality of gates and conductive regions interfacing with said floating body region. Arrays of memory cells and method of operating said memory arrays are disclosed for making a memory device.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: July 13, 2021
    Assignee: Zeno Semiconductor, Inc.
    Inventor: Yuniarto Widjaja
  • Patent number: 11031498
    Abstract: A semiconductor structure includes a substrate, first fins extending from the substrate with a first fin pitch, and second fins extending from the substrate with a second fin pitch that is smaller than the first fin pitch. The semiconductor structure also includes first gate structures engaging the first fins, second gate structures engaging the second fins, first epitaxial semiconductor features adjacent the first gate structures, and second epitaxial semiconductor features adjacent the second gate structures. The first epitaxial semiconductor features are partially embedded in the first fins at a first depth, and the second epitaxial semiconductor features are partially embedded in the second fins at a second depth that is smaller than the first depth.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: June 8, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Yang Lee, Tzu-Hsiang Hsu, Ting-Yeh Chen, Feng-Cheng Yang
  • Patent number: 10910023
    Abstract: A semiconductor storage device includes a sense amplifier configured to read and program data in memory cells, a first latch circuit to store read data or program data, a second latch circuit to store the first data transferred from the first latch circuit or the second data before the second data is transferred into the first latch circuit, an input/output circuit to output the first data stored in the second latch circuit and to transfer the second data received thereby to the second latch circuit, and a control circuit. Upon receiving a read command while the control circuit is performing a program operation on program data stored in second latch circuit, the control circuit interrupts the program operation to perform the read operation and resumes the program operation on the program data in response to a resume write command sequence that does not include the program data.
    Type: Grant
    Filed: August 5, 2020
    Date of Patent: February 2, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Junichi Sato, Akio Sugahara
  • Patent number: 10783952
    Abstract: Methods, devices, arrays and systems for reducing standby power for a floating body memory array. One method includes counting bits of data before data enters the array, wherein the counting includes counting at least one of: a total number of bits at state 1 and a total number of all bits; a total number of bits at state 0 and the total number of all bits; or the total number of bits at state 1 and the total number of bits at state 0. This method further includes detecting whether the total number of bits at state 1 is greater than the total number of bits at state 0; setting an inversion bit when the total number of bits at state 1 is greater than the total number of bits at state 0; and inverting contents of all the bits of data before writing the bits of data to the memory array when the inversion bit has been set.
    Type: Grant
    Filed: June 9, 2019
    Date of Patent: September 22, 2020
    Assignee: Zeno Semiconductor, Inc.
    Inventors: Benjamin S. Louie, Yuniarto Widjaja
  • Patent number: 10770141
    Abstract: Memory devices provide a plurality of memory cells, each memory cell including a memory element and a selection device. A plurality of first (e.g., row) address lines can be adjacent (e.g., under) a first side of at least some cells of the plurality. A plurality of second (e.g., column) address lines extend across the plurality of row address lines, each column address line being adjacent (e.g., over) a second, opposing side of at least some of the cells. Control circuitry can be configured to selectively apply a read voltage or a write voltage substantially simultaneously to the address lines. Systems including such memory devices and methods of accessing a plurality of cells at least substantially simultaneously are also provided.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: September 8, 2020
    Assignee: Ovonyx Memory Technology, LLC
    Inventors: David H. Wells, Jun Liu
  • Patent number: 10666264
    Abstract: A three-dimensional stacked integrated circuit (3D SIC) having a non-volatile memory die, a volatile memory die, and a logic die. The non-volatile memory die, the volatile memory die, and the logic die are stacked. The 3D SIC is partitioned into a plurality of columns that are perpendicular to each of the stacked dies. Each column of the plurality of columns is configurable to be bypassed via configurable routes. When the configurable routes are used, functionality of a failing part of the column is re-routed to a corresponding effective part of a neighboring column.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: May 26, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Tony M. Brewer
  • Patent number: 10546630
    Abstract: According to an embodiment, there is provided a semiconductor memory device comprising: a global bit line; a local bit line to which a plurality of cell transistors are connected; a switch connected to the local bit line; signal lines connected to the plurality of cell transistors; and a control circuit, wherein the control circuit selects a cell transistor to be selected by setting a potential of the signal line of the cell transistor to be selected to a first potential, changes a potential of the global bit line, changes a potential of the local bit line, and turns on the switch to connect the local bit line to the global bit line after changing the potential of the global bit line and the potential of the local bit line.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: January 28, 2020
    Assignees: KABUSHIKI KAISHA TOSHIBA, Toshiba Electronic Devices & Storage Corporation
    Inventor: Toshiaki Dozaka
  • Patent number: 10490253
    Abstract: A semiconductor system may include a controller and a semiconductor device. The controller may be configured to output a command. The semiconductor device may be configured to receive and decode the command and generate an internal command to perform a preset operation. The semiconductor device may be configured to update a synchronization temperature code with a temperature code when the temperature code changes. The semiconductor device may be configured to apply the synchronization temperature code to the controller in synchronization with the internal command.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: November 26, 2019
    Assignee: SK hynix Inc.
    Inventor: Haengseon Chae
  • Patent number: 10236036
    Abstract: Apparatuses for signal boost are disclosed An example apparatus includes: first and second digit lines coupled to memory cells; a sense amplifier including: first and second transistors having gates operatively coupled to the first digit line and drains coupled to a first node, sources of the first and second transistors coupled to first and second control lines providing first and second power supply voltage respectively; and third and fourth transistors having gates coupled to the second digit line and drains coupled to a second node, sources of the third and fourth transistors coupled to the first and second control lines respectively; a power line coupled to the first node and the second node; and a power switch providing either the first power supply voltage or a third power supply voltage smaller than the first power supply voltage to the power line.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: March 19, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Charles Ingalls, Christopher Kawamura
  • Patent number: 10212496
    Abstract: A high port count switching module includes a plurality of switching circuits disposed on a glass interposer, wherein the plurality of switching circuits each include cross-point switches configured to perform switching at a full signal rate; and a plurality of optical transceivers disposed on the glass interposer and communicatively coupled to the plurality of switching circuits. The glass interposer has i) a low dielectric loss, relative to a silicon, organic, or ceramic interposer, to allow wideband data transmission, ii) a smooth surface, resulting in smooth metal traces to minimize high-frequency skin effect loss, iii) a coefficient of thermal expansion that is matched to the plurality of switching circuits to minimize stresses, and iv) thermal isolation among the plurality of switching circuits due to low thermal conductivity of glass.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: February 19, 2019
    Assignee: Ciena Corporation
    Inventors: Michael Y. Frankel, John P. Mateosky, Vladimir Pelekhaty
  • Patent number: 10204684
    Abstract: A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a gate positioned between said first and second regions. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device. Methods of operating memory cells are also provided.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: February 12, 2019
    Inventor: Yuniarto Widjaja
  • Patent number: 10134744
    Abstract: A semiconductor memory device includes a first inverter, a second inverter, a first and second inner access transistors, and a first and second outer access transistors. The first inverter includes a first pull-up transistor and a first pull-down transistor, the second inverter includes a second pull-up transistor (PL2) and a second pull-down transistor, and the first inverter and the second inverter forms a latch circuit. The first and second inner access transistors and the first and second outer access transistors are electrically connected to the latch circuit, and channel widths of the second inner access transistor and the second outer access transistor are different from each other.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: November 20, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Han Chen, Wei-Chi Chen, Ching Chang, Ming-Shing Chen, Chao-Hsien Wu, Chia-Hui Hwang, Lu-Ran Huang
  • Patent number: 10083734
    Abstract: Some embodiments include an assembly having active material structures arranged in an array having rows and columns. Each of the active material structures has a first side which includes a bit contact region, and has a second side which includes a cell contact region. Each of the bit contact regions is coupled with a first redistribution pad. Each of the cell contact regions is coupled with a second redistribution pad. The first redistribution pads are coupled with bitlines, and the second redistribution pads are coupled with programmable devices. Some embodiments include methods of forming memory arrays.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: September 25, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Kuo-Chen Wang, Martin C. Roberts, Diem Thy N. Tran, Hideki Gomi, Fredrick D. Fishburn, Srinivas Pulugurtha, Michel Koopmans, Eiji Hasunuma
  • Patent number: 9922685
    Abstract: A semiconductor device includes: a source line; a bit line; a word line; a memory cell connected to the bit line and the word line; a driver circuit which drives a plurality of second signal lines and a plurality of word lines so as to select the memory cell specified by an address signal; a potential generating circuit which generates a writing potential and a plurality of reading potentials to supply to a writing circuit and a reading circuit; and a control circuit which selects one of a plurality of voltages for correction on a basis of results of the reading circuit comparing a potential of the bit line with the plurality of reading potentials.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: March 20, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Kiyoshi Kato
  • Patent number: 9859287
    Abstract: A semiconductor device may include a first active region including a first main region and a first protruding part. The semiconductor device may include a second active region including a second main region and a second protruding part. The semiconductor device may include a first transistor formed on the first active region. The semiconductor device may include a second transistor formed on the second active region. The semiconductor device may include a connecting structure connecting the first protruding part and the second protruding part to each other.
    Type: Grant
    Filed: October 5, 2016
    Date of Patent: January 2, 2018
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • Patent number: 9786363
    Abstract: A word-line enable pulse generator for a SRAM is provided. A delay unit receives an enable signal to provide an intermediate signal. A first inverter receives the intermediate signal to provide a word-line enable pulse signal to a plurality of word line drivers of the SRAM. The delay unit includes a first transistor coupled between an input terminal of the first inverter and a first power source, a resistor coupled between the input terminal of the first inverter and a second power source that is different from the first power source, and a second transistor coupled between the input terminal of the first inverter and the resistor. The first transistor and the second transistor form a second inverter. A specific edge of the word-line enable pulse signal is delayed from the specific edge of the enable signal by a delay time corresponding to resistance of the resistor.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: October 10, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Hyunsung Hong
  • Patent number: 9715907
    Abstract: An optimized method and apparatus for determining optimal DQS delay for DDR memory interfaces are disclosed. The method performs data eye training in a two dimensional space with time delay value as x-axis and reference voltage (Vref) as y-axis to determine a rectangular data eye within an overall data eye with Vref margin.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: July 25, 2017
    Assignee: Invecas, Inc.
    Inventors: Venkata N. S. N. Rao, Ravindra Kantamani, Prasad Chalasani
  • Patent number: 9653131
    Abstract: Apparatuses for voltage level control in a semiconductor device are described. An example apparatus includes: a plurality of circuits coupled in parallel between first and second nodes, the first node being supplied with a first voltage; and a voltage supply circuit that supplies the second node with one of second and third voltages, the first voltage being greater than the second voltage, and the second voltage being greater than the third voltage. The plurality of circuits includes a first circuit including a transistor coupled to the second node. The first circuit activates the transistor responsive to a first control signal and further sets a voltage level of the second node higher than the second voltage after the voltage supply circuit supplies the second nodes with the second voltage.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: May 16, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Satoshi Yamanaka
  • Patent number: 9633710
    Abstract: Provided is a highly reliable semiconductor device, a semiconductor device with a reduced circuit area, a memory element having favorable characteristics, a highly reliable memory element, or a memory element with increased storage capacity per unit volume. A semiconductor device includes a capacitor and a switching element. The capacitor includes a first electrode, a second electrode, and a dielectric. The dielectric is positioned between the first electrode and the second electrode. The switching element includes a first terminal and a second terminal. The first terminal is electrically connected to the first electrode. The following steps are sequentially performed: a first step of turning on the switching element in a first period, a second step of turning off the switching element in a second period, and a third step of turning on the switching element in a third period.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: April 25, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masashi Tsubuku, Masashi Fujita
  • Patent number: 9627376
    Abstract: A semiconductor device includes first and second memory cell regions adjacent to each other on a substrate. At least one active base and a shallow trench isolation may be sequentially laminated at a boundary between the first and second memory cell regions. First and second active fins are formed on respective sides of the shallow trench isolation, and the first and second active fins projecting from the active base. At least one deep trench isolation is formed on one side of the active base.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: April 18, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae-Joong Song, Jae-Ho Park, Kang-Hyun Baek
  • Patent number: 9600207
    Abstract: An integrated circuit with a patching function comprises a one-time programmable memory (OTP), a random access memory (RAM), and a control unit. The control unit copies data stored on the OTP into the RAM to obtain a copied image mirroring said data. It checks for presence of one or more patch instructions in the OTP, and, if a patch instruction is found in the OTP, modifies a portion of the copied image based on the patch instruction, to obtain a patched image stored in the RAM. The integrated circuit further comprises a processing unit configured to access the patched image in the RAM. The patch can be provided wirelessly.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: March 21, 2017
    Assignee: Dialog Semiconductor B.V.
    Inventors: Nikolaos Moschopoulos, Dimitris Chanos, Ioannis Sifnaios, Konstantinos Ninos, Dimitrios Papadopoulos
  • Patent number: 9520448
    Abstract: A push-pull resistive random access memory cell circuit includes an output node, a word line, a first bit line, and a second bit line. A first resistive random access memory device is connected between the first bit line and the output node and a second resistive random access memory device is connected between the output node and the second bit line. A first programming transistor has a gate connected to the word line, a drain connected to the output node, and a source. A second programming transistor has a gate connected to the word line, a drain connected to the source of the first programming transistor, and a source. The first and second programming transistors have the same pitch, the same channel length, and the same gate dielectric thickness, the gate dielectric thickness chosen to withstand programming and erase potentials encountered during operation of the push-pull ReRAM cell circuit.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: December 13, 2016
    Assignee: Microsemi SoC Corporation
    Inventors: John L. McCollum, Fethi Dhaoui
  • Patent number: 9484082
    Abstract: Methods of operating semiconductor memory devices with floating body transistors, using a silicon controlled rectifier principle are provided, as are semiconductor memory devices for performing such operations.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: November 1, 2016
    Assignee: Zeno Semiconductor, Inc.
    Inventor: Yuniarto Widjaja
  • Patent number: 9444464
    Abstract: A push-pull resistive random access memory cell circuit includes an output node, a word line, a first bit line, and a second bit line. A first resistive random access memory device is connected between the first bit line and the output node and a second resistive random access memory device is connected between the output node and the second bit line. A first programming transistor has a gate connected to the word line, a drain connected to the output node, and a source. A second programming transistor has a gate connected to the word line, a drain connected to the source of the first programming transistor, and a source. The first and second programming transistors have the same pitch, the same channel length, and the same gate dielectric thickness, the gate dielectric thickness chosen to withstand programming and erase potentials encountered during operation of the push-pull ReRAM cell circuit.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: September 13, 2016
    Assignee: Microsemi SoC Corporation
    Inventors: John L. McCollum, Fethi Dhaoui
  • Patent number: 9419006
    Abstract: A 3D NAND memory has vertical NAND strings across multiple memory planes above a substrate, with each memory cell of a NAND string residing in a different memory layer. Word lines in each memory plane each has a series of socket components aligned to embed respective floating gates of a group memory cells. In this way, the word line to floating gate capacitive coupling is enhanced thereby allowing a 4 to 8 times reduction in cell dimension as well as reducing floating-gate perturbations between neighboring cells. In one embodiment, each NAND string has source and drain switches that each employs an elongated polysilicon gate with metal strapping to enhance switching. The memory is fabricated by an open-trench process on a multi-layer slab that creates lateral grottoes for forming the socket components.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: August 16, 2016
    Assignee: SanDisk Technologies LLC
    Inventor: Raul Adrian Cernea
  • Patent number: 9293348
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate, a stacked structure, a dielectric layer, a conductive structure, a dielectric structure and a conductive plug. The stacked structure includes dielectric films and conductive films arranged alternately. The dielectric layer is between the conductive structure and a sidewall of the stacked structure. The dielectric structure is on the stacked structure and defining a through via. The conductive plug fills the through via and physically contacts one of the conductive films exposed by the through via and adjoined with the dielectric layer.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: March 22, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Erh-Kun Lai, Guan-Ru Lee, Yen-Hao Shih
  • Patent number: 9164149
    Abstract: This invention provide a testing device and method for a quantum battery by a semiconductor probe, whereby the electrical characteristics of the charging layer can be evaluated during the quantum battery manufacturing process. The testing device equipped with a semiconductor probe constituted by a conductive electrode and a metal oxide semiconductor layer including a metal oxide semiconductor which are laminated on a support, a source voltage for applying voltage across an electrode equipped to the semiconductor probe and a basic electrode laminated on a secondary battery charging layer, and an ammeter for measuring the current flowing between the electrode equipped on the semiconductor probe and the basic electrode of the secondary battery on which charging layer is laminated, and measures the current-voltage characteristics of the charging layer.
    Type: Grant
    Filed: October 30, 2011
    Date of Patent: October 20, 2015
    Assignees: Kabushiki Kaisha Nihon Micronics, Guala Technology Co., Ltd.
    Inventors: Harutada Dewa, Kiyoyasu Hiwada, Akira Nakazawa, Nobuaki Terakado
  • Patent number: 9153672
    Abstract: Some aspects of this disclosure relate to a memory device. The memory device includes a collector region having a first conductivity type and which is coupled to a source line of the memory device. A base region is formed over the collector region and has a second conductivity type. A gate structure is coupled to the base region and acts as a shared word line for first and second neighboring memory cells of the memory device. First and second emitter regions are formed over the base region and have the first conductivity type. The first and second emitter regions are arranged on opposite sides of the gate structure. First and second contacts extend upwardly from the first and second emitter regions, respectively, and couple the first and second emitter regions to first and second data storage elements, respectively, of the first and second neighboring memory cells, respectively.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: October 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Wei Ting, Chun-Yang Tsai, Kuo-Ching Huang
  • Patent number: 9118009
    Abstract: A method of fabricating a memory device includes defining a cell region on a substrate and defining a dummy region around the cell region, forming bit lines on a top surface of the substrate, the bit lines extending in one direction, forming cell vertical structures on top surfaces of the bit lines corresponding to the cell region, each cell vertical structure including a cell diode and a variable resistive element, forming dummy vertical structures on top surfaces of the bit lines corresponding to the dummy region, each dummy vertical structure including a dummy diode and a variable resistive element, and forming word lines in contact with top surfaces of the cell vertical structures and dummy vertical structures, the word lines intersecting the bit lines at right angles.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: August 25, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Masayuki Terai, In-Gyu Baek