Abstract: An improved memory cell circuit in which the collector of the "ON" transistor is clamped to a variable voltage level to prevent saturation. Saturation is prevented by providing a mechanism for limiting the voltage between a first node in the word line circuit and the collector of the conducting transistor to a first level, while limiting the voltage between the first node and the collector of the nonconducting transistor to a second, lower level.In one embodiment, clamping transistors have their emitters coupled to the collectors of the memory cell transistors and their bases coupled to the word line. A common resistor couples the load resistors of a plurality of memory cells to the word line.In a second embodiment, the common resistor couples the bases of the clamping transistors to an intermediate node in a Darlington driver for the word line.

Abstract: An adjustable sense amplifier circuit for read/write control of solid state memory devices is described. In a write mode the circuit includes a write select path, coupled to a current source and coupled to a differential pair of data select transistors, wherein the input data state sets each of two differential pairs formed by the memory element cross-coupled latch, such that the memory element stores selected data. In a sense mode, a second current path is selected wherein an adjustable sense level is provided to each of two differential pairs formed by the memory element. The current source is coupled to a reference voltage source which is independent of the supply voltage. The reference voltage source tracks changes in temperature and also provides low beta compensation for current loss due to the low beta value of transistors in the write and sense paths.

Abstract: Memory comprising a matrix of conventional Harper pnp cells and peripheral circuits which allows it to be used either as a random access memory or as an associative memory. In addition to the read/write circuits which are inhibited in search mode, it comprises search mode control circuits 7-1 to 7-m to provide the memory cells with a search argument DI-1 to DI-m and search circuits 11-1 to 11-n connected to the word lines for detecting the match or mismatch conditions. A search restore circuit 15 common to all word lines WL is used to restore the work lines to a quiescent voltage once the search operation is completed. Circuits 7 and 11 are inhibited in read/write mode.

Abstract: Herein disclosed is a bipolar memory having redundancy, which can be produced with a small area. In this semiconductor memory having a body memory for storing data and a spare memory for relief of fault bit of the body memory, a row is selected by cutting fuses in a decoder. Fundamentally signal lines such as word lines are not provided with fuses. Other parts including a power source and a reference voltage source are provided with fuses without decreasing the operating speed accompanied by only a slight increase in the area.

Abstract: A circuit for selecting a row of memory cells of an array is disclosed that reduces selection time, eliminates the need for providing a regulated voltage for biasing an active load, and utilizes the capacitive charge on the lower word line in the selection of the row. The array includes a first voltage terminal, a second voltage terminal, a plurality of word lines, a plurality of bit lines, and a plurality of memory cells, wherein the plurality of memory cells are arranged in a matrix of rows and columns. Each of the cells in a row are coupled between the first voltage terminal and a word line, and each of the cells in a column are coupled between a pair of the bit lines. A word line driver circuit is coupled between bases of active load transistors in each of the memory cells in a row and the word line of that row for selecting that row of memory cells.

Abstract: An emitter coupled logic circuit includes a bypass circuit which provides a conductive path for current when a programmable fuse is blown, so that input data is transmitted independently of the state of a clock signal. In one implementation, the circuit takes a register configuration having a master section and a slave section, each incorporating a programmable fuse. When the fuse in just one section is intact, the circuit serves as a clocked latch. When both fuses are blown, the bypass circuit is enabled so that the register functions as a combinatorial circuit which produces an output signal dependent on the input signal without reference to a clock signal.

Abstract: An I.sup.2 L programmable read only memory (PROM) row driver circuit sinks current from a row of memory elements when selectively activated. The circuit operates in the read mode at very low power levels and down to 1.0 volt. The circuit has two current sinking capabilities, a low current capability for the read mode and a high current capability for the program mode. Switching between modes is accomplished merely by changing the voltage on a power supply terminal; 1-3 volts for the read mode and 9-12 volts for program.

Abstract: A semiconductor memory device provided with at least one block pair. Each block contains therein bit line pairs, word lines, memory cells, and circuitry for writing data by cooperating with the bit line pairs. The wiring pattern of the writing part located in one of the blocks is reversed to that of the writing part located in another block adjacent thereto, whereby the two facing bit lines of different blocks assume opposite logic levels when the same data logic is written into all the memory cells.

Abstract: In a semiconductor memory cell having PNPN type memory cells, a vertical PNPN element is used as a load transistor and a sense transistor or a hold transistor, or both. A buried layer is used as a wiring layer for a word line or a bit line, so that the switching speed can be increased and the memory cell area can be decreased.

Abstract: A semiconductor memory device composed of bipolar transistors is disclosed. A read/write control circuit includes a voltage producing section which produces a reading-out voltage used for reading out the data stored in the selected memory cell. The voltage producing section includes a first transistor of an emitter follower type as its output stage, and the data-read operation is thus attained in a high speed. The voltage producing section further includes a diode whose ON voltage is substantially equal to that of a clamping diode provided in a memory cell and a second transistor having an emitter resistor and a collector resistor and supplying the collector resistor with a current determined by the ON voltage of the diode and the emitter resistor. The potential at the collector of the second transistor is applied to the first transistor.

Abstract: A semiconductor memory comprising at least memory cells, word lines (W.sub.+, W.sub.-), bit lines (BL, BL) and word line discharge circuits to be co-operated together with a word line discharge current controller. The word line discharge current controller is operative to gradually reduce a word line discharge current absorbed from the word line W.sub.- to the word line discharge circuit together with a gradual attenuation of an inverse current from the bit line to the corresponding memory cell.

Abstract: A semiconductor memory device includes a plurality of memory cells arranged in a matrix form and a decoder circuit selecting a row of the matrix in response to an address signal. The decoder circuit includes a first-stage decoder having a plurality of first-stage decoding elements and a second-stage decoder having a plurality of second-stage decoding elements. Each first-stage decoding element is connected to a plurality of second-stage decoding elements. Each of the first-stage decoding elements receives predetermined higher bits of the address signals. One of the first-stage decoding elements is selected upon one access command. Each of the plurality of second-stage decoding elements receives the address signals. One of the rows of the matrix is selected in response to the the address signals when the corresponding first-stage decoding element operates, whereby the power consumption is reduced.

Abstract: A word-line discharging circuit in a static-type semiconductor memory device, including, for each word line, a first transistor for detecting the potential change of the word line, a time-constant circuit for delaying the output of the first transistor, and a second transistor for conducting a discharging current through the memory cells. The second transistor is switched in response to the output of the time-constant circuit, and includes, for all of the word lines, a common discharging current source. The word-line discharging circuit further includes means respectively provided between the word lines and the common discharging current source for respectively slowing the rate of change in the current flowing through the word lines, whereby double selection of the word lines is prevented.

Abstract: An electronically selectable high performance data path switch which allows one input to drive two data buses or to have two inputs drive the two independently.

Abstract: A monolithically integrated memory cell having an improved clamped diode load is provided for improving write pulse width and write recovery times. A pair of latchable cross-coupled multi-emitter NPN transistors have a first emitter connected to a stand-by current drain line, and a second emitter coupled to a first bit line and a second bit line, respectively. The base of each transistor is cross-coupled to the collector of the other transistor. The base of each transistor is further coupled to the select line by a PNP transistor. The base of each PNP transistor is coupled to the collector of the respective cross-coupled transistor and is further coupled to the select line by a diode connected NPN transistor.

Abstract: A fall-through memory array comprising in a plurality of rows and columns a plurality of memory cells, each memory cell comprising a pair of cross-coupled transistors having three emitters, a collector and a base. Control potentials applied to a word line, coupled to each one of two of the emitters of each of the transistors, control the transfer of data bits from one row of such memory cells to another.

Abstract: A voltage balancing circuit, particularly suitable for bipolar memory arrays producing small signals, is provided which includes first and second conductive lines, a point of reference potential, a first device disposed between the first conductive line and the point of reference potential, a second device disposed between the second conductive line and the point of reference potential, first and second transistors, first means for coupling the first line through the first transistor to the second line, second means for coupling the second line through the second transistor to the first line, and means for supplying substantially equal signals to the control electrodes of the first and second transistors. When used in a memory array, the conductive lines are the bit/sense lines, the point of reference potential is a bit/sense line reference voltage and the equal signals for the control electrodes of the transistors are provided in response to a signal from a bit decoder.

Abstract: A memory is described comprising static MTL memory cells for high operation speeds. The cell or primary injectors and the bit line injectors are coupled to each other by an angular injection coupling via the low-resistivity base region of the cell flip-flop transistors. This results in a signal path with reduced series resistance and thus higher signals and a faster read operation obtainable. The density is additionally increased by using in common the primary injectors and the bit line injectors of adjacent cells of the array.

Abstract: A semiconductor memory device includes at least, a memory cell including a first Schottky diode therein, a word line, a bit line, a first constant-current circuit for the word line, a second constant-current circuit for the bit line, and a bias circuit for biasing the first and second constant-current circuits. The bias circuit contains therein a second Schottky barrier diode. A forward voltage V.sub.F of the second Schottky barrier diode is substantially the same as that of the first Schottky barrier diode.

Abstract: Two memory cells each can be entirely fabricated in only two isolation beds. In one embodiment each bed contains one lateral PNP and one vertical NPN transistor in a merged structure. In a second embodiment, each bed contains one lateral PNP and two vertical NPN transistors in a merged structure. Memory access circuitry provides a high ratio of selected to unselected cell current in order to permit fast memory operation.

Abstract: An I.sup.2 L type semiconductor device having an elementary region which is isolated by V-shape grooves from the other portions of the device, said semiconductor device comprising an insulating layer coating covering the surface of the semiconductor body of the device, wherein an injector region is formed under said insulating layer and surrounded by thicker portions of said insulating layer, and base regions are formed under said insulating layer between said thicker portions of said insulating layer and said V-shape grooves.

Abstract: A termination circuit for word lines of a static semiconductor memory device comprising, for each word line, a first transistor which detects a potential change on the word line, a delay circuit which delays an output signal from the first transistor by a predetermined time period and a second transistor which is turned on and off by an output signal from the delay circuit. Each of the second transistors is connected between one of the hold lines and a common hold current source, so that the second transistors and the common hold current source forming a current switch.

Abstract: A semiconductor memory circuit, comprising memory cells; word lines, hold lines and bit lines connected to respective memory cells; and a hold-current controlling circuit. The hold-current controlling circuit comprises identical controlling circuit elements connected to respective hold lines and a constant-current source commonly connected to the controlling circuit elements. Each of the controlling circuit elements comprises means for absorbing electric charges from respective hold lines, when corresponding word lines change from a selection status to a non-selection status, until the voltage level of the hold line reaches a full "L" or "H" level, and means for blocking a flow of electric charges from the hold line, when a corresponding word line changes from a non-selection status to a selection status, during a predetermined interval after time data switching from one memory cell to another memory cell is performed.

Abstract: An integrated semiconductor circuit arrangement is provided which comprises a substrate of semiconductor material of one conductivity type, an epitaxial layer of the opposite conductivity type formed on one major surface of the substrate, the epitaxial layer having function elements such as transistors, diodes, resistances, and so forth, formed therein. A least some of these function elements are located in insulated regions provided for them which in the boundary area between the substrate and the epitaxial layer are bounded by a pn junction and which at right angles to this boundary area are bounded by oxide walls which extend through the epitaxial layer to the substrate. The oxide walls are surrounded by a resistor region of the said one conductivity type which extends through the epitaxial layer to the substrate.

Abstract: The invention relates to an improvement in a semiconductor memory device including flip-flop type memory cells, each memory cell consisting of a pair of cross-coupled multi-emitter transistors. The semiconductor memory device of the invention is characterized by including a capacitance added between the collector region and the base region of each of the transistor pair of each memory cell in order to prevent the memory cell from erroneously operating due to .alpha.-rays.

Abstract: A semiconductor memory apparatus is formed of a plurality of memory cells, each of which is connected to a first word line and a second word line. According to the present invention, emitters of the transistors by which the hold current of the memory cells are determined have different areas, so that the hold currents which are supplied to each of said memory cells are uniformly distributed.

Abstract: An emitter junction type bipolar memory cell circuit having clamp diodes connected in parallel to collector resistances. The collector resistances are set to produce a potential difference of greater than 0.6 V or so caused by the stationary current. By so doing, it is possible to exclude any mal-function attributable to noises in the writing operation of the memory circuit.

Abstract: A unique topography of I.sup.2 L bipolar semiconductor elements provides Read-Write Random Access Memory (RAM) with very high packing density, low cost, and good power and speed characteristics and with a very simple metallization pattern.

Abstract: A random access memory element, fed by a constant current source, contains two complementary transistors forming a pnpn or npnp structure, with a lateral transistor and a transverse transistor. The constant current source is connected to an emitter of the lateral transistor, which is at a distance from its collector. This transistor has a second emitter near this collector, this second emitter receiving a control voltage which is able to trigger the assembly.

Abstract: A static RAM cell, including two vertical, multiple-Schottky-collector switching transistors wherein a first collector of each is coupled to first and second sources of read/write data, respectively, and wherein a second collector of each transistor is cross-coupled with the base of the other transistor. The cell is implemented with I.sup.2 L technology, and also includes a complementary inverted multiple-collector NPN load transistor having its base electrically common with the emitters of the switching transistors, a first collector merged with the base of one switching transistor, and a second collector merged with the base of the other switching transistor.

Abstract: A current mode 20-bit memory is organized as four words each containing five bits. The memory comprises a clock circuit a data-in circuit, comprising a plurality of data selectors and master latch registers, a data-out circuit comprising two independent sets of output buffers, two independent read select circuits, a write select circuit, a 4x5 matrix of memory cells, and non-functional testing circuit. In one mode data may be independently read from any two words at the same time that data is written into any one word. In another mode, all bits in a selected word may be synchronously reset. In a third mode the storage elements associated with one selected word may be configured as an inverting shift register for testing and diagnostic purposes. The device is implemented in current mode logic, and a portion of the circuitry operates on differential level signals for increased operational speed and efficiency.

Abstract: An improved random access word addressable monolithic memory having a storage cell for each binary bit of each binary word of storage capacity. The storage cells being arranged in groups. Each cell of any given group being adapted to store a binary bit corresponding to a given bit position of each word stored in said memory. Each cell of each group being connected via first and second bit lines to a sense amplifier. Each sense amplifier coupled to a reference voltage source. The magnitude of the reference voltage supplied by the reference voltage source bearing a substantially invariant mathematical relationship to first and second potentials manifested by said storage cells during a read mode.The storage cells may each be generally of the type disclosed and claimed in U.S. Pat. No. 3,423,737 entitled "Non Destructive Read Transistor Memory Cell" granted Jan. 21, 1969 to L. R. Harper and of common assignee with the instant application.