Four Layer Devices Patents (Class 365/180)
  • Patent number: 9899079
    Abstract: A device is disclosed that includes memory cells, bit lines and a source line. The bit lines and the source line are electrically connected to the memory cells. In the I/O memory block, the source line and the bit lines are configured to provide logical data to the memory cells.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: February 20, 2018
    Assignee: TAIWAN SEMINCONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Yang Chang, Chia-Fu Lee, Wen-Ting Chu, Yue-Der Chih
  • Patent number: 9437717
    Abstract: Methods of fabricating bipolar junction transistors, bipolar junction transistors, and design structures for a bipolar junction transistor. A first portion of the intrinsic base layer is masked while a second portion of an intrinsic base layer is etched. As a consequence of the masking, the second portion of the intrinsic base layer is thinner than the first portion of the intrinsic base layer. An emitter and an extrinsic base layer are formed in respective contacting relationships with the first and second portions of the intrinsic base layer.
    Type: Grant
    Filed: August 21, 2013
    Date of Patent: September 6, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Kevin K. Chan, Peng Cheng, Qizhi Liu, Ljubo Radic
  • Patent number: 8964461
    Abstract: Techniques for providing a direct injection semiconductor memory device are disclosed. In one embodiment, the techniques may be realized as a method for biasing a direct injection semiconductor memory device including the steps of applying a first non-negative voltage potential to a first region via a bit line and applying a second non-negative voltage potential to a second region via a source line. The method may also include applying a third voltage potential to a word line, wherein the word line may be spaced apart from and capacitively to a body region that may be electrically floating and disposed between the first region and the second region. The method may further include applying a fourth positive voltage potential to a third region via a carrier injection line, wherein the third region may be disposed below at least one of the first region, the body region, and the second region.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: February 24, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Yogesh Luthra
  • Patent number: 8947925
    Abstract: A semiconductor memory device including an array of memory cells (MC) formed on a substrate each realized from a load element and thyristor that define a switchable current path whose state represents a volatile bit value stored by the MC. At least one word line corresponding to a respective row of the array is formed on the substrate and coupled to MC current paths for the corresponding row. Bit lines corresponding to respective columns of the array are formed on the substrate and can be coupled to a modulation doped QW interface of the MC thyristors for the corresponding column. Circuitry is configured to apply an electrical signal to the word line(s) in order to generate current that programs phase change material of the MC load elements into one of a high or low resistive state according to state of the current path of the MCs for non-volatile backup purposes.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: February 3, 2015
    Assignees: The University of Connecticut, Opel Solar, Inc.
    Inventor: Geoff W. Taylor
  • Patent number: 8934296
    Abstract: Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory cell. The multi-port semiconductor memory cells include a plurality of gates and conductive regions interfacing with said floating body region. Arrays of memory cells and method of operating said memory arrays are disclosed for making a memory device.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: January 13, 2015
    Assignee: Zeno Semiconductor, Inc.
    Inventor: Yuniarto Widjaja
  • Publication number: 20140340962
    Abstract: Apparatuses and methods can include write schemes for a thyristor memory cell in which an access pulse applied to the gate of the thyristor memory cell is adjusted relative to the data pulse to write data into the thyristor memory cell. Some of the write schemes may substantially reduce or eliminate an unselected data line disturb. In various embodiments, the thyristor memory cell can be structured with two control nodes and its cathode or anode coupled to a reference voltage node common to all thyristor memory cells in a memory array. Additional apparatuses and methods are disclosed.
    Type: Application
    Filed: August 4, 2014
    Publication date: November 20, 2014
    Inventor: Rajesh N. Gupta
  • Patent number: 8891290
    Abstract: A method and system for providing a magnetic junction residing on a substrate and usable in a magnetic device are described. The magnetic junction includes a first pinned layer, a first nonmagnetic spacer layer having a first thickness, a free layer, a second nonmagnetic spacer layer having a second thickness greater than the first thickness, and a second pinned layer. The first nonmagnetic spacer layer resides between the pinned layer and the free layer. The first pinned layer resides between the free layer and the substrate. The second nonmagnetic spacer layer is between the free layer and the second pinned layer. Further, the magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction.
    Type: Grant
    Filed: March 11, 2011
    Date of Patent: November 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Xueti Tang, Jing Wu
  • Patent number: 8891322
    Abstract: Systems and methods are disclosed that may include a first layer comprising a first redundant memory element, an input/output interface, a first layer fuse box, and a fuse blowing control. These systems and methods also may include a second layer coupled to the first layer through a first connection comprising a second layer memory element and a second layer fuse box coupled to the first redundant memory element. In addition, these systems and methods may further include a redundancy register coupled to the first layer, wherein upon the failure of part of the second layer memory element, the redundancy register provides information to the fuse blowing control that allocates part of the first redundant memory element to provide redundancy for the failed part of the second layer memory element by blowing elements in the first layer fuse box and the second layer fuse box.
    Type: Grant
    Filed: September 17, 2012
    Date of Patent: November 18, 2014
    Assignee: Conversant Intellectual Property Management Inc.
    Inventor: Hong Beom Pyeon
  • Patent number: 8817514
    Abstract: A three-dimensional array read/write (R/W) memory elements is formed across multiple layers of planes positioned at different distances above a semiconductor substrate. It is preferable to operate the R/W elements with low current and high resistive states. The resistance of these resistive states depends also on the dimension of the R/W elements and is predetermined by the process technology. A sheet electrode in series with the R/W element and a method of forming it provide another degree of freedom to adjust the resistance of the R/W memory element. The thickness of the sheet electrode is adjusted to obtain a reduced cross-sectional contact in the circuit path from the word line to the bit line. This allows the R/W memory element to have a much increased resistance and therefore to operate with much reduced currents. The sheet electrode is formed with little increase in cell size.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: August 26, 2014
    Assignee: SanDisk 3D LLC
    Inventors: George Samachisa, Johann Alsmeier
  • Patent number: 8797794
    Abstract: Apparatuses and methods can include write schemes for a thyristor memory cell in which an access pulse applied to the gate of the thyristor memory cell is adjusted relative to the data pulse to write data into the thyristor memory cell. Some of the write schemes may substantially reduce or eliminate an unselected data line disturb. In various embodiments, the thyristor memory cell can be structured with two control nodes and its cathode or anode coupled to a reference voltage node common to all thyristor memory cells in a memory array. Additional apparatuses and methods are disclosed.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: August 5, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Rajesh N. Gupta
  • Patent number: 8780607
    Abstract: Select devices for memory cell applications and methods of forming the same are described herein. As an example, one or more memory cells comprise a a select device structure including a two terminal select device having a current-voltage (I-V) profile associated therewith, and a non-ohmic device in series with the two terminal select device. The combined two terminal select device and non-ohmic device provide a composite I-V profile of the select device structure that includes a modified characteristic as compared to the I-V profile, and the modified characteristic is based on at least one operating voltage associated with the memory cell.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: July 15, 2014
    Assignee: Micron Technology, Inc.
    Inventors: David H. Wells, D. V. Nirmal Ramaswamy
  • Patent number: 8767458
    Abstract: Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory cell. The multi-port semiconductor memory cells include a plurality of gates and conductive regions interfacing with said floating body region. Arrays of memory cells and method of operating said memory arrays are disclosed for making a memory device.
    Type: Grant
    Filed: October 6, 2013
    Date of Patent: July 1, 2014
    Assignee: Zeno Semiconductor, Inc.
    Inventor: Yuniarto Widjaja
  • Patent number: 8760954
    Abstract: An integrated circuit device (20, 60) includes a plurality of memory cells (22), which are configured to store data. Multiple P-N junctions (24) are arranged so that a single, respective P-N junction is disposed in proximity to each memory cell and is configured to emit optical radiation during readout from the memory cell with a wavelength matching an emission wavelength of the memory cell.
    Type: Grant
    Filed: February 19, 2012
    Date of Patent: June 24, 2014
    Assignee: Cisco Technology Inc.
    Inventors: Lior Amarilio, Uri Bear, Reuven Elbaum, Yigal Shapiro, Chaim D. Shen-Orr, Yonatan Shlomovich, Zvi Shkedy
  • Patent number: 8699260
    Abstract: There are provided a memory element and a memory device with improved writing and erasing characteristics during operations at a low voltage and a low current. The memory element includes a first electrode, a memory layer, and a second electrode in this order. The memory layer includes a resistance change layer provided on the first electrode side, an ion source layer provided on the second electrode side, an intermediate layer provided between the resistance change layer and the ion source layer, and a barrier layer provided at least either between the ion source layer and the intermediate layer, or between the intermediate layer and the resistance change layer, and the barrier layer containing a transition metal or a nitride thereof.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: April 15, 2014
    Assignee: Sony Corporation
    Inventors: Kazuhiro Ohba, Takeyuki Sone, Masayuki Shimuta, Shuichiro Yasuda
  • Patent number: 8675393
    Abstract: Provided is a method for driving a non-volatile memory element in which a variable resistance element including a first electrode, a second electrode, and a variable resistance layer capable of reversibly changing between a high resistance state and a low resistance state with application of electrical signals having different polarities is connected in series with a current steering element having bidirectional rectifying characteristics with respect to an applied voltage. After the non-volatile memory element is manufactured, the resistance value of the variable resistance layer is reduced from a resistance value in the initial resistance state higher than that in the high resistance state by applying, to the non-volatile memory element, a voltage pulse having the polarity identical to that of the voltage pulse for changing the variable resistance layer from the low resistance state to the high resistance state in the normal operations.
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: March 18, 2014
    Assignee: Panasonic Corporation
    Inventors: Koji Katayama, Takeshi Takagi, Mitsuteru Iijima
  • Patent number: 8665644
    Abstract: A stacked semiconductor memory device comprises a semiconductor substrate having a functional circuit, a plurality of memory cell array layers, and at least one connection layer. The memory cell array layers are stacked above the semiconductor substrate. The connection layers are stacked above the semiconductor substrate independent of the memory cell array layers. The connection layers electrically connect memory cell selecting lines arranged on the memory cell array layers to the functional circuit.
    Type: Grant
    Filed: April 17, 2013
    Date of Patent: March 4, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chul-Woo Park, Hong-Sun Hwang, In-Gyu Baek, Dong-Hyun Sohn
  • Patent number: 8630113
    Abstract: An integrated circuit (IC) includes a memory circuit. The memory circuit includes a plurality of thyristors. The plurality of thyristors are coupled in tandem.
    Type: Grant
    Filed: November 25, 2008
    Date of Patent: January 14, 2014
    Assignee: Altera Corporation
    Inventors: Yanzhong Xu, Jeffrey T. Watt
  • Patent number: 8625322
    Abstract: A three-dimensional array read/write (R/W) memory elements is formed across multiple layers of planes positioned at different distances above a semiconductor substrate. It is preferable to operate the R/W elements with low current and high resistive states. The resistance of these resistive states depends also on the dimension of the R/W elements and is predetermined by the process technology. A sheet electrode in series with the R/W element and a method of forming it provide another degree of freedom to adjust the resistance of the R/W memory element. The thickness of the sheet electrode is adjusted to obtain a reduced cross-sectional contact in the circuit path from the word line to the bit line. This allows the R/W memory element to have a much increased resistance and therefore to operate with much reduced currents. The sheet electrode is formed with little increase in cell size.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: January 7, 2014
    Assignee: SanDisk 3D LLC
    Inventors: George Samachisa, Johann Alsmeier
  • Publication number: 20140003140
    Abstract: Apparatuses and methods can include write schemes for a thyristor memory cell in which an access pulse applied to the gate of the thyristor memory cell is adjusted relative to the data pulse to write data into the thyristor memory cell. Some of the write schemes may substantially reduce or eliminate an unselected data line disturb. In various embodiments, the thyristor memory cell can be structured with two control nodes and its cathode or anode coupled to a reference voltage node common to all thyristor memory cells in a memory array. Additional apparatuses and methods are disclosed.
    Type: Application
    Filed: June 27, 2012
    Publication date: January 2, 2014
    Inventor: Rajesh N. Gupta
  • Publication number: 20130314986
    Abstract: Some embodiments include thyristors having first and second electrode regions, first and second base regions, and material having a bandgap of at least 1.2 eV in at least one of the regions. The first base region is between the first electrode region and the second base region, and the second base region is between the second electrode region and the first base region. The first base region interfaces with the first electrode region at a first junction, and interfaces with the second base region at a second junction. The second base region interfaces with the second electrode region at a third junction. A gate is along the first base region, and in some embodiments does not overlap either of the first and second junctions. Some embodiments include methods of programming thyristors, and some embodiments include methods of forming thyristors.
    Type: Application
    Filed: August 1, 2013
    Publication date: November 28, 2013
    Applicant: Micron Technology, Inc.
    Inventors: Farid Nemati, Scott T. Robins, Rajesh N. Gupta
  • Patent number: 8587996
    Abstract: Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for biasing a direct injection semiconductor memory device including the steps of applying a first non-negative voltage potential to a first region via a bit line and applying a second non-negative voltage potential to a second region via a source line. The method may also include applying a third voltage potential to a word line, wherein the word line may be spaced apart from and capacitively to a body region that may be electrically floating and disposed between the first region and the second region. The method may further include applying a fourth positive voltage potential to a third region via a carrier injection line, wherein the third region may be disposed below at least one of the first region, the body region, and the second region.
    Type: Grant
    Filed: July 26, 2010
    Date of Patent: November 19, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Yogesh Luthra
  • Patent number: 8576607
    Abstract: An integrated circuit and methods of operating same are described. In an embodiment of the integrated circuit included is an array of memory cells, where each of the memory cells includes a resistance-change storage element and a thyristor-based storage element coupled in series. In embodiments of the methods included are methods for data transfer, data tracking, and operating a memory array.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: November 5, 2013
    Inventor: Farid Nemati
  • Patent number: 8542540
    Abstract: Embodiments of tunneling barriers and methods for same can embed modules exhibiting a monodispersion characteristic into a dielectric layer (e.g., between first and second layers forming a dielectric layer). In one embodiment, by embedding C60 molecules inbetween first and second insulating layers forming a dielectric layer, a field sensitive tunneling barrier can be implemented. In one embodiment, the tunneling barrier can be between a floating gate and a channel in a semiconductor structure. In one embodiment, a tunneling film can be used in nonvolatile memory applications where C60 provides accessible energy levels to prompt resonant tunneling through the dielectric layer upon voltage application.
    Type: Grant
    Filed: March 26, 2010
    Date of Patent: September 24, 2013
    Assignee: Cornell University
    Inventors: Edwin C. Kan, Tuo-Hung Hou
  • Patent number: 8441881
    Abstract: Method and integrated circuit for tracking for read and inverse write back of a group of thyristor-based memory cells is described. The method includes: reading the group of memory cells to obtain read data, and writing back opposite data states for the read data to the group of memory cells. The group of memory cells includes data cells and at least one check cell for check data, where the check data indicates polarity of the read data. The integrated circuit includes a grouping of memory cells of an array of memory cells including data cells and at least one check cell, and sense amplifiers. The at least one check cell is to track inversion/non-inversion status of the data cells associated therewith, and the sense amplifiers are coupled to obtain read information from the grouping and to write back data states opposite of those of the read information.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: May 14, 2013
    Assignee: T-RAM Semiconductor
    Inventor: Farid Nemati
  • Patent number: 8441852
    Abstract: A stacked semiconductor memory device comprises a semiconductor substrate having a functional circuit, a plurality of memory cell array layers, and at least one connection layer. The memory cell array layers are stacked above the semiconductor substrate. The connection layers are stacked above the semiconductor substrate independent of the memory cell array layers. The connection layers electrically connect memory cell selecting lines arranged on the memory cell array layers to the functional circuit.
    Type: Grant
    Filed: February 10, 2011
    Date of Patent: May 14, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chul-Woo Park, Hong-Sun Hwang, In-Gyu Baek, Dong-Hyun Sohn
  • Patent number: 8270212
    Abstract: According to one embodiment, a semiconductor memory device includes first and second upper-layer contact members. The upper-layer contact members are arranged alternately with the first upper-layer contact members in a first direction and shifted in a second direction orthogonal to the first direction. Plugs are formed on the second upper-layer contact members. First metal wirings are provided on the first upper-layer contact members. Second metal wirings are provided on the plugs. A height of a top surface of the plugs is higher than a top surface of the first metal wirings. A width of a bottom surface of the first metal wirings in a shorter-side direction is shorter than a width of a top surface of the first metal wirings. A width of a bottom surface of the second metal wirings in a shorter-side direction is shorter than a width of a top surface of the second metal wirings.
    Type: Grant
    Filed: October 22, 2010
    Date of Patent: September 18, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Izumi, Takeshi Kamigaichi
  • Patent number: 8189364
    Abstract: Embodiments of the invention relate generally to semiconductors and semiconductor fabrication techniques, and more particularly, to devices, integrated circuits, memory cells and arrays, and methods to use silicon carbide structures to retain amounts of charge indicative of a resistive state in, for example, a charge-controlled resistor of a memory cell. In some embodiments, a memory cell comprises a silicon carbide structure including a charge reservoir configured to store an amount of charge carriers constituting a charge cloud. The amount of charge carriers in the charge cloud can represent a data value. Further, the memory cell includes a resistive element in communication with the charge reservoir and is configured to provide a resistance as a function of the amount of charge carriers in the charge reservoir. The charge reservoir is configured to modulate the size of the charge cloud to change the data value.
    Type: Grant
    Filed: December 16, 2009
    Date of Patent: May 29, 2012
    Assignee: Qs Semiconductor Australia Pty Ltd.
    Inventors: Sima Dimitrijev, Herbert Barry Harrison
  • Patent number: 8094491
    Abstract: A semiconductor device includes a memory cell including a thyristor element with a gate having a pnpn structure formed in a semiconductor substrate, and a plurality of access transistors formed on the semiconductor substrate and each connected at a first terminal thereof to a storage node at one terminal of the thyristor element such that a potential at the storage node can be transmitted to bit lines different from each other, the gate of the thyristor element and the gates of the plurality of access transistors of the memory cell being connected to word lines different from one another.
    Type: Grant
    Filed: August 27, 2008
    Date of Patent: January 10, 2012
    Assignee: Sony Corporation
    Inventors: Makoto Kitagawa, Mitsuo Soneda
  • Patent number: 7983065
    Abstract: A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.
    Type: Grant
    Filed: April 8, 2009
    Date of Patent: July 19, 2011
    Assignee: Sandisk 3D LLC
    Inventor: George Samachisa
  • Patent number: 7969777
    Abstract: A new memory cell can contain only a single thyristor. There is no need to include an access transistor in the cell. In one embodiment, the thyristor is a thin capacitively coupled thyristor. The new memory cell can be connected to word, bit, and control lines in several ways to form different memory arrays. Timing and voltage levels of word, bit and control lines are disclosed.
    Type: Grant
    Filed: December 1, 2008
    Date of Patent: June 28, 2011
    Assignee: T-RAM Semiconductor, Inc.
    Inventors: Hyun-Jin Cho, Farid Nemati
  • Patent number: 7940560
    Abstract: A memory device is provided which includes a write bit line, a read bit line, and at least one memory cell. The memory cell includes a write access transistor, a read access transistor coupled to the read bit line and to the first write access transistor, and a gated-lateral thyristor (GLT) device coupled to the first write access transistor. Among its many features, the memory cell prevents read disturbances during read operations by decoupling the read and write bit lines.
    Type: Grant
    Filed: May 29, 2008
    Date of Patent: May 10, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Hyun-Jin Cho
  • Patent number: 7936622
    Abstract: Various embodiments of the present invention are generally directed to an apparatus and associated method for handling defective bits in a multi-layer integrated memory device. In accordance with some embodiments, the multi-layer integrated memory device is formed from a plurality of vertically stacked semiconductor layers each having a number of storage sub-arrays and redundant sub-arrays. Each semiconductor layer is tested to determine a defect rate for each array, and a defective portion of a first semiconductor layer having a relatively higher defect rate is stored to a redundant sub-array of a second semiconductor layer having a relatively lower defect rate.
    Type: Grant
    Filed: July 13, 2009
    Date of Patent: May 3, 2011
    Assignee: Seagate Technology LLC
    Inventors: Hai Li, Yiran Chen, Dadi Setiadi, Harry Hongyue Liu, Brian Lee
  • Patent number: 7916530
    Abstract: In various embodiments, an addressable storage matrix includes a first plurality of intersection points, at least some of which are bridged by two-terminal non-linear elements that exhibit a threshold below which current flow is significantly lower than if the threshold is exceeded, as well as, disposed at each intersection point bridged by a non-linear element, a programmable material in series with the non-linear element and determining a bit state for the corresponding intersection point.
    Type: Grant
    Filed: December 8, 2009
    Date of Patent: March 29, 2011
    Assignee: Contour Semiconductor, Inc.
    Inventor: Daniel R. Shepard
  • Patent number: 7897440
    Abstract: A semiconductor device may comprise a plurality of memory cells. A memory cell may comprise a thyristor, at least a portion of which is formed in a pillar of semiconductor material. The pillar may comprise sidewalls defining a cylindrical circumference of a first diameter. In a particular embodiment, the pillars associated with the plurality of memory cells may define rows and columns of an array. In a further embodiment, a pillar may be spaced by a first distance of magnitude up to the first diameter relative to a neighboring pillar within its row. In an additional further embodiment, the pillar may be spaced by a second distance of a magnitude up to twice the first diameter, relative to a neighboring pillar within its column.
    Type: Grant
    Filed: November 24, 2008
    Date of Patent: March 1, 2011
    Assignee: T-RAM Semiconductor, Inc.
    Inventor: Andrew E. Horch
  • Patent number: 7894256
    Abstract: A new memory cell contains only a single thyristor without the need to include an access transistor. A memory array containing these memory cells can be fabricated on bulk silicon wafer. The memory cell contains a thyristor body and a gate. The thyristor body has two end region and two base regions, and it is disposed on top of a well. The memory cell is positioned between two isolation regions, and the isolation regions are extended below the well. A first end region is connected to one of a word line, a bit line and a third line. A second end region is connected to another of the word line, bit line, and third line. The gate is connected to the remaining of the word line, bit line and third line.
    Type: Grant
    Filed: July 25, 2007
    Date of Patent: February 22, 2011
    Assignee: T-RAM Semiconductor, Inc.
    Inventors: Farid Nemati, Scott Robins, Kevin J. Yang
  • Patent number: 7843740
    Abstract: A method for driving a nonvolatile semiconductor memory device is provided. The nonvolatile semiconductor memory device includes a semiconductor layer having a channel, a first insulating film provided on the channel, a floating electrode provided on the first insulating film, a second insulating film provided on the floating electrode, and a gate electrode provided on the second insulating film, and changes its data memory state by injection of charges into the floating electrode.
    Type: Grant
    Filed: November 11, 2008
    Date of Patent: November 30, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Jun Fujiki
  • Patent number: 7764540
    Abstract: By activating a word line and a bit line in parallel with a storage transistor set to OFF, the potential conditions of the charge line, and the word line, and the bit line are controlled so that the potential of a body region is increased by a leak current flowing from a connecting node to the body region in a period until the storage transistor is turned ON.
    Type: Grant
    Filed: March 1, 2006
    Date of Patent: July 27, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Fukashi Morishita, Kazutami Arimoto
  • Patent number: 7755937
    Abstract: A semiconductor device, includes a memory cell including a thyristor element with a gate having a pnpn structure formed on a semiconductor substrate and having first and second terminals, and an access transistor formed on the semiconductor substrate and having first and second terminals connected to a bit line and the first terminal of the thyristor element, respectively, and a control section including a load current element whose load current flows, upon reading out operation, to the second terminal side of the thyristor element and configured to carry out access control to the memory cell.
    Type: Grant
    Filed: September 10, 2008
    Date of Patent: July 13, 2010
    Assignee: Sony Corporation
    Inventor: Makoto Kitagawa
  • Patent number: 7750392
    Abstract: An embodiment of an embedded cache memory in an image sensor comprises a memory cell array wherein the memory cells are substantially isolated from laterally adjacent memory. The memory cell array includes a plurality of memory cells. Each of the memory cells is formed in a standard CMOS image sensor process without the need for SOI processes. Each cell includes first and second n-type and p-type regions arranged around a vertically integrated gate. Data is written to a cell by causing carriers to accumulate in the body of the device through carrier generation mechanisms that may include impact ionization, band-to-band tunneling and/or channel-initiated secondary hot electrons.
    Type: Grant
    Filed: March 3, 2008
    Date of Patent: July 6, 2010
    Assignee: Aptina Imaging Corporation
    Inventor: Chandra Mouli
  • Patent number: 7692960
    Abstract: A method for improving an over erasing effect of a charge-trapping memory cell. The charge-trapping memory cell has a transistor, which has a first terminal coupled to a first bit line and a second terminal coupled to a second bit line. First, the method erases the charge-trapping memory cell. Then, after the charge-trapping memory cell is completely erased, the first bit line is electrically connected to the second bit line to make a voltage level of the first bit line equal a voltage level of the second bit line such that the voltage level of the first terminal of the transistor equals the voltage level of the second terminal of the transistor.
    Type: Grant
    Filed: December 20, 2006
    Date of Patent: April 6, 2010
    Assignee: Macronix International Co., Ltd.
    Inventors: Chang-Ting Chen, Chun-Jen Huang
  • Patent number: 7652916
    Abstract: One of the simplest forms of data storage devices is the diode array storage device. However, a problem with diode array storage devices is that as the size of the array increases, the number of non-addressed diodes connected between a given selected row or column of the array and the non-addressed columns or rows of the array, respectively, also becomes very large. While the leakage current through any one non-addressed diode on the selected row or column will have little impact on the operation of the device, the cumulative leakage through multiple thousands of non-addressed diodes can become significant. This aggregate leakage current can become great enough that the output voltage can be shifted such that the threshold for distinguishing between a one state and a zero state of the addressed diode location can become obscured and can result in a misreading of the addressed diode location. The present invention is a means to manage the leakage currents in a diode array storage device.
    Type: Grant
    Filed: April 22, 2008
    Date of Patent: January 26, 2010
    Assignee: Contour Semiconductor, Inc.
    Inventor: Daniel R. Shepard
  • Publication number: 20100002502
    Abstract: A content addressable memory includes a first plurality of search lines, a second plurality of search lines, a first match line, and a storage location. Each search line of the first plurality of search lines receives a corresponding high voltage level or low voltage level during a match detect operation, and each search line of the second plurality of search lines to receive a corresponding high voltage level or low voltage level during the match detect operation. The storage location of the content addressable memory includes a plurality of CAM cells, each CAM cell a first thyristor and second thyristor.
    Type: Application
    Filed: July 3, 2008
    Publication date: January 7, 2010
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Sang Dhong, Jin Cho, John Wuu, Gurupada Mandal
  • Patent number: 7636251
    Abstract: A nonvolatile memory device may be operated in a multi-bit mode at a lower operating current and with higher integrated of the memory device. A first buried electrode may be used as a first bit line, a second buried electrode may be used as a second bit line, and/or a gate electrode may be used as a word line. First and second resistance layers may be programmed with 2-bit data and the 2-bit data may be read from the first and second resistance layers. More than 2-bit data may be programmed and read using more than 2 buried electrodes.
    Type: Grant
    Filed: July 12, 2007
    Date of Patent: December 22, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yoon-dong Park, Kyoung-lee Cho, Jae-woong Hyun, Sung-jae Byun
  • Patent number: 7630235
    Abstract: A memory cell is provided which includes an access transistor and a gated lateral thyristor (GLT) device. The access transistor includes a source node. The gated lateral thyristor (GLT) device includes an anode node coupled to the source node of the access transistor.
    Type: Grant
    Filed: March 28, 2007
    Date of Patent: December 8, 2009
    Assignee: GlobalFoundries Inc.
    Inventor: Hyun-Jin Cho
  • Patent number: 7619917
    Abstract: A memory device includes a plurality of word lines extending as rows and bit lines extending as columns. A memory cell is coupled between a word line and a bit line, wherein the memory cell includes a unipolar memory element selectively coupled to the bit line via a trigger element.
    Type: Grant
    Filed: November 28, 2006
    Date of Patent: November 17, 2009
    Assignee: Qimonda North America Corp.
    Inventors: Thomas Nirschl, Thomas Happ, Jan Boris Philipp
  • Publication number: 20090219426
    Abstract: An embodiment of an embedded cache memory in an image sensor comprises a memory cell array wherein the memory cells are substantially isolated from laterally adjacent memory. The memory cell array includes a plurality of memory cells. Each of the memory cells is formed in a standard CMOS image sensor process without the need for SOI processes. Each cell includes first and second n-type and p-type regions arranged around a vertically integrated gate. Data is written to a cell by causing carriers to accumulate in the body of the device through carrier generation mechanisms that may include impact ionization, band-to-band tunneling and/or channel-initiated secondary hot electrons.
    Type: Application
    Filed: March 3, 2008
    Publication date: September 3, 2009
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Chandra Mouli
  • Publication number: 20090213648
    Abstract: An integrated circuit is provided comprising an array of memory cells connected by word and bit lines, respectively, wherein each memory cell comprises a thyristor structure, an anode terminal that connects the thyristor structure with a respective bit line, a gate terminal that connects the thyristor structure with a respective word line, and a cathode terminal. The integrated circuit further comprises a drive/sensing circuitry configured to apply a first sequence of voltage signals at the anode terminal and the gate terminal, wherein the voltage signals are defined with respect to the cathode terminal. The first sequence comprises a first voltage signal at the anode terminal, a second voltage signal at the gate terminal, and thereafter a combination of a third voltage signal at the anode terminal and a fourth voltage signal at the gate terminal, wherein the third voltage signal is lower than the first voltage signal and lower than the fourth voltage signal.
    Type: Application
    Filed: December 19, 2008
    Publication date: August 27, 2009
    Inventor: Stefan Slesazeck
  • Publication number: 20090086537
    Abstract: A semiconductor device, includes a memory cell including a thyristor element with a gate having a pnpn structure formed on a semiconductor substrate and having first and second terminals, and an access transistor formed on the semiconductor substrate and having first and second terminals connected to a bit line and the first terminal of the thyristor element, respectively, and a control section including a load current element whose load current flows, upon reading out operation, to the second terminal side of the thyristor element and configured to carry out access control to the memory cell.
    Type: Application
    Filed: September 10, 2008
    Publication date: April 2, 2009
    Applicant: Sony Corporation
    Inventor: Makoto Kitagawa
  • Publication number: 20090086536
    Abstract: A semiconductor device includes a memory cell including a thyristor element with a gate having a pnpn structure formed in a semiconductor substrate, and a plurality of access transistors formed on the semiconductor substrate and each connected at a first terminal thereof to a storage node at one terminal of the thyristor element such that a potential at the storage node can be transmitted to bit lines different from each other, the gate of the thyristor element and the gates of the plurality of access transistors of the memory cell being connected to word lines different from one another.
    Type: Application
    Filed: August 27, 2008
    Publication date: April 2, 2009
    Applicant: Sony Corporation
    Inventors: Makoto Kitagawa, Mitsuo Soneda
  • Patent number: RE44950
    Abstract: A method for driving a nonvolatile semiconductor memory device is provided. The nonvolatile semiconductor memory device includes a semiconductor layer having a channel, a first insulating film provided on the channel, a floating electrode provided on the first insulating film, a second insulating film provided on the floating electrode, and a gate electrode provided on the second insulating film, and changes its data memory state by injection of charges into the floating electrode.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: June 17, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Jun Fujiki