Complementary Conductivity Patents (Class 365/181)
  • Patent number: 9640256
    Abstract: An integrated circuit (IC) device includes a static random access memory (SRAM) array, and a resistive memory (resistive memory) array. A first set of programmable resistive elements in the resistive memory array are used to store data from memory cells in the SRAM array. Sense amplifier circuitry is couplable to the SRAM array and the resistive memory array. An arbiter is configured to assert an resistive memory enable signal to couple the sense amplifier circuitry to the resistive memory array and decouple the sense amplifier circuitry from the SRAM array during a resistive memory read operation, and to couple the sense amplifier to the SRAM array and decouple the sense amplifier circuitry from the resistive memory array during an SRAM read operation.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: May 2, 2017
    Assignee: NXP USA, Inc.
    Inventors: Anirban Roy, Jon S. Choy, Michael A. Sadd
  • Patent number: 9449709
    Abstract: A volatile and one-time program (OTP) compatible asymmetric memory cell may include a first pull-up transistor having a first threshold voltage. The asymmetric memory cell may also include a second pull-up transistor having a second threshold voltage that differs from the first threshold voltage. The asymmetric memory cell may further include a switch coupled to a well of the first pull-up transistor and the second pull-up transistor to alternate between a program voltage (Vpg) and a power supply voltage. The asymmetric memory cell may also include a peripheral switching circuit to control programming of the asymmetric memory cell.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: September 20, 2016
    Assignee: QUALCOMM INCORPORATED
    Inventors: Xia Li, Xiaonan Chen, Niladri Narayan Mojumder, Zhongze Wang, Weidan Li
  • Patent number: 9378314
    Abstract: A system and method for designing integrated circuits and predicting current mismatch in a metal oxide semiconductor (MOS) array. A first subset of cells in the MOS array is selected and current measured for each of these cells. Standard deviation of current for each cell in the first subset of cells is determined with respect to current of a reference cell. Standard deviation of local variation can be determined using the determined standard deviation of current for one or more cells in the first subset. Standard deviations of variation induced by, for example, poly density gradient effects, in the x and/or y direction of the array can then be determined and current mismatch for any cell in the array determined therefrom.
    Type: Grant
    Filed: August 25, 2014
    Date of Patent: June 28, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Amit Kundu, Jaw-Juinn Horng, Yung-Chow Peng, Shih-Cheng Yang, Chung-Kai Lin
  • Patent number: 8964457
    Abstract: A circuit includes a Static Random Access Memory (SRAM) array. An SRAM cell is in the SRAM array and includes a p-well region, a first and a second n-well region on opposite sides of the p-well region, and a first and a second pass-gate FinFET. The first pass-gate FinFET and the second pass-gate FinFET are p-type FinFETs. A CVss line is over the p-well region, wherein the CVss line is parallel to an interface between the p-well region and the first n-well region. A bit-line and a bit-line bar are on opposite sides of the CVss line. A CVdd line crosses over the SRAM cell. A CVss control circuit is connected to the CVss line. The CVss control circuit is configured to provide a first CVss voltage and a second CVss voltage to the CVss line, with the first and the second CVss voltage being different from each other.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: February 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon-Jhy Liaw
  • Patent number: 8901704
    Abstract: An integrated circuit and a manufacturing method thereof are provided. A chip size can be reduced by forming a memory device in which a ferroelectric capacitor region is laminated on a DRAM. The integrated circuit includes a cell array region having a capacitor, a peripheral circuit region, and a ferroelectric capacitor region being formed on an upper layer of the cell array region and the peripheral circuit region, and having a ferroelectric capacitor device.
    Type: Grant
    Filed: April 20, 2007
    Date of Patent: December 2, 2014
    Assignee: SK Hynix Inc.
    Inventor: Hee Bok Kang
  • Patent number: 8901747
    Abstract: A chip layout for a high speed semiconductor device is disclosed. The chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. A serial interface is centrally located to reduce latency, power and propagation delays. Stacked die that contain one or more devices with the chip layout are characterized by having improved latency, bandwidth, power consumption, and propagation delays.
    Type: Grant
    Filed: July 29, 2010
    Date of Patent: December 2, 2014
    Assignee: MoSys, Inc.
    Inventors: Michael J. Miller, Mark Baumann, Richard S. Roy
  • Patent number: 8890332
    Abstract: A chip layout for a high speed semiconductor device is disclosed. The chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. A serial interface is centrally located to reduce latency, power and propagation delays. Stacked die that contain one or more devices with the chip layout are characterized by having improved latency, bandwidth, power consumption, and propagation delays.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: November 18, 2014
    Assignee: MoSys, Inc.
    Inventors: Michael J. Miller, Mark William Baumann, Richard S. Roy
  • Patent number: 8830732
    Abstract: A Static Random Access Memory (SRAM) cell includes a first long boundary and a second long boundary parallel to a first direction, and a first short boundary and a second short boundary parallel to a second direction perpendicular to the first direction. The first and the second long boundaries are longer than, and form a rectangle with, the first and the second short boundaries. A CVss line carrying a VSS power supply voltage crosses the first long boundary and the second long boundary. The CVss line is parallel to the second direction. A bit-line and a bit-line bar are on opposite sides of the CVss line. The bit-line and the bit-line bar are configured to carry complementary bit-line signals.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: September 9, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon-Jhy Liaw
  • Publication number: 20130286729
    Abstract: Non-volatile memory cells and methods. In an apparatus, an array of non-volatile storage cells formed in a portion of a semiconductor substrate includes a first storage cell having a first bit cell and a second bit cell; a second storage cell having a third bit cell and a fourth bit cell; and a column multiplexer coupled to a plurality of column lines, selected ones of the column lines coupled to a first source/drain terminal of the first and the second storage cell and coupled to a second source/drain terminal of the first and second storage cell, the column multiplexer coupling a voltage to one of the column lines connected to the first storage cell corresponding to the data, and coupling a voltage to one of the column lines connected to the second storage cell corresponding to the complementary data. Methods for operating the non-volatile memory cells are disclosed.
    Type: Application
    Filed: April 30, 2012
    Publication date: October 31, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Yue-Der Chih
  • Patent number: 8530979
    Abstract: Provided is a semiconductor package which includes: a semiconductor substrate; a functional element that is disposed on one surface of the semiconductor substrate; a protection substrate that is disposed in an opposite side of that surface of the semiconductor substrate with a predetermined gap from a surface of the semiconductor substrate; and a junction member that is disposed to surround the functional element and bonds the semiconductor substrate and the protection substrate together, wherein the functional element has a shape different from a shape of a plane surrounded by the junction member in that surface of the semiconductor substrate, or is disposed in a region deviated from a central region of the plane surrounded by the junction member in that surface of the semiconductor substrate.
    Type: Grant
    Filed: October 1, 2010
    Date of Patent: September 10, 2013
    Assignee: Fujikura Ltd.
    Inventors: Shingo Ogura, Yuki Suto
  • Patent number: 8493814
    Abstract: A semiconductor memory device has a memory cell array, a first transistor of a first conductivity type, a second transistor of a second conductivity type and a third transistor of the first conductivity type. A source or drain of the first transistor is connected to each of word lines. A drain of the second transistor is connected to a gate of the first transistor. A source of the third transistor is connected to the gate of the first transistor. The gates of the second transistor and the third transistor are not connected, a source of the second transistor is not connected to a drain of the third transistor, and the gate of the second transistor and the drain of the third transistor have different voltage levels corresponding to opposite logic levels each other.
    Type: Grant
    Filed: February 14, 2012
    Date of Patent: July 23, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Nakamura, Kenichi Imamiya
  • Patent number: 8451654
    Abstract: In two inverters included in a latch in a memory cell, the source or drain of a PMOS load transistor connected to a memory node is cut off, and the source or drain of an NMOS drive transistor connected to another memory node is cut off, whereby internal data is fixed or permanently stored in the memory cell while ensuring a resistance to damage to the gate of the transistor and without impairing the regularity of the layout.
    Type: Grant
    Filed: October 3, 2011
    Date of Patent: May 28, 2013
    Assignee: Panasonic Corporation
    Inventor: Tsuyoshi Koike
  • Patent number: 8432719
    Abstract: A 3D stacked AND-type flash memory structure comprises several horizontal planes of memory cells arranged in a three-dimensional array, and each horizontal plane comprising several word lines and several of charge trapping multilayers arranged alternately, and the adjacent word lines spaced apart from each other with each charge trapping multilayer interposed between; a plurality of sets of bit lines and source lines arranged alternately and disposed vertically to the horizontal planes; and a plurality of sets of channels and sets of insulation pillars arranged alternatively, and disposed perpendicularly to the horizontal planes, wherein one set of channels is sandwiched between the adjacent sets of bit lines and source lines.
    Type: Grant
    Filed: January 18, 2011
    Date of Patent: April 30, 2013
    Assignee: Macronix International Co., Ltd.
    Inventor: Hang-Ting Lue
  • Publication number: 20120275217
    Abstract: A memory array compatible with dynamic random access memories (DRAM) and static random access memories (SRAM) is disclosed. The memory array includes a first sense amplifier (700) having a first bit line (754) extending in a first direction and a second bit line (752) extending in a second direction parallel to the first bit line. A second sense amplifier (704) has a third bit line (756) adjacent and parallel to the first bit line. The third bit line remains inactive while the first bit line is active.
    Type: Application
    Filed: June 3, 2012
    Publication date: November 1, 2012
    Inventor: Robert N. Rountree
  • Patent number: 8295078
    Abstract: An integrated circuit device (for example, logic or discrete memory device) comprising a memory cell including a punch-through mode transistor, wherein the transistor includes a source region, a drain region, a gate, a gate insulator, and a body region having a storage node which is located, at least in part, immediately beneath the gate insulator. The memory cell includes at least two data states which are representative of an amount of charge in the storage node in the body region. First circuitry is coupled to the punch-through mode transistor of the memory cell to: (1) generate first and second sets of write control signals, and (2a) apply the first set of write control signals to the transistor to write a first data state in the memory cell and (2b) apply the second set of write control signals to the transistor to write a second data state in the memory cell.
    Type: Grant
    Filed: April 22, 2011
    Date of Patent: October 23, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Serguei Okhonin, Mikhail Nagoga
  • Patent number: 8213211
    Abstract: A method and system for improving reliability of OTP memories, and in particular anti-fuse memories, by storing one bit of data in at least two OTP memory cells. Therefore each bit of data is read out by accessing the at least two OTP memory cells at the same time in a multi-cell per bit mode. By storing one bit of data in at least two OTP memory cells, defective cells or weakly programmable cells are compensated for since the additional cell or cells provide inherent redundancy. Program reliability is ensured by programming the data one bit at a time, and verifying all programmed bits in a single-ended read mode, prior to normal operation where the data is read out in the multi-cell per bit mode. Programming and verification is achieved at high speed and with minimal power consumption using a novel program/verify algorithm for anti-fuse memory. In addition to improved reliability, read margin and read speed are improved over single cell per bit memories.
    Type: Grant
    Filed: February 5, 2010
    Date of Patent: July 3, 2012
    Assignee: Sidense Corp.
    Inventor: Wlodek Kurjanowicz
  • Patent number: 8054703
    Abstract: An active termination circuit is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage through at least one PMOS transistor and to ground through at least one NMOS transistor. The impedances of the transistors are controlled by a control circuit that generates a first control signal to set the impedance of another PMOS transistor to be equal to a first predetermined resistance, and generates a second control signal to set the impedance of another NMOS transistor to be equal to a second predetermined resistance. The first control signal is used to control all of the PMOS transistors and the second control signal is used to control all of the NMOS transistors. As a result, the PMOS and NMOS transistors coupled to each input terminal have impedances corresponding to the first and second resistances, respectively.
    Type: Grant
    Filed: April 15, 2010
    Date of Patent: November 8, 2011
    Assignee: Round Rock Research, LLC
    Inventor: Chris G. Martin
  • Patent number: 8004042
    Abstract: In accordance with an embodiment of the present invention, a static random access memory (SRAM) cell comprises a first pull-down transistor, a first pull-up transistor, a first pass-gate transistor, a second pull-down transistor, a second pull-up transistor, a second pass-gate transistor, a first linear intra-cell connection, and a second linear intra-cell connection. Active areas of the transistors are disposed in a substrate, and longitudinal axes of the active areas of the transistors are all parallel. The first linear intra-cell connection electrically couples the active area of the first pull-down transistor, the active area of the first pull-up transistor, and the active area of the first pass-gate transistor to a gate electrode of the second pull-down transistor and a gate electrode of the second pull-up transistor.
    Type: Grant
    Filed: March 20, 2009
    Date of Patent: August 23, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Lie-Yong Yang, Feng-Ming Chang, Chang-Ta Yang, Ping-Wei Wang
  • Patent number: 7965540
    Abstract: A digital logic storage structure includes cross coupled first and second complementary metal oxide semiconductor (CMOS) inverters formed on a semiconductor substrate, the CMOS inverters including a first storage node and a second storage node that is the logical complement of the first storage node; both of the first and second storage nodes each selectively coupled to a deep trench capacitor through a switching transistor, with the switching transistors controlled by a common capacitance switch line coupled to gate conductors thereof; wherein, in a first mode of operation, the switching transistors are rendered nonconductive so as to isolate the deep trench capacitors from the inverter storage nodes and, in a second mode of operation, the switching transistors are rendered conductive so as to couple the deep trench capacitors to their respective storage nodes, thereby providing increased resistance of the storage nodes to single event upsets (SEUs).
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: June 21, 2011
    Assignee: International Business Machines Corporation
    Inventors: Ethan H. Cannon, Toshiharu Furukawa, David Horak, Charles W. Koburger, III, Jack A. Mandelman
  • Patent number: 7933142
    Abstract: An integrated circuit device (for example, logic or discrete memory device) comprising a memory cell including a punch-through mode transistor, wherein the transistor includes a source region, a drain region, a gate, a gate insulator, and a body region having a storage node which is located, at least in part, immediately beneath the gate insulator. The memory cell includes at least two data states which are representative of an amount of charge in the storage node in the body region. First circuitry is coupled to the punch-through mode transistor of the memory cell to: (1) generate first and second sets of write control signals, and (2a) apply the first set of write control signals to the transistor to write a first data state in the memory cell and (2b) apply the second set of write control signals to the transistor to write a second data state in the memory cell.
    Type: Grant
    Filed: April 30, 2007
    Date of Patent: April 26, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Serguei Okhonin, Mikhail Nagoga
  • Patent number: 7760558
    Abstract: Systems and methods for improving efficiency of a voltage booster for read mode operations of memory cells and discharging a boosted supply voltage safely are disclosed. The system contains a plurality of boosting stages coupled in series including a plurality of boosting capacitors, a plurality of isolators. The isolator can be used to prevent boosting of one capacitor from negatively affecting a charge of the other adjacent capacitor to improve the efficiency of the voltage booster. A voltage booster circuit can accurately boost a supply voltage with a suitable number of boosting stages depending on a level of the supply voltage being provided. Since boosters contain a suitable number of boosting stages, the boosters can discharge a boosted voltage sequentially. With this sequential discharge method, memory cells can not have a hot switching problem.
    Type: Grant
    Filed: January 15, 2008
    Date of Patent: July 20, 2010
    Assignee: Spansion LLC
    Inventors: Chin-Ghee Ch'ng, Kuan-Cheng Tang
  • Patent number: 7755937
    Abstract: A semiconductor device, includes a memory cell including a thyristor element with a gate having a pnpn structure formed on a semiconductor substrate and having first and second terminals, and an access transistor formed on the semiconductor substrate and having first and second terminals connected to a bit line and the first terminal of the thyristor element, respectively, and a control section including a load current element whose load current flows, upon reading out operation, to the second terminal side of the thyristor element and configured to carry out access control to the memory cell.
    Type: Grant
    Filed: September 10, 2008
    Date of Patent: July 13, 2010
    Assignee: Sony Corporation
    Inventor: Makoto Kitagawa
  • Patent number: 7733693
    Abstract: There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory device and technique of reading data from and writing data into memory cells of the memory device. In this regard, in one embodiment of this aspect of the invention, the memory device and technique for operating that device that minimizes, reduces and/or eliminates the debilitating affects of the charge pumping phenomenon. This embodiment of the present invention employs control signals that minimize, reduce and/or eliminate transitions of the amplitudes and/or polarities. In another embodiment, the present invention is a semiconductor memory device including a memory array comprising a plurality of semiconductor dynamic random access memory cells arranged in a matrix of rows and columns.
    Type: Grant
    Filed: April 8, 2008
    Date of Patent: June 8, 2010
    Assignee: Innovative Silicon ISi SA
    Inventors: Richard Ferrant, Serguei Okhonin, Eric Carman, Michel Bron
  • Publication number: 20100134149
    Abstract: An ultra-low-power transconductance device is provided, (FIG. 1b, FIG. 1c), comprising a series connection of a transistor of a first channel type (A) and a transistor of a second channel type (B), the first channel type having a different polarity than the second channel type. The transistors each have a source, a drain and a gate. The source of the transistor of the first channel type (A) is coupled with the source of the transistor of the second channel type (B) and the drain of the transistor of the first channel type (A) is coupled with the gate of the transistor of the second channel type (B).
    Type: Application
    Filed: April 29, 2008
    Publication date: June 3, 2010
    Inventors: David Bol, Denis Flandre, Jean-Didier Legat
  • Patent number: 7715256
    Abstract: An active termination circuit is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage through at least one PMOS transistor and to ground through at least one NMOS transistor. The impedances of the transistors are controlled by a control circuit that generates a first control signal to set the impedance of another PMOS transistor to be equal to a first predetermined resistance, and generates a second control signal to set the impedance of another NMOS transistor to be equal to a second predetermined resistance. The first control signal is used to control all of the PMOS transistors and the second control signal is used to control all of the NMOS transistors. As a result the PMOS and NMOS transistors coupled to each input terminal have impedances corresponding to the first and second resistances, respectively.
    Type: Grant
    Filed: January 10, 2006
    Date of Patent: May 11, 2010
    Assignee: Round Rock Research, LLC
    Inventor: Chris G. Martin
  • Patent number: 7683430
    Abstract: An integrated circuit having a memory cell and/or memory cell array including a plurality of memory cells (as well as techniques for reading, controlling and/or operating, the memory cell, and/or memory cell array). Each memory cell includes at least one transistor having an electrically floating body transistor and an active access element. The electrically floating body region of the transistor forms a storage area or node of the memory cell wherein an electrical charge which is representative of a data state is stored in the electrically floating body region. The active access element is coupled to the electrically floating body transistor to facilitate programming of the memory cell and to provide a relatively large amount of majority carriers to the storage area or node of the memory cell during a write operation.
    Type: Grant
    Filed: December 4, 2006
    Date of Patent: March 23, 2010
    Assignee: Innovative Silicon ISi SA
    Inventor: Serguei Okhonin
  • Patent number: 7656702
    Abstract: Methods and apparatus to provide ultra low voltage, low leakage, high density, and/or variation tolerant memory bit cells are described. In one embodiment, each of the cross-coupled invertors of a memory cell may include a plurality of p-channel transistors. Other embodiments are also described.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: February 2, 2010
    Assignee: Intel Corporation
    Inventors: Sapumal Wijeratne, Matthew W. Ernest, Brian A. Kuns
  • Patent number: 7652910
    Abstract: Provided herein are embodiments of layouts for applying impact ionization potentials across the channel of a selected floating body cell in an array without having to impose the potential on other unselected cells.
    Type: Grant
    Filed: June 30, 2007
    Date of Patent: January 26, 2010
    Assignee: Intel Corporation
    Inventors: Uygar E. Avci, Peter L. D. Chang, Dinesh Somasekhar
  • Patent number: 7630235
    Abstract: A memory cell is provided which includes an access transistor and a gated lateral thyristor (GLT) device. The access transistor includes a source node. The gated lateral thyristor (GLT) device includes an anode node coupled to the source node of the access transistor.
    Type: Grant
    Filed: March 28, 2007
    Date of Patent: December 8, 2009
    Assignee: GlobalFoundries Inc.
    Inventor: Hyun-Jin Cho
  • Patent number: 7626850
    Abstract: Various systems and methods for implementing memory devices are disclosed. For example, some embodiments of the present invention provide sub-threshold memory devices that include a differential bit cell. Such a differential bit cell includes two PMOS transistors, two NMOS transistors, and two inverters. The source of the first PMOS transistor and the source of the second PMOS transistor are electrically coupled to a bit line input, and the source of the first NMOS transistor and the source of the second NMOS transistor are electrically coupled to the bit line input. The gate of the first NMOS transistor and the gate of the second NMOS transistor are electrically coupled to a word line input. The gate of the first PMOS transistor and the gate of the second PMOS transistor are electrically coupled to an inverted version of the word line input.
    Type: Grant
    Filed: April 17, 2007
    Date of Patent: December 1, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Charles M. Branch, Steven C. Bartling
  • Patent number: 7613030
    Abstract: A semiconductor memory device is provided, which comprises an analog switch, a first inverter, a second inverter, and a clocked inverter. A first terminal of the analog switch is electrically connected to a first data line. A second terminal of the analog switch is electrically connected to an input terminal of the first inverter, an output terminal of the second inverter, and an input terminal of the clocked inverter. An output terminal of the first inverter is electrically connected to an input terminal of the second inverter. An output terminal of the clocked inverter is electrically connected to a second data line. Each of the analog switch and the clocked inverter is electrically connected to at least one word line. The word line electrically connected to the analog switch is different from the word line electrically connected to the clocked inverter.
    Type: Grant
    Filed: November 20, 2006
    Date of Patent: November 3, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Syusuke Iwata, Yoshiyuki Kurokawa
  • Patent number: 7598544
    Abstract: Hybrid carbon nanotube FET (CNFET), static ram (SRAM) and method of making same. A static ram memory cell has two cross-coupled semiconductor-type field effect transistors (FETs) and two nanotube FETs (NTFETs), each having a channel region made of at least one semiconductive nanotube, a first NTFET connected to the drain or source of the first semiconductor-type FET and the second NTFET connected to the drain or source of the second semiconductor-type FET.
    Type: Grant
    Filed: January 13, 2006
    Date of Patent: October 6, 2009
    Assignee: Nanotero, Inc.
    Inventors: Claude L. Bertin, Mitchell Meinhold, Steven L. Konsek, Thomas Rueckes, Frank Guo
  • Publication number: 20090168509
    Abstract: Methods and apparatus to provide ultra low voltage, low leakage, high density, and/or variation tolerant memory bit cells are described. In one embodiment, each of the cross-coupled invertors of a memory cell may include a plurality of p-channel transistors. Other embodiments are also described.
    Type: Application
    Filed: December 31, 2007
    Publication date: July 2, 2009
    Inventors: Sapumal Wijeratne, Matthew W. Ernest, Brian A. Kuns
  • Patent number: 7542333
    Abstract: A memory cell stores information in the form of a first logic level and a second logic level that are complementary to each other. The memory cell includes a first storage circuit and a second storage circuit for storing the first logic level and the second logic level. The first and second storage circuits each have a respective input and output. An isolation circuit provides electrical isolation of the input of the first storage device from the output of the second storage device, except during access to the first and second storage circuits.
    Type: Grant
    Filed: August 23, 2007
    Date of Patent: June 2, 2009
    Assignee: STMicroelectronics SA
    Inventors: Gilles Gasiot, François Jacquet, Philippe Roche
  • Patent number: 7539931
    Abstract: In a preferred embodiment, the invention provides a method for reducing soft errors in logic. After obtaining two delayed clock signals, the delayed clock signals, the clock signal, and an output from a logic circuit are applied to a triple redundant memory element. The delay of the first delayed clock signal is equal to or greater than the pulse width of a soft error event occurring in the logic circuit. The delay of the second delayed clock signal is equal to or greater than half the pulse width of a soft error event occurring in the logic circuit.
    Type: Grant
    Filed: April 8, 2005
    Date of Patent: May 26, 2009
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Larry J. Thayer
  • Publication number: 20090116282
    Abstract: Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.
    Type: Application
    Filed: January 5, 2009
    Publication date: May 7, 2009
    Inventors: Kenichi OSADA, Masataka Minami, Shuji Ikeda, Koichiro Ishibashi
  • Publication number: 20090004803
    Abstract: One aspect of the inventors' concept relates to a method of forming a semiconductor device. In this method, a gate structure is formed over a semiconductor body. A source/drain mask is patterned over the semiconductor body implanted source and drain regions are formed that are associated with the gate structure. After forming the implanted source and drain regions, a multi-stage implant is performed on the source and drain regions that comprises at least two implants where the dose and energy of the first implant varies from the dose and energy of the second implant. Other methods and devices are also disclosed.
    Type: Application
    Filed: June 27, 2007
    Publication date: January 1, 2009
    Inventors: Manoj Mehrotra, Stan Ashburn, Shaoping Tang
  • Publication number: 20080304314
    Abstract: A method of operating a semiconductor device, a semiconductor device and a digital micromirror system are presented. In an embodiment, the semiconductor device comprises a grounded substrate, a memory array, and a reset driver. The memory array may be isolated from the grounded substrate with a buried layer. The set of voltages of the memory array may be shifted with respect to a reset voltage. The reset driver may drive the reset voltage and the reset driver may have at least one extended drain transistor in the grounded substrate.
    Type: Application
    Filed: June 6, 2007
    Publication date: December 11, 2008
    Inventors: James D. Huffman, James Norman Hall
  • Patent number: 7451384
    Abstract: A system and method for providing error recovery to an asynchronous logic circuit is presented. The asynchronous logic circuit with error recovery may use temporal redundancy to compare the results of an asynchronous computation and initiate error recovery if necessary. Outputs of the asynchronous logic circuit are compared using a plurality of asynchronous register voters. If an asynchronous register voter detects an inconsistent result, the asynchronous register voter clears itself. A majority of common data outputs from the plurality of asynchronous register voters is provided as an output that is representative of the output of the asynchronous logic circuit.
    Type: Grant
    Filed: July 15, 2004
    Date of Patent: November 11, 2008
    Assignee: Honeywell International Inc.
    Inventors: David O. Erstad, Roy M. Carlson
  • Publication number: 20080273382
    Abstract: A pseudo 6T SRAM cell design comprising eight transistors is provided. An embodiment comprises a pair of cross-coupled inverters and a pair of pass-gate transistors electrically coupled to each inverter through the substrate. Each pass-gate transistor has a different beta ratio from the other transistor in its pair, and the smaller beta ratio in the pair acts as a “read” port while the larger beta ratio in the pair acts as a “write” port. Two pairs of bit lines are connected to the pass-gate transistors. A variety of word lines are connected to the pass-gate transistors. In one embodiment, a single word line is connected to all of the pass-gate transistors. In another embodiment, a pair of word lines is connected to the pass-gate transistors. In yet another embodiment, a different word line is connected to each pass-gate transistor.
    Type: Application
    Filed: October 2, 2007
    Publication date: November 6, 2008
    Inventor: Ping-Wei Wang
  • Publication number: 20080259681
    Abstract: Various systems and methods for implementing memory devices are disclosed. For example, some embodiments of the present invention provide sub-threshold memory devices that include a differential bit cell. Such a differential bit cell includes two PMOS transistors, two NMOS transistors, and two inverters. The source of the first PMOS transistor and the source of the second PMOS transistor are electrically coupled to a bit line input, and the source of the first NMOS transistor and the source of the second NMOS transistor are electrically coupled to the bit line input. The gate of the first NMOS transistor and the gate of the second NMOS transistor are electrically coupled to a word line input. The gate of the first PMOS transistor and the gate of the second PMOS transistor are electrically coupled to an inverted version of the word line input.
    Type: Application
    Filed: April 17, 2007
    Publication date: October 23, 2008
    Inventors: Charles M. Branch, Steven C. Bartling
  • Publication number: 20080253180
    Abstract: The memory cell comprises first and second inverter circuits, connected in a loop. First and second decoupling transistors, normally turned off outside the write phases, are respectively connected between an output of the second inverter circuit and first and second inputs of the first inverter circuit. The memory cell is thereby protected against transient disturbances due to ionizing particles. The gates of the decoupling transistors are preferably respectively connected to a supply voltage for the P-type decoupling transistors and grounded for the N-type decoupling transistors.
    Type: Application
    Filed: July 5, 2006
    Publication date: October 16, 2008
    Inventors: Michel Nicolaidis, Renaud Perez
  • Publication number: 20080144365
    Abstract: In this invention, high manufacturing yield is realized and variations in threshold voltage of each MOS transistor in a CMOS•SRAM is compensated. Body bias voltages are applied to wells for MOS transistors of each SRAM memory cell in any active mode of an information holding operation, a write operation and a read operation of an SRAM. The threshold voltages of PMOS and NMOS transistors of the SRAM are first measured. Control information is respectively programmed into control memories according to the results of determination. The levels of the body bias voltages are adjusted based on the programs so that variations in the threshold voltages of the MOS transistors of the CMOS•SRAM are controlled to a predetermined error span. A body bias voltage corresponding to a reverse body bias or an extremely shallow forward body bias is applied to a substrate for the MOS transistors with an operating voltage applied to the source of each MOS transistor.
    Type: Application
    Filed: November 20, 2007
    Publication date: June 19, 2008
    Inventors: Masanao YAMAOKA, Kenichi OSADA, Shigenobu KOMATSU
  • Patent number: 7382667
    Abstract: An active termination circuit is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage through at least one PMOS transistor and to ground through at least one NMOS transistor. The impedances of the transistors are controlled by a control circuit that generates a first control signal to set the impedance of another PMOS transistor to be equal to a first predetermined resistance, and generates a second control signal to set the impedance of another NMOS transistor to be equal to a second predetermined resistance. The first control signal is used to control all of the PMOS transistors and the second control signal is used to control all of the NMOS transistors. As a result, the PMOS and NMOS transistors coupled to each input terminal have impedances corresponding to the first and second resistances, respectively.
    Type: Grant
    Filed: January 10, 2006
    Date of Patent: June 3, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Chris G. Martin
  • Publication number: 20080117667
    Abstract: A memory includes a first bipolar transistor, a first bit line, and a first resistive memory element coupled between a collector of the first bipolar transistor and the first bit line. The memory includes a second bit line, a second resistive memory element coupled between an emitter of the first bipolar transistor and the second bit line, and a word line coupled to a base of the first bipolar transistor.
    Type: Application
    Filed: November 21, 2006
    Publication date: May 22, 2008
    Inventors: Thomas Nirschl, Thomas Happ, Klaus Aufinger
  • Publication number: 20080094889
    Abstract: The present invention provides an integrated circuit capable of reducing a leak current and reliably holding data therein in a standby mode. A potential higher than a potential of a second source line is supplied to a first source line. A potential lower than a potential of a first ground line is supplied to a second ground line. A virtual source line and a virtual ground line are respectively connected to the second source line and the first ground line by switches in an operation mode and float thereby in the standby mode. Substrates of MOS transistors are respectively connected to the second source line and the first ground line by switches in the operation mode and connected to the first source line and the second ground line thereby in the standby mode. A gate circuit transmits an output signal of a data non-holding circuit to a data holding circuit in the operation mode and fixes an input signal of the data holding circuit in the standby mode.
    Type: Application
    Filed: July 24, 2007
    Publication date: April 24, 2008
    Applicant: OKI ELECTRIC INDUSTRY CO., LTD.
    Inventor: Satoru KUROTSU
  • Patent number: 7359229
    Abstract: There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory device and technique of reading data from and writing data into memory cells of the memory device. In this regard, in one embodiment of this aspect of the invention, the memory device and technique for operating that device that minimizes, reduces and/or eliminates the debilitating affects of the charge pumping phenomenon. This embodiment of the present invention employs control signals that minimize, reduce and/or eliminate transitions of the amplitudes and/or polarities. In another embodiment, the present invention is a semiconductor memory device including a memory array comprising a plurality of semiconductor dynamic random access memory cells arranged in a matrix of rows and columns.
    Type: Grant
    Filed: March 2, 2007
    Date of Patent: April 15, 2008
    Assignee: Innovative Silicon S.A.
    Inventors: Richard Ferrant, Serguei Okhonin, Eric Carman, Michel Bron
  • Publication number: 20080062756
    Abstract: The invention proposes a SRAM memory cell comprising two inverters and, a plurality of switches, the SRAM cell being manufactured in a technology offering N/P shunt capabilities, the inputs of the inverters being connected to at least one pair of bit lines (BLa, BLa/; BLb, BLb/) via two of said switches, said switches being controlled by a signal word line (WLa, WLb), each inverter comprising a first transistor (MN0, MN1) of a first conductivity type and a second transistor (MP0, MP1) of a second conductivity type, and each switch comprising at least a third transistor (MN2, MN3) of the first conductivity type, characterized in that the two transistors (MP0, MP1) of the second conductivity type in the inverters are arranged in two opposite end regions of the memory cell, respectively.
    Type: Application
    Filed: March 25, 2005
    Publication date: March 13, 2008
    Inventors: Cedric Mayor, Denis Dufourt
  • Patent number: RE41638
    Abstract: A semiconductor memory having a memory cell structure capable of reducing soft error without complicating a circuit configuration. Specifically, an inverter (I1) consists of a NMOS transistor (N1) and a PMOS transistor (P1), and an inverter (I2) consists of a NMOS transistor (N2) and a PMOS transistor (P2). The inverters (I1, I2) are subjected to cross section. The NMOS transistor (N1) is formed within a P well region (PW0), and the NMOS transistor (N2) is formed within a P well region (PW1). The P well regions (PW0, PW1) are oppositely disposed with an N well region (NW) interposed therebetween.
    Type: Grant
    Filed: November 3, 2005
    Date of Patent: September 7, 2010
    Assignee: Renesas Technology Corp.
    Inventor: Koji Nii
  • Patent number: RE44242
    Abstract: A semiconductor memory having a memory cell structure capable of reducing soft error without complicating a circuit configuration. Specifically, an inverter (I1) consists of a NMOS transistor (N1) and a PMOS transistor (P1), and an inverter (I2) consists of a NMOS transistor (N2) and a PMOS transistor (P2). The inverters (I1, I2) are subjected to cross section. The NMOS transistor (N1) is formed within a P well region (PW0), and the NMOS transistor (N2) is formed within a P well region (PW1). The P well regions (PW0, PW1) are oppositely disposed with an N well region (NW) interposed therebetween.
    Type: Grant
    Filed: July 29, 2010
    Date of Patent: May 28, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Koji Nii