Abstract: An output circuit is incorporated in an integrated circuit for communicating with an external device, and includes a plurality of output inverting circuits. Each such inverting circuit is implemented by a series combination of a p-channel enhancement type field effect transistor and an n-channel enhancement type field effect transistor. The inverting circuits are coupled between a positive power voltage line and a ground voltage line electrically connected with a semiconductor substrate. The output circuit also includes a plurality of output pins, each coupled between an external load and one of the output inverting circuits, and a resistive element coupled between the ground voltage line and the semiconductor substrate, so that the ground voltage line hardly fluctuates in voltage level upon concurrent switching actions of the output inverting circuits.

Abstract: A read only memory includes a memory cell provided at an intersection between a word line and a bit line, and a plurality of reference potential transmission lines each receiving a reference potential determined in accordance with an externally applied potential designating signal. The memory cell includes a transistor element having a gate coupled to a word line, a drain coupled to a bit line and a source which is coupled to one of the reference potential transmission lines or is held in an open state. Stored data in the memory cell is changed by switching the potentials of the reference potential transmission lines. This enables storing of different data bits in one memory cell.

Abstract: A memory circuit which includes a memory SCR and an output SCR is provided. The memory SCR is coupled between the input terminal and the common terminal of the memory circuit wherein the input terminal is the control terminal of the output SCR and the output SCR is coupled across the output terminal and the common terminal of the memory circuit. When the memory SCR latches, it functions to subsequently latch the output SCR. Because the output SCR has a greater forward operating voltage than the memory SCR and by providing a current path from the output terminal to the memory SCR, the memory SCR remains latched during the transition period of when the output SCR goes from a latched state to an unlatched state.

Abstract: A memory arrangement that includes a static memory cell with two MOSFETs that are connected such that an input signal for setting the memory cell is applied to one MOSFET, and the output of the other MOSFET is connected to the input of the first MOSFET, so that one MOSFET is always conductive while the other is blocked. The two MOSFETs are connected with positive feedback. In each case, the gate electrode is connected to a voltage equal to half the battery voltage. The source electrode of the first (N channel) MOSFET forms the input of the memory cell. The drain electrode of the first MOSFET is connected to the source electrode of the second (P channel) MOSFET. The blocking resistance of the drain-substrate diode of the first MOSFET is greater than the blocking resistance of the source-substrate diode of the second MOSFET. Also, the output voltage of the first (N channel) MOSFET is greater than the sum of the gate voltage and the threshold voltage of the second (P channel) MOSFET.

Abstract: A semiconductor integrated circuit includes a first P-channel MOS transistor and a second P-channel MOS transistor. The drain of the first P-channel MOS transistor is connected to the gate of the second P-channel MOS transistor. The second P-channel MOS transistor has a threshold voltage (a gate potential with respect to a source potential) greater than that of the first P-channel MOS transistor.

Abstract: In order to obtain a highly stable SRAM cell having a small cell area, a cell ratio R is set to be R=(W.sub.DEFF /L.sub.DEFF)/(W.sub.TEFF /L.sub.TEFF)<3 where L.sub.DEFF and W.sub.DEFF denote an effective channel length and an effective channel width of two driver MOSFETs 3 and 4 respectively, and L.sub.TEFF and W.sub.TEFF denote an effective channel length and an effective channel width of two transfer MOSFETs 5 and 6 respectively. Further, a maximum current I.sub.R flowing into the active loads MOSFETs 1 and 2 is set to be greater than a current I.sub.L (1.times.10.sup.-8 A) that flows into the driver MOSFET 5 when a threshold voltage is applied across the gate and the cource of the MOSFET 5. The pair of active load MOSFETs 1 and 2 are stacked on the driver MOSFETs 3 and 4 and on the transfer MOSFETs 5 and 6.

Abstract: In a metal-oxide semiconductor (MOS) dynamic formed on a semiconductor substrate, data nodes of a first flip-flop are connected to a first pair of folded bit lines. Its power supply node is connected through a switch to a first power supply (Vss). Data nodes of a second flip-flop are connected to a second pair of folded bit lines. Its power supply node is connected through a switch to the first power supply (Vss). A power supply node of a third flip-flop is connected through a switch to a second power supply (Vcc). Data nodes of the third flip-flop are coupled through a first pair of transfer gates to the first pair of the folded bit lines, and through a second pair of transfer gates to the second pair of the folded bit lines. Coupling the first to the third flip-flops forms a first sense amplifier and coupling the second to the third flip-flops forms a second sense amplifier.

Abstract: A semiconductor memory circuit comprises a plurality of memory cells and a plurality of programming transistors, each memory cell being provided at the intersections of one bit line and one word line. The memory cell includes an insulator and a cell transistor, and a conductivity type of the cell transistor selected by a word line select signal is opposite to that of the programming transistor selected by a bit line select signal. The memory cell is programmed by utilizing an electrical breakdown of the insulator, when the bit line select signal and the word line select signal supplied are in-phase and both the programming transistor and the cell transistor are switched. Therefore, the memory cell is programmed in a short time during which the programming transistor and the cell transistor are switched, and thus this semiconductor memory circuit can be programmed with a low consumption of power and of a high speed.

Abstract: A complementary semiconductor memory device comprises a memory cell array (73, 100) in which each cell (MC.sub.p ; MC.sub.po) has a first MIS transistor (Q.sub.p); Q.sub.p1, Q.sub.p2) of a first conduction type connected to a word line, a decoding circuit (71) for decoding an input address signal and generating a selecting signal, and a driving circuit (72; 90) having a second MIS transistor (W.sub.80) of a second conduction type opposite to the first conduction type for driving the word line, thereby improving the operation speed thereof, while decreasing the possibility of the destruction of information in each cell by .alpha.-rays. A word drive signal having a negative potential may be used, and the threshold voltage of the second MIS transistor is selected to be greater than an absolute valve of the threshold voltage of the first MIS transistor.

Abstract: A CMOS-RAM memory is composed of at least one main memory area SF whose memory cells are realized with a seven transistor basic cell (SC) in a gate array arrangement. The memory cells are thereby arranged in a matrix in the main memory area. A word line decoder (WD) lies at one side of the main memory area (SF) of the gate array arrangement in row direction, this word line decoder (WD) containing - per row of memory cells-a decoder sub-circuit (WDT) realized with basic cells for generating a word line signal from address signals. A drive circuit (AST) is arranged between the word line decoder (WD) and the main memory area (SF), the drive circuit (AST) providing - per row of memory cells - a drive sub-circuit (ASTT) for generating a write signal in inverted and non-inverted form from the word line signal and from a selection signal with which the memory cells of a row of memory cells are driven.

Abstract: An Electrically Programmable Read Only Memory (EPROM) memory cell includes a serially connected Complementary Metal Oxide Silicon (CMOS) transistor pair having common floating gates and common control gates. A third n-type floating gate field effect transistor is utilized for programming the memory cell. The floating gate and the control gate of the third transistor are connected to the common floating gates and the common control gates, respectively, of the Complementary Metal Oxide Silicon (CMOS) transistor pair. The memory cell is tri-statable by connecting the source of the p-channel transistor of the Complementary Metal Oxide Silicon (CMOS) pair to the common control gates.

Abstract: A semiconductor memory device in which a data line and a holding circuit for storing data thereon are connected through a transmission gate comprised of an N-type MOS transistor and a P-type MOS transistor, wherein the semiconductor memory device comprises an initial potential setting circuit for setting an initial potiential on the data line prior to readout operation of data from the holding circuit; and a control circuit operative to allow the both transistors of the transmission gate to be turned on at the time of writing data into the holding circuit, and to allow one of the transistors to be turned on at the time of reading data from the holding circuit. Where a hold potential changes when data in the holding circuit has been read out onto the data line, such a change in the hold potential increases on resistance of one of the transistors which has been turned on of the transmission gate.

Abstract: There is described a low voltage sense amplifier for an EPROM memory transistor which has a low voltage inverter coupled to the memory transistor. The inverter receives a selectable low reference voltage as its power supply and the same reference voltage is fed as a precharge voltage, prior to reading an EPROM bit, to the input of the inverter.

Abstract: A p-channel MOS transistor is connected in series to a floating gate n-channel MOS transistor forming a memory cell, so that the p-channel MOS transistor functions as the load of the memory cell. The operational characteristic of the p-channel MOS transistor determines the data-writing current of the memory cell. Hence, hardly any change occurs in the data-writing current, even if the operation characteristic of the memory cell changes. A semiconductor memory includes memory cells constituted by floating gate n-channel MOS transistors. The memory further includes a data-reading, column-selecting circuit comprising n-channel MOS transistors, and a data-writing, column-selecting circuit comprising p-channel MOS transistors. By way of the above structure, the data-writing voltage can be prevented from being lowered.

Abstract: The logic has an extremely high speed, very low number of components and large common mode rejection, and is intended to eliminate the emitter-coupled logic (ECL). The supply voltage and power consumption are small. The logic is particularly for digital systems requiring extremely fast and complex digital processing, such as supercomputers. One basic gate is responsive to and providing differential binary signals, and comprises a pair of transistors of opposite conductivity types, each having a base, emitter and collector, wherein the bases are separately coupled to gate inputs, the emitters are coupled together, and the collectors are separately coupled to gate outputs and further to a power supply via biasing resistors. Based on the basic gate is a memory cell which includes a positive feedback resistor and can be read and written via a single terminal.

Abstract: In an output buffer circuit for a memory including complementarily-connected P-channel and N-channel MOS transistors, a voltage is induced across the lead inductance whenever the load capacitance is charged or discharged through the lead inductance during the switching operation of the buffer circuit. This induced voltage changes the ground level or the supply voltage level, and results in a problem such that data signals read from the memory are distorted. To overcome this problem, one of the two MOS transistors through which an electric charge is charged or discharged is divided into two MOS transistors of a small size, and the data signal is applied to one of the divided MOS transistors directly and to the other thereof through a delay element so that the peak of the induced voltage is lowered without increasing the access time of the memory.

Abstract: For reduction in occupation area, there is provided a complementary field effect transistor consisting of a n-channel MIS type field effect transistor formed along a side wall of a p-type silicon substrate and a p-channel MIS type field effect transistor formed along a side wall of an n-type well in the p-type silicon substrate, and both of the side wall of the silicon substrate and the side wall of the n-type well define a groove where a conductive material is deposited to provide an interconnection between the n-type and p-type MIS type field effect transistors and another complementary field effect transistor.

Abstract: A semiconductor memory device of the invention has a plurality of floating gate memory cells. A detector detects the data stored in a floating gate memory cell selected by a decoder and produces a corresponding detection signal. A load circuit amplifies the detection signal. The amplified detection signal is supplied to a differential amplifier. The differential amplifier compares the voltage of the amplified detection signal with a reference voltage from a reference voltage generator and produces a binary signal corresponding to the storage contents in the floating gate memory. The load circuit is a p-channel enhancement-type MOS transistor. The load transistor has a gate and drain which are connected to the node between the detector and the differential amplifier, and also has a source and substrate which receive a predetermined voltage.

Abstract: A memory circuit implemented in a CMOS gate array employs both P-channel and N-channel transistors as memory devices. The use of P-channel memory devices is made possible by providing a level-shifting circuit and a voltage reference circuit to compensate for manufacturing process variations and fluctuations in power supply levels. The reference circuit is made up of a series connection of P-channel FETS that are the same as the memory transistors. The reference voltage produced by the reference circuit tracks variations in the power supply and reflects changes in manufacturing processes so that they are compensated in the output of the level shifting circuit. Performance is further enhanced by clocking load FETS that connect the memory transistors to the voltage source, and density is increased by providing two word lines per row of memory transistors.

Abstract: A programmable memory cell useful in a logic cell array draws no D.C. power in either a "1" or a "0" state. The cell includes a CMOS transistor pair including a p-channel transistor connected to a positive voltage source and an n-channel transistor connected to a circuit ground potential. The cell output is connected to a common terminal of the CMOS transistor pair. The CMOS transistor pair has a common floating gate which is selectively charged for programming the cell. In a preferred embodiment, the floating gate comprises a first polycrystalline silicon layer (polysilicon), and capacitive means including a second polysilicon layer spaced from and capacitively coupled with the first polysilicon layer is utilized to selectively applying charge to the common floating gate.

Abstract: An electrical data storage element which provides for alteration of this stored data by way of a data line and address lines. Data is held as a charge set on a charge storage device. The state of the switch elements is sensed by way of the data line and address line.

Abstract: A compact, nonvolatile, zero static power, electrically alterable, bistable CMOS latch device is fabricated with single layer of polysilicon. The single polysilicon layer forms the floating gates of the nonvolatile elements of the device. The control gates are formed in the substrate by buried N+ diffusions and are separated from their respective floating gates by a thin oxide dielectric. The circuit can be designed to power-up in a preferred mode even before any programming operation has been performed on it. Thereafter, the circuit is available to be programmed to either of its two stable states. After the programming operation is completed and the circuit is latched to one of its two stable states, the fields across the thin oxide dielectrics are minimal and virtually no read disturb condition exist. Thus, the latch also offers excellent data retention characteristics.

Abstract: A CMOS data cell having increased immunity to single event upsets is disclosed. The cell includes a first CMOS inverter and a second CMOS inverter which have their respective storage nodes interconnected by cross-coupling connections. The respective storage nodes of the cell are connected through word line or write clock transfer gates to bit lines or data bus lines which serve to both write in and read out the data state of the cell. The soft error resistant data cell further includes six transistors which provide the hardening features to the data storage cell design. Two data state control transistors (one for each storage node) have their drain electrodes connected to a data storage node and their source electrodes connected to the power supply rail. Each of the data state control transistors is gated by the word line voltage via a transfer device or pass transistor that is in turn, gated by the complementary storage node on the opposite side of the cell.

Abstract: A CMOS dual port RAM cell is disclosed wherein one of the word lines is parallel to one of the bit lines in the cell. One bit line is accessed through a p-channel transistor while the other bit lines are accessed through n-channel transistors. This configuration permits the cell to use a single well, thus permitting higher density.

Abstract: A content addressable memory cell includes two storage field effect transistors of opposite conductivity type with their gates connected in common. A single write transistor is connected between the common gates and a bitline for storing a potential on the gates from the bitline.

Abstract: The data cell invention disclosed herein is a CMOS latch having a first CMOS inverter and a second CMOS inverter which have their respective storage nodes interconnected by cross-coupling connections which each include a gated polysilicon resistor. The respective storage nodes of the cell are connected through word line transfer gates to bit lines which serve to both write in and read out the state of the cell. The control gate of the word line transistors is also connected to the control gates of the respective gated polysilicon resistors in the cross-coupled connections for the cell. In normal operation, when the word line transfer gates are not conductive, the gated polysilicon resistors are also not conductive.

Abstract: It is contemplated to realize a semiconductor memory with a large memory capacity, high in integration and low in power dissipation. A semiconductor memory is disclosed, comprising a plurality of blocks each having a memory cell array and sense amplifier(s) to differentially amplify signals read out from the array, wherein a common driving line of amplifiers composed of N-channel MOS transistors among said sense amplifiers and a common driving line of amplifiers composed of P-channel MOS transistors among the sense amplifers are connected between different blocks.

Abstract: A gate array arrangement provides cell zones in the form of a matrix in a core zone of a chip. Each cell zone contains a fundamental circuit which consists of six or seven transistors designed in CMOS technology and which can perform a logic function or a storage function on the basis of appropriate interconnections. The connection of the fundamental circuits to one another is carried out either by way of the fundamental circuits or by using fundamental circuits which are not used to construct memories or logic functions. On the basis of the fundamental circuits consisting of six or seven n-channel and p-channel transistors it is possible to construct one storage cell per fundamental circuit and therefore to provide memories which can be adapted to the prevailing requirements in a gate array arrangement.

Abstract: In an output buffer circuit for a memory including complementarily-connected P-channel and N-channel MOS transistors, a voltage is induced across the lead inductance whenever the load capacitance is charged or discharged through the lead inductance during the switching operation of the buffer circuit. This induced voltage changes the ground level or the supply voltage level, and results in a problem such that data signals read from the memory are distorted. To overcome this problem, one of the two MOS transistors through which an electric charge is charged or discharged is divided into two MOS transistors of a small size, and the data signal is applied to one of the divided MOS transistor directly and to the other thereof through a delay element so that the peak of the induced voltage is lowered without increasing the access time of the memory.

Abstract: A read only semiconductor memory device which comprises a plurality of transistor pairs comprising two transistors of one and the other conductivity types arranged in a matrix manner, thus allowing only one of the two transistors constituting each transistor pair to be operated to obtain a predetermined logical output. By employing a structure of the transmission gate type as the transistor pair, high speed and reliable operation for raising a potential on the output line can be realized.

Abstract: A MOS sense amplifier having a differential input and a single-ended output, and formed of only six MOS transistors. The amplifier's non-inverting input is connected to the gates of first and second MOSFETs. The drains of the first and second MOSFETs are connected to each other and to the gates of third and fourth MOSFETs. The drain of the third MOSFET is connected to the sources of the second and sixth MOSFETs; and the source of the third MOSFET is connected to the positive supply voltage. The drain of the fourth MOSFET is connected to the sources of the first and fifth MOSFETs. The source of the fourth MOSFET is connected to ground. The inverting input of the sense amplifier is connected to the gates of the fifth and sixth MOSFETs. The drains of the fifth and sixth MOSFETs are connected to each other and provide the output terminus of the amplifier. The first, fourth and fifth MOSFETs are n-channel devices, while the second, third and sixth MOSFETs are p-channel devices.

Abstract: An integrated circuit for a dynamic semiconductor random access memory, constructed of complementary transistors, has memory cells connected to bit lines by way of individual selection transistors of a first channel type, the operation of which is controlled by word lines. The voltage on the word lines is controlled by a first switching transistor of a second channel type, controlled by the output of a decoder. The first switching transistor is connected between the word line and a selection voltage which alternates between two voltage values of different operational signs, and the gate of the first switching transistor is connected through a capacitor to the selection voltage and through a second switching transistor having its gate at reference potential, to the output of the decoder.

Abstract: A programmable read only memory having an improved writing circuit is disclosed. The writing circuit includes a first field effect transistor of a conductivity type opposite to the conductivity type of a second field effect transistor constituting a memory cell. A programming current is supplied via the first transistor to the second transistor. The first transistor represents its load characteristic having a constant current region. A programming power consumption is thereby reduced.

Abstract: An electrically programmable memory cell contains a source-drain series arrangement of a field-effect select transistor arrangement and a complementary pair of memory transistors arranged between a first bit line and a second bit line. The pair of memory transistors comprises a common electrically floating storage gate and a common control gate which is connected to one programming line. Each of the electrodes of the select transistors is connected to the row selecting line associated therewith. The drain regions which are connected to one another, are lead to a read line. The memory cell according to the invention permits reading without requiring any significant DC power, and programming by using the complete programming voltage as available.

Abstract: A system for preventing forward biasing of the bit line junctions formed between the N-well and bit lines of a CMOS memory. The system includes a gating system for maintaining the bit line voltage at V.sub.CC /2 whenever the well voltage is less than V.sub.CC. A well regulator and well pump maintain the well voltage at a selected multiple of V.sub.CC.

Abstract: A semiconductor memory device includes: a memory cell constituted by MOSFETs; a bit line for transmitting a writing and a reading information to or from the memory cell therethrough; a writing-in control signal line for controlling the writing operation onto the memory cell; a first conductive type MOSFET with a source thereof being connected to a power supply terminal, with a gate thereof being connected to the writing-in control signal line, and with a drain thereof being connected to the bit line; the first conductive type MOSFET being adapted to charge up the bit line when no writing is performed in the memory cell; a second conductive type MOSFET with first control line thereof being connected to the bit line, with a gate thereof being connected to the writing-in control signal line, and with a second control line thereof being connected to the output terminal of the writing circuit; and the second conductive type MOSFET being adapted to transmit to the bit line an output from the writing circuit.

Abstract: A current limiting, process compensating circuit for CMOS memory arrays is provided. A dual transistor bias circuit is connected to each of a pair of columns of the array with a four transistor voltage reference circuit having its output connected to the gates of the active P-channel transistor of each bias circuit. A first P-channel transistor of the voltage reference circuit is sized to be less than the P-channel transistor of the bias circuit and the other three N-channel transistors are sized to be the same as the second transistor of the bias circuit and the two transistors of each memory cell in the array. As supply voltage to the array moves up or down making more or less current available, the combined circuit maintains nearly constant current on the first transistor of each bias circuit while compensating for process variation.

Abstract: A static bipolar random access memory cell includes first and second transistors formed in epitaxial silicon pockets 41 and 42 in a substrate. The collectors 19 and 19' and bases 15 and 15' of the transistors are interconnected with polycrystalline silicon 21 doped to match the conductivity types of the regions contacted. Undesired PN junctions 40 and 40' created thereby are shorted using an overlying layer of a metal silicide 25. In a region overlying the N conductivity type polycrystalline silicon 23 or 23', the metal silicide is removed and a PH junction 37 or 37' created by depositing P conductivity type polycrystalline silicon 35c or 35c'. If desired additional P type polycrystalline silicon 35a and 35b may be deposited across the surface of the epitaxial layer where the base regions of the two transistors are formed to reduce the base series resistance.

Abstract: A random access memory cell of complementary field effect transistors that include a bit storage latch for storing binary bit information connected to a word address line and a data address line. The data address line provides bit information to the latch. This bit data is stored in the latch when the word address line is active. A switching circuit is connected to the latch that enables new data to be stored in the latch by removing the previously stored data during the time that the new data is being stored.

Abstract: A memory is described comprising static MTL memory cells for high operation speeds. The cell or primary injectors and the bit line injectors are coupled to each other by an angular injection coupling via the low-resistivity base region of the cell flip-flop transistors. This results in a signal path with reduced series resistance and thus higher signals and a faster read operation obtainable. The density is additionally increased by using in common the primary injectors and the bit line injectors of adjacent cells of the array.

Abstract: A logic circuit comprises a first and second circuit. The first circuit consists of at least one first conductivity-type MOSFET having a gate connected to an input terminal, and having a first current path connected at one end to an output terminal. The second circuit consists of at least one second conductivity-type MOSFET having a gate is connected to the input terminal, and having a second current path connected at one end to the output terminal. The logical circuit further comprises a depletion-type MOSFET of the second conductivity type and a depletion-type MOSFET of the first conductivity type. The depletion-type MOSFET of the second conductivity type has a threshold voltage the absolute value of which is larger than that of the first conductivity-type MOSFET, has a current path connected between the other end of the first current path and a first power source, and has a gate connected to the output terminal.

Abstract: An output driver circuit for fast memories and microprocessors and the li The driver circuit is responsive to a binary input voltage and includes first and second signal control paths respectively coupled to a pair of series connected output stage transistors coupled between two high and low reference voltages and switched alternately between conducting and non-conducting states in mutual opposition to provide a binary output voltage substantially equal to either of the two reference voltages depending upon the binary state of the input voltage. Additionally included is an anticipatory circuit having means responsive to both an externally applied precharge signal and a feedback signal corresponding to the binary state of the output voltage which alternately predrive the transistors close to their respective conducting switching points for increasing the speed of transition of the transistors between conductive and non-conductive states.

Abstract: A static bipolar random access memory employs a novel layout for high packing density. Each cell uses a cross-coupled pair of NPN vertical transistors as drivers merged with a pair of PNP lateral transistors as loads, Schottky diode coupling to the input/output lines and Schottky diode clamping of the internal nodes. The PNP transistors are also partially merged between cells to conserve space. OXIL technology is used to achieve high gain vertical transistors and to provide dielectric isolation.

Abstract: An I.sup.2 L type semiconductor device having an elementary region which is isolated by V-shape grooves from the other portions of the device, said semiconductor device comprising an insulating layer coating covering the surface of the semiconductor body of the device, wherein an injector region is formed under said insulating layer and surrounded by thicker portions of said insulating layer, and base regions are formed under said insulating layer between said thicker portions of said insulating layer and said V-shape grooves.

Abstract: A memory cell formed of two serially connected MOS transistors one of which has a floating gate is connected to a series combination of a Y address MOS transistor, a readout selection MOS transistor and an MOS transistor disposed in an output buffer circuit across two DC sources. A writing selection MOS transistor is connected across the series combination of the last-mentioned two transistors. The Y address MOS transistor, the readout selection MOS transistor, the output buffer MOS transistor and the writing selection MOS transistor are all operated in the triode region with V.sub.G -V.sub.TH >V.sub.D and at least one of these MOS transistors has a channel conductivity type different from the channel conductivity type of the memory cell MOS transistors.

Abstract: Disclosed herein is a semiconductor memory device comprising a semiconductor substrate having a first conductivity type, first and second regions of a second conductivity type opposite to said first type formed in the surface of the semiconductor substrate and separated with a certain space therebetween, a third region of the first conductivity type formed in the second region, and a gate electrode formed on an insulating film on the semiconductor substrate between the first and the third regions. By applying a gate voltage to the gate electrode, charge carriers are transferred between the first and second regions in accordance with the data to be stored. The stored data is read out by applying a prescribed gate voltage to the gate electrode and by detecting the value of the current between the third region and the semiconductor substrate.

Abstract: A memory circuit comprising a memory cell for storing information, constituted of semiconductor circuit elements and the associated circuit elements, and a control input section provided on the input side of the memory cell for controlling the memory cell, constituted of transistor means and current control means, wherein one of ON and OFF states is selected and also held in accordance with more than two logic input signals supplied to the control input section and no power is consumed to hold the OFF state.

Abstract: A circuit having a first drive transistor for clamping the circuit output to a first point of operating potential in response to a first data input signal representing one binary value and a second drive transistor for clamping the circuit output to a second point of operating potential in response to a second data input signal representing the other binary value includes means for momentarily turning on the first and second drive transistors and presetting the output of the circuit to a voltage level intermediate the first and second points of operating potential in anticipation of the application of a data signal. The circuit may also include a first signal path, for applying the data and control signals to the first transistor, which propagates the first signals faster than the second signals and a second signal path, for applying the data and control signals to the second transistor, which propagates the second signals faster than the first signals.

Abstract: A CMOS semiconductor memory device in which a memory cell array and peripheral circuits are formed on the same semiconductor substrate. Wells of the peripheral circuits with MOS transistors of one channel type formed therein are supplied with a PN junction reverse bias potential higher than that for wells of the memory cell array during the memory operation, while the potential at the peripheral circuit wells is made equal to the potential at the wells of the memory cell array when the memory is not operating. High-speed operation of the memory device may be achieved because the junction capacitance of the MOS transistors formed in the peripheral circuit wells is reduced when the memory is operating.

Abstract: An electrically reprogrammable non-volatile memory device is disclosed which includes complementary MOS transistors provided with a polycrystalline silicon floating gate electrode in a common n.sup.- -type substrate. The device comprises three main parts. The first part, which is used for writing, comprises a p-channel writing transistor, a p-channel control transistor and a resistance element. The second part, which comprises a second gate electrode capacitance coupled with the floating gate, is used for erasing. The third part is used for performing information read-out and consists of a p-channel transistor the gate of which forms a portion of the floating gate and the drain of which is connected to a read-out terminal and to the terminal of a loading element having its other terminal connected to a negative supply potential.