Variable Threshold Patents (Class 365/184)
  • Patent number: 10284233
    Abstract: A device includes a memory, an error correction code (ECC) decoder, and an ECC input adjuster. The ECC decoder is configured to perform a first decode operation to decode a first portion of a representation of data read from the memory based on one or more decode parameters and to perform a second decode operation to decode a second portion of the representation of data based on one or more adjusted decode parameters. The ECC input adjuster is configured to adjust one or more decode parameters to set the one or more adjusted decode parameters based on a count of bits of the first portion that are erroneous.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: May 7, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Alexander Bazarsky, Eran Sharon, Ariel Navon
  • Patent number: 10170201
    Abstract: A data storage device includes a memory device including memory regions classified into a plurality of memory groups each corresponding to a plurality read bias voltage groups; and a controller suitable for: performing for a target memory region a read retry operation based on a first read bias voltage group corresponding to a memory group in which the target memory region is included, and performing an additional read retry operation based on at least one of remaining read bias voltage groups excluding the first read bias voltage group among the plurality of read bias voltage groups, according to a result of the read retry operation.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: January 1, 2019
    Assignee: SK Hynix Inc.
    Inventor: Sang Gon Kim
  • Patent number: 10158380
    Abstract: A device includes a memory and a controller coupled to the memory. The controller is configured to determine a first count of bits of a representation of data that are estimated to be erroneous and a second count of bits of the representation of data that have high estimated reliability and are estimated to be erroneous. The controller is further configured to modify at least one read parameter or at least one decode parameter based on the first count and the second count.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: December 18, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Eran Sharon, Alexander Bazarsky, Idan Goldenberg, Stella Achtenberg, Omer Fainzilber, Ran Zamir
  • Patent number: 10152372
    Abstract: A method for operating a data storage device includes reading a plurality of data chunks from a plurality of pages corresponding to target memory cells coupled to a target word line based on read biases; obtaining discrimination data corresponding to the target memory cells based on discrimination biases; determining an unreliable bit in a target data chunk among the plurality of data chunks based on the plurality of data chunks and the discrimination data; and determining whether the unreliable bit is an error bit.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: December 11, 2018
    Assignee: SK Hynix Inc.
    Inventor: Hyung Min Lee
  • Patent number: 10083069
    Abstract: A data storage device includes a non-volatile memory and a controller. The non-volatile memory includes a word line coupled to a plurality of storage elements. A method includes detecting a condition associated with a defect in the word line. A first subset of the plurality of storage elements and a second subset of the plurality of storage elements are determined based on an estimated location of the defect. The method further includes determining a first read threshold for the first subset and a second read threshold for the second subset.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: September 25, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Seungjune Jeon, Idan Alrod, Eran Sharon, Dana Lee
  • Patent number: 10055326
    Abstract: In an embodiment, a method for monitoring the state of health of an electronic data carrier involves using a reader device to determine the state of health of the electronic data carrier by reading a parameter value indicative of a state of health from the electronic data carrier. In an embodiment, a system for monitoring a state of health of an electronic data carrier comprising a reader device operable to read data from the electronic data carrier. The reader device is arranged to determine the state of health of the electronic data carrier by reading a parameter value indicative of the state of health from the electronic data carrier.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: August 21, 2018
    Assignee: NXP B.V.
    Inventors: Klaas Brink, Manvi Agarwal, Ghiath Al-kadi
  • Patent number: 10025505
    Abstract: A method includes sending data access requests to storage units regarding a set of encoded data slices. The method further includes, when a write transaction is pending for the set of encoded data slices, receiving proposal records from the storage units. The method further includes interpreting the proposal records to determine an ordering of visible versions of the set of encoded data slices stored by the storage units. The method further includes determining whether a threshold number of encoded data slices of a desired version of the set of encoded data slices is visible. The method further includes, when the threshold number of encoded data slices is visible, determining whether to proceed with the data access request. The method further includes, when determined to proceed with the data access request, sending a request to proceed with the data access request to the storage units.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: July 17, 2018
    Assignee: International Business Machines Corporation
    Inventors: Andrew D. Baptist, Greg R. Dhuse, Ravi V. Khadiwala, Ilya Volvovski
  • Patent number: 9977736
    Abstract: A method for managing memory operations in a storage device having a plurality of data blocks, the method including steps for determining a number of page reads for each of the plurality of data blocks and determining a dwell time for each of the plurality of data blocks. In certain aspects, the method further includes steps for associating the plurality of data blocks with a plurality of rank groups based on the number of page reads and the dwell time associated with each of the plurality of data blocks and selecting a data block, from among the plurality of data blocks, for memory reclamation based on the associated rank group and the selected data block. A storage system and computer-readable media are also provided.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: May 22, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventor: Ashot Melik-Martirosian
  • Patent number: 9934847
    Abstract: According to one embodiment, a memory system acquires HB information and SB1 information through SB4 information on each of four pages including LOWER, MIDDLE, UPPER, and HIGHER pages from a NAND memory 100 that includes QLCs each being capable of retaining a 4-bit value. An ECC circuit 260 of a memory controller 200 decodes the acquired HB information and SB1 to SB4 information on the four pages.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: April 3, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kenji Sakurada, Masanobu Shirakawa
  • Patent number: 9928136
    Abstract: A codeword is generated from a message. One or more anchor values are appended to the codeword at predetermined anchor positions. Before the codeword is stored in a memory block, the locations and values of stuck cells in the memory block are determined. Based on the values and positions of the stuck cells, the values of the codeword are remapped so that values of the codeword that are the same as the values of the stuck cells are placed at the positions of the stuck cells. The remapped codeword is stored in the memory block. When the message is later read, the original codeword can be recovered from the remapped codeword based on the locations of the anchor values in the remapped codeword.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: March 27, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: John D. Davis, Parikshit Gopalan, Mark Manasse, Karin Strauss, Sergey Yekhanin
  • Patent number: 9711525
    Abstract: Disclosed are a semiconductor device and a manufacturing method thereof. The semiconductor device includes: source select lines, word lines, drain select lines, and a bit line stacked on a substrate in which a first cell string region and a second cell string region are defined; channel layers and memory layers vertically passing through the source select lines, the word lines, and the drain select lines in each of the first cell string region and the second cell string region; and a common source line vertically passing through the source select lines, the word lines, and the drain select lines at centers of the first cell string region and the second cell string region, and extended to a lower side of the source select lines.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: July 18, 2017
    Assignee: SK hynix Inc.
    Inventor: Min Sik Jang
  • Patent number: 9620219
    Abstract: A method of operating a nonvolatile memory device includes: first programming a target transistor of a cell string of the nonvolatile memory device, wherein the target transistor has a first threshold voltage distribution after the first programming, and wherein the cell string includes a plurality of transistors; and second programming the target transistor of the cell string, wherein the first transistor has a second threshold voltage distribution after the second programming, wherein a width of the second threshold voltage distribution is less than a width of the first threshold voltage distribution.
    Type: Grant
    Filed: January 18, 2016
    Date of Patent: April 11, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Wandong Kim
  • Patent number: 9607707
    Abstract: Techniques are disclosed for accurately sensing memory cells without having to wait for a voltage that creeps up on word line after a sensing operation to die down. The word line creep up could cause electrons to trap in shallow interface traps of a memory cell, hence impacting its threshold voltage. In one aspect, trapped electrons are removed (e.g., de-trapped) from shallow interface traps of a memory cell using a weak erase operation. Therefore, problems associated with word line voltage creep up are reduced or prevented. Thus, the memory cell can be sensed without waiting, while still providing an accurate result. The weak erase could be part of a sensing operation, but that is not required. For example, the weak erase could be incorporated into the beginning part of a read operation, which provides for a very efficient solution.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: March 28, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Liang Pang, Yingda Dong, Xuehong Yu, Jingjian Ren
  • Patent number: 9520445
    Abstract: Various embodiments describe an integrated non-volatile component. The component may include a surface contact with associated mating contact wherein a ferroelectric layer is used as a conductive channel having variable conductivity and the surface contact and/or the associated mating contact are/is embodied as a rectifying contact and, as a result of an applied voltage between the surface contact and the associated mating contact, a non-volatile space charge zone forms in the surface contact terminal region and/or mating contact terminal region in the ferroelectric layer.
    Type: Grant
    Filed: July 12, 2012
    Date of Patent: December 13, 2016
    Assignee: HELMHOLTZ-ZENTRUM DRESDEN-ROSSENDORF E. V.
    Inventors: Heidemarie Schmidt, Yao Shuai, Shengqiang Zhou, Ilona Skorupa, Xin Ou, Nan Du, Christian Mayr, Wenbo Luo
  • Patent number: 9520406
    Abstract: A method of making a vertical NAND device includes forming a lower portion of a memory stack over a substrate, forming a lower portion of memory openings in the lower portion of the memory stack, and at least partially filling the lower portion of the memory openings with a sacrificial material. The method also includes forming an upper portion of the memory stack over the lower portion of the memory stack and over the sacrificial material, forming an upper portion of the memory openings in the upper portion of the memory stack to expose the sacrificial material in the lower portion of the memory openings, removing the sacrificial material to connect the lower portion of the memory openings with a respective upper portion of the memory openings to form continuous memory openings, and forming a semiconductor channel in each continuous memory opening.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: December 13, 2016
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Raghuveer S. Makala, Yao-Sheng Lee, Jayavel Pachamuthu, Johann Alsmeier, Henry Chien
  • Patent number: 9501113
    Abstract: There is a need to solve a possible system malfunction when a power supply voltage decreases steeply. To solve this problem, a control method is provided for a voltage detection system having an interrupt mode and a reset mode. First and second detection levels are configured. When a power supply voltage is higher than the first detection level, a latch circuit is placed in a first state to enable the interrupt mode. When the power supply voltage becomes lower than or equal to the first detection level, an interrupt signal is generated to change the latch circuit from the first state to a second state and enable the reset mode. A system reset is issued when the power supply voltage becomes lower than or equal to the second detection level in the reset mode.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: November 22, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kyouhei Kouno, Shinichi Nakatsu, Kazuyo Yamaguchi, Kimiharu Eto, Kuniyasu Ishihara, Hirotaka Shimoda, Yuusuke Urakawa, Seiya Indo
  • Patent number: 9490321
    Abstract: A semiconductor device includes a substrate supporting a plurality of layers that include at least one modulation doped quantum well (QW) structure offset from a quantum dot in quantum well (QD-in-QW) structure. The modulation doped QW structure includes a charge sheet spaced from at least one QW by a spacer layer. The QD-in-QW structure has QDs embedded in one or more QWs. The QD-in-QW structure can include at least one template/emission substructure pair separated by a barrier layer, the template substructure having smaller size QDs than the emission substructure. A plurality of QD-in-QW structures can be provided to support the processing (emission, absorption, amplification) of electromagnetic radiation of different characteristic wavelengths (such as optical wavelengths in range from 1300 nm to 1550 nm).
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: November 8, 2016
    Assignees: THE UNIVERSITY OF CONNECTICUT, Opel Solar, Inc.
    Inventor: Geoff W. Taylor
  • Patent number: 9449682
    Abstract: Adaptive write operations for non-volatile memories select programming parameters according to monitored programming performance of individual memory cells. In one embodiment of the invention, programming voltage for a memory cell increases by an amount that depends on the time required to reach a predetermined voltage and then a jump in the programming voltage is added to the programming voltage required to reach the next predetermined voltage. The adaptive programming method is applied to the gate voltage of memory cells; alternatively, it can be applied to the drain voltage of memory cells along a common word line. A circuit combines the function of a program switch and drain voltage regulator, allowing independent control of drain voltage of selected memory cells for parallel and adaptive programming. Verify and adaptive read operations use variable word line voltages to provide optimal biasing of memory and reference cells during sensing.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: September 20, 2016
    Inventor: Sau Ching Wong
  • Patent number: 9412463
    Abstract: Read disturb due to hot electron injection is reduced in a 3D memory device by controlling the magnitude and timing of word line and select gate ramp down voltages at the end of a sensing operation. In an example read operation, a predefined subset of word lines includes source-side and drain-side word lines. For the predefined subset of word lines, word line voltages are ramped down before the voltages of the select gates are ramped down. Subsequently, for a remaining subset of word lines, word line voltages are ramped down, but no later than the ramping down of the voltages of the select gates. The timing of the ramp down of the selected word line depends on whether it is among the predefined subset or the remaining subset. The predefined subset can include a number of adjacent or non-adjacent word lines.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: August 9, 2016
    Assignee: SanDisk Technologies LLC
    Inventors: Hong-Yan Chen, Yingda Dong
  • Patent number: 9396799
    Abstract: A semiconductor memory device and a method of operating the same are provided. The device may include a memory cell array including a plurality of memory blocks and a peripheral circuit configured for selecting one of the plurality of memory blocks and performing a program operation on selected memory cells of the selected memory block when the program operation is performed. The peripheral circuit may be configured to float a plurality of source select lines and a plurality of drain select lines of an unselected memory block of the plurality of memory blocks when the program operation is performed.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: July 19, 2016
    Assignee: Sk hynix Inc.
    Inventor: Keon Soo Shim
  • Patent number: 9389061
    Abstract: A magnetostrictive position sensor achieves an improved signal to noise ratio by implementing several electronic control features, including: enclosing a waveguide within an approximately tubular return conductor, adjusting the energy of an interrogation pulse and then clamping the waveguide, tracking the peak voltage of a sensed signal, cutting off the signal of a pickup during the time period outside of a signal time frame, adjusting the pass band of a filter based on an interrogation rate and waveguide length, zeroing and scaling a signal without digitizing the signal, and avoiding noise from an interrogation voltage generator.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: July 12, 2016
    Inventor: David Scott Nyce
  • Patent number: 9367391
    Abstract: Memory devices configured to determine if an error exists in read data and to respond to determined errors, as well as methods of operating such memory devices. In at least one embodiment, an internal controller of a memory device periodically performs internal error correction operations on stored user data and corrects user data in the memory device independently from instructions from an external memory access device. In further memory devices, an internal controller performs internal error correction operations on stored user data and adjusts trim values that define voltages to be utilized during a read operation in response to determining that the read user data comprises an error.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: June 14, 2016
    Assignee: Micron Technology, Inc.
    Inventor: William Lam
  • Patent number: 9218874
    Abstract: When writing a multi-state non-volatile memory, a de-trapping operation is included in the programming cycle. To reduce the performance penalty of including a de-trapping operation, the programming cycle of a single series of increasing pulses alternating with verify operations is replaced with a cycle including a pulse from each of two or more staircases, where each staircase is for a corresponding subset of the data states. After the multiple pulses, but before the following verify, a de-trapping operation is inserted in the programming cycle.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: December 22, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Yee Lih Koh, Tien-chien Kuo, Man Mui, Juan Lee
  • Patent number: 9208892
    Abstract: An operation method of a multi-level memory is provided. A first read voltage lower than a standard read voltage is applied to a doped region in a substrate at one side of a control gate of the memory, so as to determine whether a first storage position and a second storage position are both at the lowest level.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: December 8, 2015
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Guan-Wei Wu, Yao-Wen Chang, I-Chen Yang, Tao-Cheng Lu
  • Patent number: 9030868
    Abstract: A nonvolatile memory device includes bit and source lines alternately arranged parallel to each other and even strings and odd strings alternately arranged between the bit lines and the source lines and each including drain selection transistors, memory transistors, and a source selection transistor. The drain selection transistors include a first drain selection transistor with the same structure as the memory transistors and a second drain selection transistor with the same structure as the source selection transistor. The nonvolatile memory device further includes an even drain selection line connected to the first drain selection transistors of the even strings and the second drain selection transistors of the odd strings and an odd drain selection line connected to the second drain selection transistors of the even strings and the first drain selection transistors of the odd strings.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: May 12, 2015
    Assignee: SK Hynix Inc.
    Inventor: Nam-Jae Lee
  • Patent number: 9025373
    Abstract: According to one embodiment, a non-volatile programmable switch according to this embodiment includes first and second non-volatile memory transistors, and a common node that is connected to the output side terminals of the first and second non-volatile memory transistors, and a logic transistor unit that is connected to the common node. A length of a gate electrode of the first and second non-volatile memory transistors in a channel longitudinal direction is shorter than a length of the charge storage film in the channel longitudinal direction.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: May 5, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kosuke Tatsumura, Koichiro Zaitsu, Mari Matsumoto, Shinichi Yasuda
  • Patent number: 9019760
    Abstract: A memory device is provided, including a back gate including a first portion of electrically conductive material, a first portion of dielectric material arranged on the back gate, a semiconductor nanobeam arranged on the first portion of dielectric material, a second portion of dielectric material covering the semiconductor nanobeam, a portion of material configured to receive electrons and holes, and configured to store electrical charges and covering the second portion of dielectric material, a third portion of dielectric material covering the portion of material configured to perform storage of electrical charges, and a front gate including a second portion of electrically conductive material covering the third portion of dielectric material.
    Type: Grant
    Filed: November 25, 2011
    Date of Patent: April 28, 2015
    Assignee: Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Alexandre Hubert, Maryline Bawedin, Sorin Cristoloveanu, Thomas Ernst
  • Patent number: 9007823
    Abstract: A semiconductor device according to an embodiment includes: a first transistor including a gate connected to a first interconnection, a first source, and a first drain, one of the first source and the first drain being connected to a second interconnection; and a second transistor including a gate structure, a second source, and a second drain, one of the second source and second drain being connected to a third interconnection and the other of the second source and second drain being connected to a fourth interconnection. The gate structure includes a gate insulation film, a gate electrode, and a threshold-modulating film provided between the gate insulation film and the gate electrode to modulate a threshold voltage, the other of the first source and first drain of the first transistor is connected to the gate electrode.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: April 14, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takahiro Kurita, Yoshifumi Nishi, Kosuke Tatsumura, Atsuhiro Kinoshita
  • Patent number: 8987701
    Abstract: In one embodiment there is set forth a method comprising providing a semiconductor structure having an electrode, wherein the providing includes providing a phase transition material region and wherein the method further includes imparting energy to the phase transition material region to induce a phase transition of the phase transition material region. By inducing a phase transition of the phase transition material region, a state of the semiconductor structure can be changed. There is further set forth an apparatus comprising a structure including an electrode and a phase transition material region, wherein the apparatus is operative for imparting energy to the phase transition material region to induce a phase transition of the phase transition material region without the phase transition of the phase transition material region being dependent on electron transport through the phase transition material region.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: March 24, 2015
    Assignee: Cornell University
    Inventors: Sandip Tiwari, Ravishankar Sundararaman, Sang Hyeon Lee, Moonkyung Kim
  • Patent number: 8982636
    Abstract: A memory comprises a memory cell, a sense amplifier, and a control unit. The memory cell stores a first bit and a second bit. The sense amplifier senses a first cell current and a second cell current corresponding to the first and the second bits respectively with a voltage applying on the memory cell. The control unit determines a digital state of the first bit by comparing a first reference current with the first cell current or by comparing a reference data with a first delta current between the first cell current and the second cell current.
    Type: Grant
    Filed: April 8, 2013
    Date of Patent: March 17, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Tsung-Yi Chou, Ming-Feng Zhou, Chung-Yi Li, Zong-Qi Zhou
  • Patent number: 8964462
    Abstract: The present invention relates to a nonvolatile memory device and to a method for manufacturing same. According to the present invention, the blocking insulation layer of a nonvolatile memory device having a typical SONOS structure is replaced with a threshold voltage switching material, which changes to a low resistance state only while a voltage greater than a threshold voltage is applied while maintaining a high resistance state under normal conditions and returning to the high resistance state when the applied voltage is removed. The present invention performs a program operation by injecting charges from a gate electrode layer into a charge trap layer through an insulation layer formed of the threshold voltage switching material after applying a voltage pulse greater than the threshold voltage to the gate electrode layer.
    Type: Grant
    Filed: August 17, 2011
    Date of Patent: February 24, 2015
    Assignee: Korea University Research and Business Foundation
    Inventors: Taegeun Kim, Homyoung An
  • Patent number: 8860459
    Abstract: According to one embodiment, a semiconductor integrated circuit includes nonvolatile memory areas, each includes a first nonvolatile memory transistor, a second nonvolatile memory transistor and an output line, the first nonvolatile memory transistor includes a first source diffusion region, a first drain diffusion region and a first control gate electrode, the second nonvolatile memory transistor includes a second source diffusion region, a second drain diffusion region and a second control gate electrode, the output line connected the first drain diffusion region and the second drain diffusion region, and logic transistor areas, each includes a logic transistor, the logic transistor includes a third source diffusion region, a third drain diffusion region and a first gate electrode.
    Type: Grant
    Filed: September 18, 2012
    Date of Patent: October 14, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichiro Zaitsu, Kosuke Tatsumura, Mari Matsumoto
  • Patent number: 8854883
    Abstract: According to one embodiment, there is provided a fusion memory including a first memory cell array formed of a NAND cell unit and a second memory cell array formed of a DRAM cell on a semiconductor substrate. The NAND cell unit is formed of a non-volatile memory cell having a two-layer gate structure in which a first gate and a second gate are stacked, and a selective transistor connecting the first and second gates of the non-volatile memory cell. The DRAM cell is formed of a cell transistor having a structure same as the structure of the selective transistor, and a MOS capacitor having a structure same as the structure of the non-volatile memory cell or the selective transistor.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: October 7, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Daisaburo Takashima
  • Publication number: 20140269078
    Abstract: A 3D memory device includes an improved dual gate memory cell. The improved dual gate memory cell has a channel body with opposing first and second side surfaces, charge storage structures on the first and second side surfaces, and a gate structure overlying the charge storage structures on both the first and second side surfaces. The channel body has a depth between the first and second side surfaces less than a threshold channel body depth, combined with the gate structure which establishes an effective channel length of the cell greater than a threshold length. The combination of the channel body depth and effective channel length are related so that the cell channel body can be fully depleted, and sub-threshold leakage current can be suppressed when the memory cell has a high threshold state under a read bias.
    Type: Application
    Filed: August 19, 2013
    Publication date: September 18, 2014
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: YI-HSUAN HSIAO, HANG-TING LUE, WEI-CHEN CHEN
  • Publication number: 20140241054
    Abstract: To provide a semiconductor device with such a new structure that the effect of variation in transistor characteristics can be reduced to achieve less variation in the output voltage of a memory cell. A memory cell includes a source follower (common drain) transistor for reading data held in a gate. A voltage applied to a transistor generating a reference current flowing through the memory cell is determined so that a gate-source voltage is approximately equal to the threshold voltage of the transistor. With such a structure, data stored in the memory cell can be read as a voltage that is less influenced by variation of transistors such as the field-effect mobility and the size.
    Type: Application
    Filed: February 26, 2014
    Publication date: August 28, 2014
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Jun Koyama
  • Publication number: 20140231820
    Abstract: A graphene memory includes a source and a drain spaced apart from each other on a conductive semiconductor substrate, a graphene layer contacting the conductive semiconductor substrate and spaced apart from and between the source and the drain, and a gate electrode on the graphene layer. A Schottky barrier is formed between the conductive semiconductor substrate and the graphene layer such that the graphene layer is used as a charge-trap layer for storing charges.
    Type: Application
    Filed: August 6, 2013
    Publication date: August 21, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-ho LEE, Hyun-jong CHUNG, Seong-jun PARK, Kyung-eun BYUN, David SEO, Hyun-jae SONG, Jin-seong HEO
  • Patent number: 8804416
    Abstract: Memory devices and methods of operating memory devices are shown. Configurations described include a memory cell string having an elongated n type body region and having select gates with p type bodies. Configurations and methods shown can provide a reliable bias to a body region for memory operations such as erasing.
    Type: Grant
    Filed: January 20, 2014
    Date of Patent: August 12, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Akira Goda
  • Patent number: 8804415
    Abstract: A method for adaptive voltage range management in non-volatile memory is described. The method includes establishing an adaptive voltage range for a memory element of an electronic memory device. The memory element includes at least two states. The adaptive voltage range comprises a lower state and an upper state. The method also includes establishing an adjustment process to implement a first adjustment of an abode characteristic of a first state and to implement a second adjustment of an abode characteristic of a second state in the adaptive voltage range in response to a trigger event, wherein the first adjustment of an abode characteristic of the first state is different from the second adjustment of an abode characteristic of the second state.
    Type: Grant
    Filed: June 19, 2012
    Date of Patent: August 12, 2014
    Assignee: Fusion-io, Inc.
    Inventors: Robert B. Wood, Jea Woong Hyun, Hairong Sun, Warner Losh, David Flynn
  • Patent number: 8773906
    Abstract: The present invention provides a memory circuit in which, while the power is not supplied, a data signal that has been held in a memory section corresponding to a volatile memory can be held in a capacitor in a memory section corresponding to a nonvolatile memory. In the nonvolatile memory section, a transistor whose channel is formed in an oxide semiconductor layer allows a signal to be held in the capacitor for a long period. Thus, the memory circuit can hold a logic state (data signal) even while the power supply is stopped. A potential applied to a gate of the transistor whose channel is formed in an oxide semiconductor layer is raised by a booster circuit provided between a wiring for carrying power supply potential and the gate of the transistor, allowing a data signal to be held even by one power supply potential without malfunction.
    Type: Grant
    Filed: January 24, 2012
    Date of Patent: July 8, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Takuro Ohmaru
  • Patent number: 8767459
    Abstract: A method for data storage includes accepting data for storage in an array of analog memory cells, which are arranged in rows associated with respective word lines. At least a first page of the data is stored in a first row of the array, and at least a second page of the data is stored in a second row of the array, having a different word line from the first row. After storing the first and second pages, a third page of the data is stored jointly in the first and second rows.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: July 1, 2014
    Assignee: Apple Inc.
    Inventors: Yoav Kasorla, Naftali Sommer, Eyal Gurgi, Micha Anholt
  • Patent number: 8750037
    Abstract: A non-volatile memory device (and method of manufacture) is disclosed and structured to enable a write operation using an ionization impact process in a first portion of the device and a read operation using a tunneling process in a second portion of the device. The non-volatile memory device (1) increases hot carrier injection efficiency, (2) decreases power consumption, and (3) enables voltage and device scaling in the non-volatile memory devices.
    Type: Grant
    Filed: June 16, 2009
    Date of Patent: June 10, 2014
    Assignee: Globalfoundries Singapore PTE. Ltd.
    Inventors: Eng Huat Toh, Chung Foong Tan, Shyue Seng Tan, Jae Gon Lee, Elgin Quek
  • Patent number: 8738836
    Abstract: A non-volatile semiconductor memory device, comprising: a non-volatile memory array, storing multi-values by setting a plurality of different threshold voltages for each memory cell, and a control circuit, controlling a write-in operation to the memory cell array. When data have been written into the memory cell, the control circuit selects an adjacent word line, uses an erasing level to perform write-in which is weaker than the data write-in, and verifies soft programming of the amount of one page, such that a narrow-banded erasing level distribution is realized in an adjacent memory cell.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: May 27, 2014
    Assignee: Powerchip Technology Corporation
    Inventor: Masaru Yano
  • Patent number: 8723878
    Abstract: A graphics memory device includes a memory array configured to store data for a display device comprising b*y rows by a*x columns of pixels, where b>a. The memory array is arranged in a*y rows by b*x columns of memory locations. Each memory location is adapted to store n-bit image data for one of the pixels of the display device. A memory location remapping circuit is adapted to map image data stored in the b*x columns of memory locations in the memory device to the a*x columns of the display device.
    Type: Grant
    Filed: March 9, 2007
    Date of Patent: May 13, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jongkon Bae, Kyuyoung Chung
  • Patent number: 8705278
    Abstract: Silicon-oxide-nitride-oxide-silicon SONOS-type devices (or BE-SONOS) fabricated in Silicon-On-Insulator (SOI) technology for nonvolatile implementations. An ultra-thin tunnel oxide can be implemented providing for very fast program/erase operations, supported by refresh operations as used in classical DRAM technology. The memory arrays are arranged in divided bit line architectures. A gate injection, DRAM cell is described with no tunnel oxide.
    Type: Grant
    Filed: November 5, 2010
    Date of Patent: April 22, 2014
    Assignee: Macronix International Co., Ltd.
    Inventor: Hang-Ting Lue
  • Patent number: 8687417
    Abstract: A first bias charge is provided to first bias region at a first level of an electronic device, the first bias region directly underlying a first transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the first transistor is based upon the first bias charge. A second bias charge is provided to second bias region at the first level of an electronic device, the second bias region directly underlying a second transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the second transistor is based upon the second bias charge.
    Type: Grant
    Filed: October 5, 2007
    Date of Patent: April 1, 2014
    Inventors: Ruigang Li, Jingrong Zhou, David Donggang Wu, Zhonghai Shi, James F. Buller, Akif Sultan, Fred Hause, Donna Michael
  • Publication number: 20140085975
    Abstract: A microcontroller system is determining to exit a power saving mode and, in response, enable a reference current source to begin providing a reference current for a memory module. The microcontroller system determines that the reference current has reached a substantial fraction of a target reference current, and, in response to determining that the reference current has reached a substantial fraction of the target reference current, enables the memory module to begin performing one or more memory operations.
    Type: Application
    Filed: March 13, 2013
    Publication date: March 27, 2014
    Applicant: Atmel Corporation
    Inventors: Olivier Husson, Thierry Gourbilleau, Bernard Coloma
  • Publication number: 20140063935
    Abstract: A semiconductor memory device, a memory system having the same, and a method of fabricating the same are provided. The semiconductor memory device includes a vertical channel layer protruding from a surface of a substrate, a tunnel insulating layer and a charge storage layer, which are surrounding the vertical channel layer, a blocking layer surrounding the charge storage layer, interlayer insulating layers stacked along the blocking layer, and conductive layers interposed between the interlayer insulating layers. The blocking layer includes a metal oxide layer.
    Type: Application
    Filed: December 14, 2012
    Publication date: March 6, 2014
    Applicant: SK HYNIX INC.
    Inventor: Sun Mi PARK
  • Publication number: 20140063936
    Abstract: A semiconductor memory device, a memory system including the same, a method of manufacturing the same and a method of operating the same are provided. The semiconductor memory device includes a pipe channel layer, vertical channel layers coupled to a top surface of the pipe channel layer, a first pipe gate substantially surrounding a bottom surface and side surfaces of the pipe channel layer, a boosting gate formed over the pipe channel layer, and first insulating layers and conductive layers alternately stacked over the boosting gate and the pipe channel layer.
    Type: Application
    Filed: December 18, 2012
    Publication date: March 6, 2014
    Applicant: SK HYNIX INC.
    Inventors: Sa Yong Shim, Kyoung Jin Park
  • Patent number: 8664712
    Abstract: The invention relates to a flash memory cell having a FET transistor with a floating gate on a semiconductor-on-insulator (SOI) substrate composed of a thin film of semiconductor material separated from a base substrate by an insulating buried oxide (BOX) layer, The transistor has in the thin film, a channel, with two control gates, a front control gate located above the floating gate and separated from it by an inter-gate dielectric, and a back control gate located within the base substrate directly under the insulating (BOX) layer and separated from the channel by only the insulating (BOX) layer. The two control gates are designed to be used in combination to perform a cell programming operation. The invention also relates to a memory array made up of a plurality of memory cells according to the first aspect of the invention, which can be in an array of rows and columns, and a method of fabricating such memory cells and memory arrays.
    Type: Grant
    Filed: November 15, 2010
    Date of Patent: March 4, 2014
    Assignee: Soitec
    Inventors: Carlos Mazure, Richard Ferrant
  • Patent number: RE47381
    Abstract: A semiconductor memory cell and arrays of memory cells are provided In at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type, the second region being formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region and having the first conductivity type; and a gate positioned betw
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: May 7, 2019
    Assignee: Zeno Semiconductor, Inc.
    Inventor: Yuniarto Widjaja