Abstract: A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column.

Abstract: A method of programming a memory cell (100), the method comprising applying a first electric potential to a first electric terminal (101) of the memory cell (100) to accelerate first charge carriers of a first type of conductivity to thereby generate second charge carriers of a second type of conductivity by impact ionisation of the accelerated first charge carriers, and applying a second electric potential to a second electric terminal (102) of the memory cell (100) to accelerate the second charge carriers to thereby inject the second charge carriers in a charge trapping structure (103) of the memory cell (100).

Abstract: A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column.

Abstract: The invention relates to a memory cell having an FET transistor with a source, a drain and a floating body between the source and the drain, and an injector that can be controlled to inject a charge into the floating body of the FET transistor. The injector includes a bipolar transistor having an emitter, a base and a collector formed by the body of the FET transistor. Specifically, in the memory cell, the emitter of the bipolar transistor is arranged so that the source of the FET transistor serves as the base for the bipolar transistor. The invention also includes a memory array comprising a plurality of memory cells according to the first aspect of the invention, and to methods of controlling such memory cells.

Abstract: A nonvolatile memory device includes an array of EEPROM configured nonvolatile memory cells each having a floating gate memory transistor for storing a digital datum and a floating gate select transistor for activating the floating gate memory transistor for reading, programming, and erasing. The nonvolatile memory device has a row decoder to transfer the operational biasing voltage levels to word lines connected to the floating gate memory transistors for reading, programming, verifying, and erasing the selected nonvolatile memory cells. The nonvolatile memory device has a select gate decoder circuit transfers select gate control biasing voltages to the select gate control lines connected to the control gate of the floating gate select transistor for reading, programming, verifying, and erasing the floating gate memory transistor of the selected nonvolatile memory cells.

Abstract: A method for forming a device is disclosed. The method includes providing a substrate prepared with a primary gate and forming a charge storage layer on the substrate over the primary gate. A secondary gate electrode layer is formed on the substrate over the charge storage layer. The charge storage and secondary gate electrode layers are patterned to form first and second secondary gates on first and second sides of the primary gate.

Abstract: A multi-functional and multi-level memory cell comprises a tunnel layer formed over a substrate. In one embodiment, the tunnel layer comprises two layers such as HfO2 and LaAlO3. A charge blocking layer is formed over the tunnel layer. In one embodiment, this layer is formed from HfSiON. A control gate is formed over the charge blocking layer. A discrete trapping layer is embedded in either the tunnel layer or the charge blocking layer, depending on the desired level of non-volatility. The closer the discrete trapping layer is formed to the substrate/insulator interface, the lower the non-volatility of the device. The discrete trapping layer is formed from nano-crystals having a uniform size and distribution.

Abstract: A semiconductor device includes a semiconductor region, a tunnel insulating film formed on the semiconductor region, a charge-storage insulating film formed on the tunnel insulating film, a block insulating film formed on the charge-storage insulating film, and a control gate electrode formed on the block insulating film, wherein the tunnel insulating film comprises a first region which is formed on a surface of the semiconductor region and contains silicon and oxygen, a second region which contains silicon and nitrogen, a third region which is formed on a back surface of the charge-storage insulating film and contains silicon and oxygen, and an insulating region which is formed at least between the first region and the second region or between the second region and the third region, and contains silicon and nitrogen and oxygen and the second region is formed between the first region and the third region.

Abstract: A nonvolatile semiconductor memory device includes an MIS transistor having nodes, a control circuit configured to apply a first set of potentials to the nodes to cause an irreversible change in transistor characteristics, to apply a second set of potentials to the nodes to cause a first current to flow through the MIS transistor in a first direction, and to apply the second set of potentials to the nodes to cause a second current to flow through the MIS transistor in a second direction opposite the first direction, and a sense circuit configured to produce a signal responsive to a difference between the first current and the second current.

Abstract: Structures, systems and methods for transistors utilizing oxide nanolaminates are provided. One transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A gate is separated from the channel region by a gate insulator. The gate insulator includes oxide insulator nanolaminate layers with charge trapping in potential wells formed by different electron affinities of the insulator nanolaminate layers.

Abstract: A disclosed temperature sensor includes a charge trap structure including a silicon oxide film formed on a substrate; an aluminum oxide film that is formed on the silicon oxide film, wherein oxygen is injected into the aluminum oxide film from an upper surface thereof; and an electrode formed on the aluminum oxide film, wherein a flat band voltage of the charge trap structure is temperature dependent.

Abstract: A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column.

Abstract: An embodiment of the invention relates to a memory comprising a strained double-heterostructure having an inner semiconductor layer which is sandwiched between two outer semiconductor layers, wherein the lattice constant of the inner semiconductor layer differs from the lattice constants of the outer semiconductor layers, the resulting lattice strain in the double-heterostructure inducing the formation of at least one quantum dot inside the inner semiconductor layer, said at least one quantum dot being capable of storing charge carriers therein, and wherein, due to the lattice strain, the at least one quantum dot has an emission barrier of 1.15 eV or higher, and provides an energy state density of at least three energy states per 1000 nm3, all said at least three energy states being located in an energy band of 50 meV or less.

Abstract: A memory device comprising: a back gate including a first portion of electrically conductive material, a first portion of dielectric material arranged on the back gate, a semiconductor nanobeam arranged on the first portion of dielectric material, a second portion of dielectric material covering the semiconductor nanobeam, a portion of material capable of receiving electrons and holes, and able to perform storage of electrical charges and covering the second portion of dielectric material, a third portion of dielectric material covering the portion of material capable of performing storage of electrical charges, a front gate including a second portion of electrically conductive material covering the third portion of dielectric material.

Abstract: The invention relates to a nonvolatile two-transistor semiconductor memory cell and an associated fabrication method, source and drain regions (2 ) for a selection transistor (AT) and a memory transistor (ST) being formed in a substrate (1). The memory transistor (ST) has a first insulation layer (3 ), a charge storage layer (4), a second insulation layer (5) and a memory transistor control layer (6), while the selection transistor (AT) has a first insulation layer (3 ?) and a selection transistor control layer (4*). By using different materials for the charge storage layer (4) and the selection transistor control layer (4*), it is possible to significantly improve the charge retention properties of the memory cell by adapting the substrate doping with electrical properties remaining the same.

Abstract: In a semiconductor layer, information is written by applying a first potential to a first electrode, applying a second potential that is lower than the first potential to all of back gate electrodes, applying a third potential that is higher than the first potential to the first to (i?1)th front gate electrodes, and applying a fourth potential that is between the second and third potentials to the ith and subsequent front gate electrodes, where “i” is a positive integer and identifies a specific location to which information is to be written.

Abstract: A high-density and high-robustness sub-threshold memory cell circuit, having two PMOS transistors P1 and P2 and five NMOS transistors N1˜N5, wherein, the each base electrode of the two PMOS transistors and NMOS transistors N3, N4, and N5 is connected with the local grid electrode respectively; the base electrode of the NMOS transistors N1 and N2, are grounded respectively; the NMOS transistor N1 form an phase inverter with the PMOS transistor P1, and the NMOS transistor N2 form another phase inverter with the PMOS transistor P2; the two phase inverters are connected with each other in a cross coupling manner via the cut-off NMOS transistor N5, the output end of the phase inverter N1 and P1 directly connected to the input end of the phase inverter N2 and P2, and the output end of the phase inverter N2 and P2 connected to the input end of the phase inverter N1 and P1 via the cut-off NMOS transistor N5; the NMOS transistor N3 is connected with the write bit line (WBL) of the phase inverter N1 and P1, and the NMO

Abstract: A system embodiment comprises a nonvolatile memory device, a memory, and a controller. The nonvolatile memory device includes a plurality of nonvolatile memory cells. Each nonvolatile memory cell is adapted to store at least two bits. The memory is adapted to store a program when the system powers up. The controller is adapted to implement the program to provide instructions used to program and erase nonvolatile memory cells. A method embodiment comprises loading a program into memory upon powering up a memory system, and implementing the program using a controller, including programming and erasing multi-bit nonvolatile memory cells.

Abstract: A nonvolatile semiconductor memory device has a first select transistor having a gate connected to a first select word line extending in a column direction, a source connected to a first sub bit line, and a drain connected to a first main bit line extending in a row direction, and a second select transistor having a gate connected to a second select word line extending in the column direction, a source connected to a second sub bit line, and a drain connected to a second main bit line extending in the row direction. The second select transistor has a lower breakdown voltage than the first select transistor.

Abstract: A nonvolatile semiconductor memory device has a first select transistor having a gate electrode connected to a first select word line, a source connected to a first sub bit line, and a drain connected to a first main bit line, and a second select transistor having a gate electrode connected to a second select word line, a source connected to a second sub bit line, and a drain connected to a second main bit line. The first sub bit lines are controlled by the first select transistor so as to be electrically isolated from each other between memory cell groups each formed by the memory cells to be erased simultaneously. On the other hand, the second sub bit lines are connected in common to the memory cells of memory cell groups to be erased separately, by the second select transistor.

Abstract: A multi-bit flash memory and a reading method thereof. Multiple reference memory cells for saving reserved data are provided to operate together with multiple data memory cells. Before the data memory cells are read, data stored in the reference memory cell is sensed based on a present reference current. Then, a value of a new reference current for reading the data memory cells is determined according to a difference between the sensed data and the reserved data.

Abstract: A write-once read-many times memory device is made up of first and second electrodes, a passive layer between the first and second electrodes, and an active layer between the first and second electrode. The memory device is programmed by providing a charged species from the passive layer into the active layer. The memory device may be programmed to have for the programmed memory device a first erase activation energy. The present method provides for the programmed memory device a second erase activation energy greater than the first erase activation energy.

Abstract: A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell consisting essentially of one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. The device includes data sense circuitry coupled to the memory cell. The data sense circuitry comprises a word line coupled to the gate region and a bit output coupled to the source region or the drain region.

Abstract: An SRAM device including a memory cell, the memory cell having two access transistors connected to a word line, and a flip-flop circuit having complementary transistors, the transistor being a field effect transistor having a standing semiconductor thin plate, a logic signal input gate and a bias voltage input gate, the gates sandwiching the semiconductor thin plate and being electrically separated from each other, a first bias voltage is applied to bias voltage input gates of the transistors of the memory cells in a row including a memory cell being accessed for reading or writing, and a second bias voltage is applied to the bias voltage input gates of the transistors of the memory cells in a row including a memory cell under memory holding operation.

Abstract: A semiconductor device includes an active region defined in a semiconductor substrate, and gate electrodes crossing over the active region. Source/drain regions are defined in the active region on two sides of the gate electrode. At least one of the source/drain regions is a field effect source/drain region generated by a fringe field of the gate. The other source/drain region is a PN-junction source/drain region having different impurity fields and different conductivity than the substrate. At least one of the source/drain regions is a field effect source/drain region. Accordingly, a short channel effect is reduced or eliminated in the device.

Abstract: Methods of operating dual-gate memory cells having asymmetric band-gap tunnel insulators using direct tunneling. The asymmetric band-gap tunnel insulators allow for low voltage direct tunneling programming and efficient erase with holes and/or electrons, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention.

Abstract: Example embodiments provide a capacitorless dynamic random access memory (DRAM), and methods of manufacturing and operating the same. The capacitorless DRAM according to example embodiments may include a semiconductor layer separated from a top surface of a substrate and that contains a source region, a drain region, and a channel region, a charge reserving layer formed on the channel region, and a gate formed on the substrate to contact the channel region and the charge reserving layer.

Abstract: Memory cells in which an erase and write operation is performed by injecting electrons from a substrate and extracting the electrons into a gate electrode constitute a semiconductor nonvolatile memory device. That is a gate extraction semiconductor nonvolatile memory device. In that device, if an erase bias is applied in a first process of an erase and write operation, memory cells in an overerase condition occur and the charge retention characteristics of such memory cells are degraded. The present invention provides a semiconductor nonvolatile memory device using means for writing all the memory cells in an erase unit before applying the erase bias, and then applying the erase bias.

Abstract: A semiconductor processing device according to the invention includes a first non-volatile memory (21) for erasing stored information on a first data length unit, a second non-volatile memory (22) for erasing stored information on a second data length unit, and a central processing unit (2), and capable of inputting/outputting encrypted data from/to an outside. The first non-volatile memory is used for storing an encryption key to be utilized for encrypting the data. The second non-volatile memory is used for storing a program to be processed by the central processing unit. The non-volatile memories to be utilized for storing the program and for storing the encryption key are separated from each other, and the data lengths of the erase units of information to be stored in the non-volatile memories are defined separately.

Abstract: A nonvolatile semiconductor memory device includes: a memory cell array region having memory cells connected in series; a control circuit region disposed below the memory cell array region; and an interconnection portion electrically connecting the control circuit region and the memory cell array region. The memory cell array region includes: a plurality of first memory cell regions having the memory cells; and a plurality of connection regions. The interconnection portion is provided in the connection regions. The first memory cell regions are provided at a first pitch in a first direction orthogonal to a lamination direction of the memory cell array region and the control circuit region. The connection regions are provided between the first memory cell regions mutually adjacent in the first direction, and at a second pitch in a second direction orthogonal to the lamination direction and the first direction.

Abstract: A semiconductor integrated circuit includes a non-volatile memory built into the semiconductor integrated circuit, the non-volatile memory electrically writing and erasing data and including a memory cell, the memory cell including: a selecting transistor controlled by a word line; an impurity diffused region formed inside a semiconductor substrate, the impurity diffused region being coupled to one of a source and a drain of the selecting transistor; a first electrode formed above the semiconductor substrate with an insulating film therebetween, the first electrode receiving a control signal and part of the first electrode having an opening; a second electrode formed above the first electrode so as to oppose the first electrode with an insulating film therebetween, the second electrode having a protrusion which opposes the impurity diffused region with a tunnel film therebetween and projects toward the semiconductor substrate through the opening of the first electrode, and storing information based on an appl

Abstract: The semiconductor device includes the nonvolatile memory cell in the main surface of a semiconductor substrate. The nonvolatile memory cell has a first insulating film over the semiconductor substrate, a conductive film, a second insulating film, the charge storage film capable of storing therein charges, a third insulating film over the charge storage film, a first gate electrode, a fourth insulating film in contact with the set of stacked films from the first insulating film to the foregoing first gate electrode, a fifth insulating film juxtaposed with the first insulating film over the foregoing semiconductor substrate, a second gate electrode formed over the fifth insulating film to be adjacent to the foregoing first gate electrode over the side surface of the fourth insulating film, and source/drain regions with the first and second gate electrodes interposed therebetween. The conductive film and the charge storage film are formed to two-dimensionally overlap.

Abstract: To provide a semiconductor device that can suppress deterioration in transistors and has a small layout area. In a nonvolatile semiconductor memory device according to the present invention, a control voltage (4 V) between a write voltage (10 V) and a reference voltage (0 V) is applied to a gate of a P-channel MOS transistor of a memory gate drive circuit corresponding to a selected memory gate line and also the reference voltage (0 V) is applied to a gate of an N-channel MOS transistor, and the write voltage is applied to the memory gate line. Since the transistors are turned on with a gate-source voltage lower than the conventional one, deterioration in the transistors can be suppressed.

Abstract: The present invention relates to a nonvolatile memory apparatus and a method of using a thin film transistor (TFT) as a nonvolatile memory by storing carriers in a body of the TFT, which operates a general TFT as a memory cell of a nonvolatile memory by manipulating the electrical characteristics of the TFT in order to integrate with other electrical components formed by TFTs, such as logic circuit or TFT-LCD pixel transistor, on the LCD panel without additional semiconductor manufacturing processes.

Abstract: A NAND based memory device uses inversion bit lines in order to eliminate the need for implanted bit lines. As a result, the cell size can be reduced, which can provide greater densities in smaller packaging. In another aspect, a method for fabricating a NAND based memory device that uses inversion bit lines is disclosed.

Abstract: Methods, devices, and systems are disclosed relating to a memory cell having a floating body. A memory cell includes a transistor comprising a drain and a source each formed in silicon and a gate positioned between the drain and the source. The memory cell may further include a bias gate recessed into the silicon and positioned between an isolation region and the transistor. In addition, the bias gate may be configured to be operably coupled to a bias voltage. The memory cell may also include a floating body within the silicon. The floating body may include a first portion adjacent the source and the drain and vertically offset from the bias gate and a second portion coupled to the first portion. Moreover, the bias gate may be formed adjacent to the second portion.

Abstract: A multi-functional and multi-level memory cell comprises a tunnel layer formed over a substrate. In one embodiment, the tunnel layer comprises two layers such as HfO2 and LaAlO3. A charge blocking layer is formed over the tunnel layer. In one embodiment, this layer is formed from HfSiON. A control gate is formed over the charge blocking layer. A discrete trapping layer is embedded in either the tunnel layer or the charge blocking layer, depending on the desired level of non-volatility. The closer the discrete trapping layer is formed to the substrate/insulator interface, the lower the non-volatility of the device. The discrete trapping layer is formed from nano-crystals having a uniform size and distribution.

Abstract: The invention relates to a method of controlling a DRAM memory cell of an FET transistor on a semiconductor-on-insulator substrate that includes a thin film of semiconductor material separated from a base substrate by an insulating layer or BOX layer, the transistor having a channel and two control gates, a front control gate being arranged on top of the channel and separated from the latter by a gate dielectric and a back control gate being arranged in the base substrate and separated from the channel by the insulating layer (BOX). In a cell programming operation, the front control gate and the back control gate are operated jointly by applying a first voltage to the front control gate and a second voltage to the back control gate, with the first voltage being lower in amplitude than the voltage needed to program the cell when no voltage is applied to the back control gate.

Abstract: A semiconductor device comprising: a first well region which is formed at a surface portion of a semiconductor substrate and to which a first voltage is applied; a gate insulating film which is formed on the first well region; a gate electrode which is formed on the gate insulating film and has a polarity different from a polarity of the first well region and to which a second voltage is applied; and an element isolating region which is formed at a surface portion of the first well region to surround a region within the first well region that is opposed to the gate insulating film, wherein a capacitance is formed between the region within the first well region surrounded by the element isolating region and the gate electrode.

Abstract: The present invention relates to a semiconductor device, and more precisely to an 1-transistor type DRAM cell implemented using bulk silicon, a DRAM device and a DRAM comprising thereof and a driving method thereof and a manufacturing method thereof. The driving method of an 1-transistor type DRAM comprises: a data hold process biasing a word line at a negative voltage level and biasing a sensing line and a bit line at a first constant voltage level; a data purging process resetting data by biasing the word line at a second constant voltage level and biasing the sensing line and the bit line at the first constant voltage level; and a data write process allowing a write current to be flowed from the bit line to a floating body by rasing the bit line to the second constant voltage level and raising the sensing line to the half second constant voltage level, while maintaining the bias of the word line at the second constant voltage level.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array includes a stacked body, a through-hole, a semiconductor pillar, and a charge storage film. The stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films. The through-hole is made in the stacked body to align in a stacking direction. The semiconductor pillar is buried in the through-hole. The charge storage film is provided between the electrode films and the semiconductor pillar. Memory cells are formed at each intersection between the electrode films and the semiconductor pillar.

Abstract: A nonvolatile semiconductor memory device includes a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; a second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory string and the first to nth electrodes of at least two other memory strings which are adjacent to the memory string in two directions are shared as first to nth conductor layers spread in two dimensions.

Abstract: The invention relates to a method for determining a set of programming conditions for a given type of charge-trapping non-volatile memory device, comprising the steps of: (a) selecting different sets of programming parameters to be applied to the corresponding number of non-volatile memory devices of said type, (b) programming said number of non-volatile memory devices by means of the sets of programming parameters, (c) determining an actual spatial charge distribution of the charge trapping layer of each of the programmed devices, (d) determining the influence of at least one of the programming parameters on the spatial charge distribution, (e) determining an optimised value for at least one of the programming parameters, (f) entering each optimized value in said sets of programming parameters and repeating steps b) to e) at least once.

Abstract: According to an aspect of the present invention, there is provided, a nonvolatile semiconductor storage device including: a substrate; a stacked portion that includes a plurality of conductor layers and a plurality of insulation layers alternately stacked on the substrate, at least one layer of the plurality of conductor layers and the plurality of insulation layers forming a marker layer; a charge accumulation film that is formed on an inner surface of a memory plug hole that is formed in the stacked portion from a top surface to a bottom surface thereof; and a semiconductor pillar that is formed inside the memory plug hole through the charge accumulation film.

Abstract: A nonvolatile semiconductor memory device comprises: a bit line; a source line; a memory string having a plurality of electrically data-rewritable memory transistors connected in series; a first select transistor provided between one end of the memory string and the bit line; a second select transistor provided between the other end of the memory string and the source line; and a control circuit configured to control a read operation. A plurality of the memory strings connected to one bit line via a plurality of the first select transistors. During reading of data from a selected one of the memory strings, the control circuit renders conductive the first select transistor connected to an unselected one of the memory strings and renders non-conductive the second select transistor connected to unselected one of the memory strings.

Abstract: In a first aspect, a first apparatus is provided. The first apparatus is a memory element that includes (1) one or more MOSFETs each including a dielectric material having a dielectric constant of about 3.9 to about 25; and (2) control logic coupled to at least one of the one or more MOSFETs. The control logic is adapted to (a) cause the memory element to operate in a first mode to store data; and (b) cause the memory element to operate in a second mode to change a threshold voltage of at least one of the one or more MOSFETs from an original threshold voltage to a changed threshold voltage such that the changed threshold voltage affects data stored by the memory element when operated in the first mode. Numerous other aspects are provided.

Abstract: Non-volatile memory devices and methods of programming the non-volatile memory devices use six threshold voltage levels. Data also may be read from the non-volatile memory devices. The non-volatile memory devices include a first non-volatile memory cell and a second non-volatile memory cell, each of which can be programmed with first through sixth threshold voltage levels that sequentially increase. Programming includes first, second and third data bit program operations. In the first and second data bit program operation, the first and second non-volatile memory cells are programmed with the first or second threshold voltage level in order to store first and second bits of data. In the third data bit program operation, the first non-volatile memory cell is programmed with the third or fourth threshold voltage level according to the first and second bits of the data in order to store a third bit of the data. Fourth and fifth data bit program operations also may be provided.

Abstract: A nonvolatile semiconductor memory device includes: a memory unit; and a control unit. The memory unit includes: a multilayer structure including electrode films and interelectrode insulating films alternately stacked; a semiconductor pillar piercing the multilayer structure; insulating films and a memory layer provided between the electrode films and the semiconductor pillar; and a wiring connected to the semiconductor pillar. In an erase operation, the control unit performs: a first operation setting the wiring at a first potential and the electrode film at a second potential lower than the first potential during a first period; and a second operation setting the wiring at a third potential and the electrode film at a fourth potential lower than the third potential during a second period after the first operation. A length of the second period is shorter than the first period, and/or a difference between the third and fourth potentials is smaller than a difference between the first and second potentials.

Abstract: An operating method of a non-volatile memory adapted for a non-volatile memory disposed on an SOI substrate including a first conductive type silicon body layer is provided. The non-volatile memory includes a gate, a charge storage structure, a second conductive type drain region, and a second conductive type source region. In operating such a non-volatile memory, voltages are applied to the gate, the second conductive type drain region, the second conductive type source region and the first conductive type silicon body layer beneath the gate, to inject electrons or holes in to the charge storage structure or evacuate the electrons from the charge storage structure by a method selected from a group consisting of channel hot carrier injection, source side injection, band-to-band tunnelling hot carrier injection and Fowler-Nordheim (F-N) tunnelling.

Abstract: A programming method applied to a memory is provided. The memory includes a number of memory cells. The method includes the following steps. A target cell of the memory cells is programmed in response to a first programming command. The target cell is programmed in response to a second programming command.