Abstract: A dynamic semiconductor memory device includes memory cells each having a one-transistor/one-capacitor. The memory cells are arranged at their respective intersections of bit lines and word lines. Bit-line precharge circuits are provided at bit line pairs, respectively, to precharge and equalize the bit line pairs. An output potential of a plate potential generator is applied to the power supply terminals of the bit-line precharge circuits. The memory cells have a plurality of capacitors. A plate electrode of the capacitors are connected in common. An insulation film is formed on the plate electrode and a wiring layer is formed on the insulation film. The wiring layer is electrically connected to the plate electrode through a via hole formed in the insulation film and connected in common to the power supply terminals of the bit-line precharge circuits through a contact hole formed in the insulation film, thereby transmitting a potential in proportion to variations in plate potential.

Abstract: A voltage dependent capacitor to provide soft error rate tolerance in an integrated circuit is disclosed. In one embodiment, a parallel n-p voltage dependent capacitor is used to protect a node from noise. In another embodiment, an nFET-in-nWell voltage dependent capacitor is used to provide a soft error rate tolerant capacitor with reduced area.

Abstract: A digital memory array includes memory cells having respective anti-fuse layers. Write signals that vary in at least one of current, voltage, and pulse length are applied to selected ones of the memory cells to disrupt the respective anti-fuse layers to differing extents, thereby programming the selected memory cells with resistances that vary in accordance with the degree of anti-fuse layer disruption. The state of a selected memory cell is read by applying a voltage across the cell and comparing the resulting read signal with two or more thresholds, thereby reading more than one bit of digital data from each memory cell.

Abstract: A semiconductor integrated circuit device includes an integrated circuit provided in a semiconductor chip and setting information memory. The setting information memory stores operation/function setting information of the integrated circuit and receives a signal generated based on power-on in reading out the operation/function setting information.

Abstract: A memory cell array, in which a voltage that can reverse polarization is applied only to a memory cell that is an object of data writing. A semiconductor storage element is formed by a ferroelectric capacitor, a selection transistor and a control transistor. The ferroelectric capacitor is structured to be provided with a ferroelectric layer between an upper electrode and a lower electrode. The selection transistor is provided with a first main electrode, a second main electrode and a control electrode. The control transistor is provided with a first main electrode, a second main electrode and a control electrode. The lower electrode of the ferroelectric capacitor is connected with the first main electrode of the selection transistor. The second main electrode of the selection transistor is connected with the control electrode of the control transistor.

Abstract: A semiconductor memory device includes a plurality of N and P channel MOS transistors. The plurality of MOS transistors are formed on an SOI (Silicon On Insulator) substrate. Each MOS transistor includes a source region, a drain region, and a body region located between the source region and the drain region. The body region of at least one N channel MOS transistor is electrically fixed. The body region of at least one P channel MOS transistor is rendered floating.

Abstract: A semiconductor memory cell device exhibiting superior cell reliability comprising a dual layer floating gate wherein the thin upper layer of the floating gate overlaps the edges of surrounding field insulating regions and has rounded edges to minimize leakage concerns. The tunnel dielectric separating the dual layer floating gate from the substrate comprises a layer of uniform thickness which is grown prior to the formation of the field insulating regions. The Fowler-Nordheim tunneling mechanism is used for programming and erasing the inventive cells in a programming process flow which comprises flash programming all cells on a word line, sensing current on a selected cell, and selectively erasing the charge on the cell by applying a higher voltage on the intersecting bit line than is applied to the word line, until the sensed current is as desired.

Abstract: In some embodiments, the invention includes an integrated circuit including a bitline and a bitline#, wordlines, and memory cells. The memory cells each corresponding to one of the wordlines and each include first and second pass transistors coupled between first and second storage nodes, respectively, and the bitline and bitline#, respectively, the corresponding wordline being coupled to gates of the first and second pass transistors. The memory cells include first and second inverters cross-coupled between the first and second storage nodes, wherein the first and second pass transistors each have a lower threshold voltage than do transistors of the first and second inverters. Wordline voltage control circuitry coupled to the wordlines selectively controls wordline signals on the wordlines.

Abstract: A reading circuit for a multibit memory cell in a memory array, the memory cell having a threshold gate voltage within a range of one of a first, second, third and fourth predetermined threshold voltages corresponding respectively to one of four states of two bits stored in the memory cell. The reading circuit includes a circuit to provide a gate voltage to the multibit memory cell during a read cycle, the gate voltage having a first level between the second and third predetermined threshold voltages during a first time interval of the read cycle and a second level between the third and fourth predetermined threshold voltages during a second time interval of the read cycle.

Abstract: A semicomductive memory device has a memory cell connected to a word line and a digit line. The memory cell is for memorizing data of two bits in correspondence to first through fourth threshold voltages. The first threshold voltage is lower than the second threshold voltage which is lower than the third threshold voltage. The third threshold voltage is lower than the fourth threshold voltage. The semicomductive memory device has a supplying section for selectively supplying first through third read-out voltages with the word line. The first read-out voltage has a value between the first and the second threshold voltages. The second read-out voltage has a value between the second and the third threshold voltages. The third read-out voltage has a value between the third and the second threshold voltages. The supplying section supplies the second read-out voltage to the word line at first.

Abstract: A dynamic random access memory solves long-existing tight pitch layout problems using a multiple-dimensional bit line structure. Improvement in decoder design further reduces total area of this memory. A novel memory access procedure provides the capability to make internal memory refresh completely invisible to external users. By use of such memory architecture, higher performance DRAM can be realized without degrading memory density. The requirements for system support are also simplified significantly.

Abstract: An EEPROM chip includes a unit cell array. A plurality of word lines and bit lines are formed on the unit cell array. Unit cells are arranged at the intersections of these lines. Each unit cell is formed of a NAND-type cell including a plurality of memory transistors connected in series between the bit line and the word line. A selection transistor is connected in series between the drain terminal of the NAND-type cell and the bit line. Another selection transistor is connected in series between the source terminal of the NAND-type cell and the word line. In a normal read operation, a voltage of 5 V (power supply voltage Vcc) is applied to a selection gate to turn on the selection transistor. A read reference voltage of 0 V is applied to a control gate of a selected memory transistors. An ON voltage of 5 V is applied to non-selected control gates to turn on the unit cells having the non-selected control gates.

Abstract: A semiconductor integrated circuit device has a data storage section for storing mode setting data corresponding to products of a plurality of types, redundancy data, and so on. The redundancy storage section is made up of a nonvolatile transistor for storing the mode setting data corresponding to the products, the redundancy data, etc., a latch circuit for latching data read out from the nonvolatile transistor and generating a mode signal, and a transmission gate for transmitting the data from read out from the nonvolatile transistor to the latch circuit. The semiconductor integrated circuit device also has an internal voltage generator for generating an internal voltage. This internal voltage is used as the power supply voltage of the data storage section.

Abstract: Soft errors occur during normal use of a solid-state memory such as EEPROM or Flash EEPROM. A soft error results from the programmed threshold voltage of a memory cell being drifted from its originally intended level. The error is initially not readily detected during normal read until the cumulative drift becomes so severe that it develops into a hard error. Data could be lost if enough of these hard errors swamps available error correction codes in the memory. A memory device and techniques therefor are capable of detecting these drifts and substantially maintaining the threshold voltage of each memory cell to its intended level throughout the use of the memory device, thereby resisting the development of soft errors into hard errors.

Abstract: The current paths of a plurality of floating gate type MOSFETs are series-connected to form a series circuit. The series circuit is connected at one end to receive a reference voltage, and is connected to data programming and readout circuit. In the data programming mode, electrons are discharged from the floating gate to the drain of the MOSFET or holes are injected into the drain into the floating gate. The data readout operation is effected by checking whether current flows from the other end to the one end of the series circuit or not.

Abstract: A sensing system for sensing data from a data source and driving a pair of output lines in response thereto comprises: a primary sensing device operatively coupled to the data source for sensing and storing said data therein; and a secondary sensing device operatively coupled to the primary sensing device via a pair of input lines and also operatively coupled to the pair of output lines, the secondary sensing device being responsive to a differential voltage generated across the pair of input lines in accordance with said data stored by the primary sensing device and the secondary sensing device having a differential voltage threshold range associated therewith defined by a negative threshold and a positive threshold, whereby the secondary sensing device drives the pair of output lines to a first output condition when the differential voltage across the pair of input lines is within the differential voltage threshold range, to a second output condition when the differential voltage is at least equal to the ne

Abstract: An interlaced storage method for storing data in multi-level flash memory cells so that data bits from multiple addresses are encoded and stored in a single flash memory cell, and a method for reading and decoding the stored data. In the method for storing data, the data bit values for each address are multiplied by a weight having a greater value for each successively higher address to provide weighted bit values. The weighted bit values for the same order bits from the addresses are then added together to provide results, each result being programmed as a threshold voltage vt in a flash memory cell. To read the stored data, a weight comparison is set equal to the greatest weight and compared with the vt value in a first pass. If the vt value is equal to the weight comparison value, the data bits represented by the vt value are identified.

Abstract: The circuit for sensing a memory having a plurality of threshold voltages is directed to using a technique for maintaining a characteristic curve of a voltages-matched circuit and combining a characteristic curve in which the voltage is moved by a minimum value which is one half of the reference voltage with a conventional characteristic curve, so that it is possible to reduce in half the minimum distance between the voltage distributions for thereby optimizing the above distance by controlling the power voltage irrespective of the characteristic of a device.

Abstract: A memory cell includes non-volatile and volatile storage elements and is configured to dynamically alter threshold voltages of the non-volatile storage elements to store states of the volatile storage elements. The volatile storage elements may be stacked gate PMOS transistors, one of which may include a gate structure having a poly-silicon control gate disposed over a poly-silicon floating gate. The control gate and floating gate may be separated by a coupling dielectric, which may be an ONO stack or a deposited oxide. The gate structure may be disposed over an active area of a substrate including a drain and a source of the PMOS transistor. The active area may be disposed in an n-well of the substrate. A first of the volatile storage elements may comprise an NMOS transistor which is formed in a p-well of the substrate. The p-well may further be disposed in an n-well.

Abstract: At the data programming time, data of a plurality of bits are transformed by a data transforming logic circuit into data (multi-value data) according to the combination of the bits, and the transformed data are sequentially transferred to a latch circuit connected to the bit lines of a memory array. A program pulse is generated according to the data latched in the latch circuit and is applied to a memory element of a selected state corresponding to the multi-value data. At the data reading operation, the states of the memory elements are read out by changing the read voltage to intermediate values of the individual threshold values and are transferred to and latched in a register for storing the multi-value data, so that the original data may be restored by a data inverse transforming logic circuit on the basis of the multi-value data stored in the register.

Abstract: A semiconductor memory including memory cells, word lines, bit lines, a row decoder, column decoder, a voltage-changing circuit, a sense amplifier, and an output circuit. Each memory cell stores multi-level data. The row decoder selects one of the word lines in accordance with an address signal. The voltage-changing circuit generates different voltages, which are applied to the row decoder. The different voltages are sequentially applied from the voltage-changing circuit to the word line selected by the row decoder. The column decoder selects a bit line every time the potential of the word line changes. The sense amplifier detects the data read from the memory cell onto the bit line every time the potential of the word line changes. The output circuit converts the data to code data.

Abstract: Methods and apparatus for determining the state of a memory cell having more than two possible states are disclosed. For a first embodiment, the state of a flash cell having n states, where n is a power of 2, is determined by selectively comparing the threshold voltage V.sub.t of a selected memory cell to (n-1) reference voltages. For every two states, a single comparator is provided such that the total number of comparators is equal to the number of bits stored in the memory cell.

Abstract: A floating gate diode which can be used as a sourceless memory cell, and which may be arranged into an array of memory cells is disclosed. The floating gate diode comprises: a drain region formed in a substrate; an oxide overlying and associated with the drain region; and a floating gate overlying the oxide. Upon application of a voltage to the drain, a current between the drain and substrate is induced in proportion to an amount of electrons stored on the gate. The cells may be arranged into an array which comprises a substrate having a surface; a plurality of drain regions, one of said drain regions respectively corresponding to one of the plurality of cells, formed in the substrate; an oxide region overlying the plurality of drain regions on the surface of the substrate; and a plurality of floating gates overlying the oxide and respectively associated with the plurality of drain regions.

Abstract: A nonvolatile semiconductor memory device includes a memory cell including a charge storage section for storing n-value data (n.gtoreq.3). In this device, the charge storage section has discrete first to n-th charge amount regions for storing the n-value data. If the first to n-th charge amount regions are defined as n-th, (n-1)-th, . . . , (i+1)-th, i-th charge amount regions descending order of an amount of positive or negative charge stored in the charge storage section, a charge amount difference .DELTA.Mj between a j-th charge amount region and a (j-1)-th charge amount region is set to .DELTA.Mn >.DELTA.Mn-1> . . . >.DELTA.Mi+2>.DELTA.Mi+1.

Abstract: An embodiment of the present invention describes a redundancy repair circuit fabricated in a Static Random Access Memory (SRAM) semiconductor device, with the redundancy repair circuit comprising: a plurality of thin film transistors (TFTs); a programming pad connecting to serially connected control gates of the plurality of TFTs; the plurality of TFTs having their individual source/drain terminals connecting between substitution logic and an address multiplexer.

Abstract: Methods and apparatus for determining the state of a memory cell having more than two possible states are disclosed. For a first embodiment, the state of a flash cell having n states, where n is a power of 2, is determined by selectively comparing the threshold voltage V.sub.t of a selected memory cell to (n-1) reference voltages. For every two states, a single comparator is provided such that the total number of comparators is equal to the number of bits stored in the memory cell.

Abstract: A non-volatile semiconductor device can be obtained which is capable of enhancing integration level and performing accurate control of operations. A memory cell transistor of the semiconductor device in accordance with the present invention has a gate dielectric film including a ferroelectric film between a gate electrode and a semiconductor region. A back electrode is formed at the semiconductor region in a position corresponding to the gate electrode. A channel is formed at a channel formation region of the semiconductor region by applying a voltage to the back electrode, and the ferroelectric film is polarized as desired by the difference in potential between the channel and the gate electrode. Information can thus be written into the memory cell.

Abstract: An extremely compact dynamic memory cell (200) includes a capacitor (204) or any other suitable stored charge device, and a diode (208) such as a Zener diode, a pair of parallel, reverse-connected diodes, or any other suitable voltage dropping device having substantially definite voltage drops when conducting in each direction. The capacitor and Zener diode are connected in series between a Row Select line (202) and a Column Bit line (210). These structures are suitable for fabrication by any of a variety of processes used to fabricate conventional semiconductor DRAMs. The memory cell is replicated millions of times and arrayed in rows and columns as in conventional one-transistor MOSFET DRAM memories to form a memory integrated circuit. Rows of cells are accessed by asserting the corresponding Row Select line, and columns are accessed by asserting the Column Bit line.

Abstract: A semiconductor memory includes a memory transistor having a gate connected to a word line and having a threshold level selected from a plurality of threshold levels, and a plurality of comparison transistors having gates are respectively connected to the word line, each of the comparison transistor having a threshold level selected from the reference threshold levels and the threshold levels of the comparison transistor being different from each other. The word line is driven respectively to a plurality of voltage levels, and whenever they are driven to respective values of the plurality of voltage levels, the logical level state determined based on the difference between the current flowing in the memory transistor and the current flowing in the transistor circuit is held, and multibit data stored in the memory transistor is output based on the logical level state held.

Abstract: A method and apparatus for reading a memory, such that the address decoding is started when the address bits have not yet all been received. All the information elements corresponding to the partially decoded address are extracted and, when the last address bits have been received, the information element corresponding to the complete address is selected. The maximum permissible time for extracting an information element is thus increased internally, while this period of time external to the memory remains the same for a given frequency.

Abstract: The memory cells of a read-only memory are connected in parallel between adjacent bus-bit lines. The selection of tile sub-bit lines is through a selector logic decoder. The decoder has many rows of MOSFETs connected in series. Only one of MOSFETs in a row between an adjacent bit line bus and a virtual ground bus is active and controllable by a sub-word line selection signal with other MOSFETs non-conducting and connected between two adjacent sub-bit lines. These active MOSFETs in different rows are connected in series. One of these active MOSFETs is coupled to a main bit line, and another of these active MOSFETs is coupled to a virtual ground. When the active MOSFET is open, the main bit line signal and the virtual signal appear between the corresponding memory cells between these two corresponding sub-bit lines and are sensed. With this structure, the accessed memory cell is coupled between the main bit line and the virtual ground line through a number of series MOSFETs.

Abstract: Soft errors occur during normal use of a solid-state memory such as EEPROM or Flash EEPROM. A soft error results from the programmed threshold voltage of a memory cell being drifted from its originally intended level. The error is initially not readily detected during normal read until the cumulative drift becomes so severe that it develops into a hard error. Data could be lost if enough of these hard errors swamps available error correction codes in the memory. A memory device and techniques therefor are capable of detecting these drifts and substantially maintaining the threshold voltage of each memory cell to its intended level throughout the use of the memory device, thereby resisting the development of soft errors into hard errors.

Abstract: According to the present invention, a nonvolatile semiconductor storage device for applying to each word line either one of a selected voltage and a non-selected voltage, corresponding to a selection state and a non-selection state, respectively, is provided. The selection state or the non-selection state is selected in accordance with an address signal in each operational mode.

Abstract: Each of memory cells has one MOS transistor including a drain region, a source region, a channel region and a gate electrode. An impurity-introducing area of the channel region is varied in the width direction of the channel region to store data of plural bits in the memory cell.

Abstract: An apparatus and method, the apparatus including an NMOS pass gate separating NMOS and PMOS transistors of a CMOS memory cell configured for tunneling during program and erase through the NMOS and PMOS transistors. The additional NMOS pass gate enables the CMOS memory cell to be utilized as a memory cell in a programmable logic device (PLD). The method includes steps for programming and erasing CMOS memory cells to prevent current leakage. The steps include applying specific voltages to the sources of the NMOS and PMOS transistors during program and erase, rather than leaving either source floating. Such voltages can be applied during program or erase without additional pass gates being connected to the sources of the PMOS or NMOS transistors of individual CMOS cells, or the additional pass gate provided between the drains of the PMOS and NMOS as in the described apparatus.

Abstract: Provided between a control gate electrode and a channel region of the EEPROM memory cell is a capacitor. Formed on the channel region are a first gate dielectric layer of silicon oxide, a first carrier capture layer of silicon nitride, a carrier migration layer of n.sup.31 polysilicon, a second carrier capture layer of silicon nitride, and a second gate dielectric layer of silicon oxide. The carrier capture state of the carrier capture layer is changed to generate a polarization state in the capacitor, and the generated polarization state is held as data. The gate dielectric layer is not destroyed since the movement of carriers is limited to within the capacitor, and by adjusting the carrier bound energy, low-voltage drive can be accomplished.

Abstract: A nonvolatile memory with a simple structure where recorded information can be read without destruction. A voltage is impressed between a control gate and a memory gate for writing. A ferroelectric layer is polarized in accordance with the direction of the impressed voltage. A control gate voltage to make channel is small when the ferroelectric layer is polarized with the control gate side being positive. Control gate voltage to make channel is large when the ferroelectric layer is polarized with the control gate side being negative. The reference voltage is impressed on the control gate for reading. A large drain current flows when the ferroelectric layer is polarized with a second polarization and a small drain current flows when the ferroelectric layer is polarized with a first polarization. Record information can be read by detecting the drain current. Polarization status of the ferroelectric is not destroyed in the reading operation.

Abstract: A memory cell structure with the reduced number of bit line contacts, contributing to high integration and high reliability of a DRAM is provided. Each of memory cells (M1, M2, M3, M4) of the DRAM includes a field effect transistor and a capacitor (I, II, III, IV) connected thereto. The field effect transistor constituting each of the memory cells has a combination of two gates: a transfer gate (A) of a low Vth and a sub-transfer gate (a) of a high Vth, a transfer gate (B) of a high Vth and a sub-transfer gate (b) of a low Vth, a transfer gate (C) of a high Vth and a sub-transfer gate (c) of a low Vth, and a transfer gate (D) of a low Vth and a sub-transfer gate (d) of a high Vth. The four memory cells share a bit line contact.

Abstract: A multi-level NAND architecture non-volatile memory device reads and programs memory cells, each cell storing more than one bit of data, by comparing to a constant current level while selectively adjusting the gate voltage on the cell or cells being read or programmed. A plurality of read and write reference cells are provided each programmed to correspond to one each of the multi-level programming wherein during reading of the memory cells, the read reference cells provide the constant current level and during writing to the memory cells, the write reference cells provide the same. Furthermore, during a read operation, corresponding write reference cells are coupled to read reference cells to gauge the reading time associated with reading of memory cells.

Abstract: An electrically alterable non-volatile memory having a memory cell array including a plurality of memory cells, each memory cell including a transistor having a selected one of a plurality of different threshold voltages; a reference cell array including at least one set of reference cells, each reference cell in the set being set to a different threshold voltage; selection circuitry for selecting one of the memory cells; and a comparing circuitry for comparing a memory current read out of the selected memory cell with each of reference currents read out of the reference cells, sequentially in an order of levels of the threshold voltages set for the reference cells, respectively, thereby outputting data according to such comparison.

Abstract: Multiple logic levels can be simultaneously programmed into any combination of memory cells in a column of an ETOX array by applying one of a corresponding number of programming voltages to the word lines that correspond with the cells to be programmed. In the present invention, the memory cells in the array form a punchthrough current during programming which, in turn, leads to the formation of an increased number of substrate hot electrons. By utilizing the substrate hot electrons formed from the punchthrough current in addition to the channel hot electrons, much lower control gate voltages can be utilized during programming.

Abstract: A storage cell includes a first bit line, a storage circuit, and a pass transistor. The storage circuit has a first storage node for holding a logic state indicative of a logic value. The pass transistor is coupled to the first bit line and the first storage node for establishing a conduction path therebetween. The pass transistor receives a bias voltage to switch the pass transistor into a substantially nonconducting state when the storage cell is not being accessed. The reverse bias on the first transistor substantially reduces the leakage current through the pass transistor.

Abstract: A memory cell is disclosed. The memory cell operating within a power supply range that induces the pass transistor(s) of the memory cell to be reversed biased when the memory cell is not being accessed. The memory cell includes a storage element capable of storing either a first data value or a second data value, a pass transistor, coupled to the storage element, and a power supply generator is coupled to the storage element. The power supply generator is configured to generate supply level voltages for the storage element so as to induce the pass transistor into a substantially reverse-biased state when the storage element is not being accessed, regardless of whether the storage element is storing the first data value or a second data value.

Abstract: A non-volatile semiconductor memory device includes a semiconductor substrate, a memory cell including source and drain regions formed in a surface region of the semiconductor substrate, and a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate sequentially stacked on the semiconductor substrate, the memory cell being capable of electrically rewriting data by exchanging charges between the charge storage layer and the semiconductor substrate, and a means for applying a high potential to the semiconductor substrate and an intermediate potential to the control gate in a first data erase operation, and applying a high potential to the semiconductor substrate and a low potential to the control gate in second and subsequent data erase operations, thereby removing electrons from the charge storage layer.

Abstract: Soft errors occur during normal use of a solid-state memory such as EEPROM or Flash EEPROM. A soft error results from the programmed threshold voltage of a memory cell being drifted from its originally intended level. The error is initially not readily detected during normal read until the cumulative drift becomes so severe that it develops into a hard error. Data could be lost if enough of these hard errors swamps available error correction codes in the memory. A memory device and techniques therefor are capable of detecting these drifts and substantially maintaining the threshold voltage of each memory cell to its intended level throughout the use of the memory device, thereby resisting the development of soft errors into hard errors.

Abstract: In order to improve the degree of storage data integration, side walls (32) are selectively formed on side surfaces of word lines (22) to serve as masks for changing ON-state current values of memory cells by changing widths or lengths of active regions (24) of the memory cells, thereby forming several of types of memory cells having different electrical properties. Storage data per memory cell is therefore so multivalued that the number of memory cells is reduced.

Abstract: A semiconductor memory device includes a current driving transistor composed of a bipolar transistor which is coupled to a corresponding bit line for increasing the bit line current. The collector of the current driving transistor is constituted by a well coupled to ground and the base is constituted by a common drain region of two adjacent string selecting transistors. The emitter of the current driving transistor is a separate polysilicon layer disposed from among a first interlayer insulating layer and a second interlayer insulating layer and the emitter is coupled to both the base region and the bit line through contact holes. Otherwise, the emitter of the current driving transistor is a doping region formed in the base region which serves as the common drains of two adjacent string selecting transistor.The memory device has the effect that the operation speed is increased and the integration density can be increased, so as to reduce the cost thereof.

Abstract: A nonvolatile memory circuit having a decoding scheme for reliable multiple bit hot electron programming. The nonvolatile memory circuit has a memory array in which data received at each data input can be programmed into multiple memory bits simultaneously. The address of each memory bit selected for programming is decoded by a row decoder and a column decoder. The row decoder decodes the word line of each selected memory bit and the column decoder decodes the bit line of each selected memory bit. The column decoder includes a programming column decoder and a read column decoder. The programming column decoder is enabled during a programming operation and disabled during a reading operation. The read column decoder is enabled during a reading operation and disabled during a programming operation. During a programming operation, a programming voltage is applied to the nonvolatile memory.

Abstract: It is an object of the present invention to optimize the range of threshold voltage in a flash EEPROM and to simplify the verifying operation. In memory transistors (1)-(4) and a dummy memory transistor (5), erasing operation can be performed by setting a source lines SL and a dummy source line DSL at Vpp-level and Vpp1-level, respectively and by setting word lines WL1, WL2 and a dummy word line DWL at GND level. As the erasing process proceeds, the threshold voltage in the dummy memory transistor (5) is reduced before the threshold voltages in the memory transistors (1)-(4) are reduced. Therefore, the verifying operation can be executed by only detecting the threshold voltage in the dummy memory transistor. In addition, the overerasing can be prevented by previously detecting the threshold voltage in the dummy memory transistor.

Abstract: A semiconductor memory includes memory cells, word lines, bit lines, a row decoder, column decoder, a voltage-changing circuit, a sense amplifier, and an output circuit. Each memory cell stores multi-level data. The row decoder selects one of the word lines in accordance with an address signal. The voltage-changing circuit generates different voltages, which are applied to the row decoder. The different voltages are sequentially applied from the voltage-changing circuit to the word line selected by the row decoder. The column decoder selects a bit line every time the potential of the word line changes. The sense amplifier detects the data read from the memory cell onto the bit line every time the potential of the word line changes. The output circuit converts the data to code data.