Disturbance Control Patents (Class 365/185.02)
  • Patent number: 10665300
    Abstract: Methods, and apparatus configured to perform similar methods, might include performing an access operation on a memory cell of an array of memory cells, discharging a control gate of a first field-effect transistor after performing the access operation, discharging a control gate of a second field-effect transistor connected in series between the first field-effect transistor and the memory cell after discharging the control gate of the first field-effect transistor, and discharging a control gate of the memory cell after discharging the control gate of the second field-effect transistor.
    Type: Grant
    Filed: November 12, 2018
    Date of Patent: May 26, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Jeffrey S. McNeil
  • Patent number: 10643718
    Abstract: Program disturb is a condition that includes the unintended programming of a memory cell while performing a programming process for other memory cells. Such unintended programming can cause an error in the data being stored. In some cases, program disturb can result from electrons trapped in the channel being accelerated from one side of a selected word line to another side of the selected word line and redirected into the selected word line. To prevent such program disturb, it is proposed to open the channel from one side of a selected word line to the other side of the selected word line after a sensing operation for program verify and prior to a subsequent programming voltage being applied.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: May 5, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Dengtao Zhao, Peng Zhang, Nan Lu, Deepanshu Dutta
  • Patent number: 10643700
    Abstract: According to one embodiment of the present invention, an apparatus is disclosed. The apparatus includes a memory array having a plurality of memory cells. The apparatus further includes memory access circuits coupled to the memory array and configured to perform write operations responsive to control signals. The apparatus further includes control logic coupled to the memory access circuits and configured to apply a set of write parameters based, at least in part, on a number of write operations performed by the memory access circuits and further configured to provide control signals to the memory access circuits to perform write operations on the plurality of memory cells according to the set of write parameters.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: May 5, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Shekoufeh Qawami, Rajesh Sundaram
  • Patent number: 10628302
    Abstract: A semiconductor memory device preventing inconsistent busy states between a plurality of memory chips is provided. A semiconductor memory device includes a master chip and at least one slave chip. The master chip and the slave chip include a status register capable of storing protection information. When a write-protect (WP) commend for locking the protection information of the status register is input, the protection information and lock information are programmed in a memory array. At this time, programming is controlled in a manner that a programming time in a selected memory chip is longer than a programming time in an unselected memory chip.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: April 21, 2020
    Assignee: Winbond Electronics Corp.
    Inventor: Kazuki Yamauchi
  • Patent number: 10622040
    Abstract: Provided is a semiconductor device and an operating method thereof. The operating method of the semiconductor device includes performing a soft program operation on a top dummy cell and a bottom dummy cell, among dummy cells stacked in a vertical direction, by applying a first soft program voltage to a bottom dummy word line coupled to the bottom dummy cell and a second soft program voltage greater than the first soft program voltage to a top dummy word line coupled to the top dummy cell formed above the bottom dummy cell.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: April 14, 2020
    Assignee: SK hynix Inc.
    Inventor: Hee Youl Lee
  • Patent number: 10607709
    Abstract: A flash memory system may include a cell flash memory having a plurality of threshold voltages, and a circuit for performing operations of the cell flash memory. The circuit may perform a first read operation on a first cell of the cell flash memory with a first threshold voltage among the plurality of threshold voltages, estimate a first interference state relating to the first threshold voltage, estimate a first voltage shift based on the first interference state, and perform a first shifted read operation on the first cell of the cell flash memory with a shifted first threshold voltage shifted with the first voltage shift, generate a first decoder input based on the estimated first interference state and the result of the first shifted read operation on the first cell, and decode, based on the first decoder input, a result of the first read operation on the first cell.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: March 31, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Avi Steiner
  • Patent number: 10594793
    Abstract: A distributed storage network (DSN) employs multiple storage units, each of which includes distributed storage (DS) memories for dispersed storage of encoded data slices. A requesting device transmits a read-prepare request specifying a slice name to the storage units, and instructs the storage units to attempt to retrieve, one or more data slices associated with the slice name from dispersed storage, and to temporarily store the one or more data slices in a memory, rather than transmitting them to the requesting device. The requesting device receives read-prepare responses from the storage units. The read-prepare responses include either an error indication indicating that the storage unit was unable to retrieve one or more valid data slices from dispersed storage, or names and revisions of valid data slices actually retrieved. The requesting device selects a subset of the storage units based on the read-prepare responses, and transmits a read-complete request to them.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: March 17, 2020
    Assignee: PURE STORAGE, INC.
    Inventor: Jason K. Resch
  • Patent number: 10593397
    Abstract: In a particular implementation, a method to perform a read operation on a magneto-resistive random-access memory (MRAM) bit-cell includes: providing a voltage signal across one or more storage elements of the MRAM bit-cell, determining an electrical resistance of the one or more storage elements of the MRAM bit-cell, and removing the voltage signal from the MRAM bit-cell prior to an end of an incubation delay interval.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: March 17, 2020
    Assignee: Arm Limited
    Inventors: Akhilesh Ramlaut Jaiswal, Mudit Bhargava
  • Patent number: 10580504
    Abstract: Program disturb is a condition that includes the unintended programming of a memory cell while performing a programming process for other memory cells. Such unintended programming can cause an error in the data being stored. In some cases, program disturb can result from electrons trapped in the channel being accelerated from one side of a selected word line to another side of the selected word line and redirected into the selected word line. To prevent such program disturb, it is proposed to open the channel from one side of a selected word line to the other side of the selected word line after a sensing operation for program verify and prior to a subsequent programming voltage being applied.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: March 3, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Dengtao Zhao, Peng Zhang, Nan Lu, Deepanshu Dutta
  • Patent number: 10572651
    Abstract: A key generating method includes obtaining a first error correcting code (ECC) for original data, obtaining read data from a cell array of a memory comprising the original data, generating a second ECC for the read data, obtaining a location of a cell in which an error occurs from the cell array of the memory in response to the second ECC being different from the first ECC, and generating a key for the memory based on the location of the cell in which the error occurs.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: February 25, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Chan Kim, Jungsoon Shin, Taesung Jung, Du-Sik Park, Joonah Park, Soochul Lim
  • Patent number: 10559365
    Abstract: An apparatus includes a plurality of solid-state storage elements, a plurality of control lines coupled to the plurality of solid-state storage elements, and control circuitry in communication with the plurality of control lines. The control circuitry is configured to during a first phase of a control line pre-charging stage, charge one or more unselected control lines of the plurality of control lines using a regulated charging current for a period of time based at least in part on a bias variance state associated with the plurality of control lines, and during a second phase of the control line pre-charging stage, charge the one or more unselected bit lines to an inhibit voltage level using an unregulated charging current.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: February 11, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Xiang Yang, Huai-yuan Tseng, Deepanshu Dutta
  • Patent number: 10559367
    Abstract: Apparatus and methods are disclosed, such as a method that includes precharging channel material of a string of memory cells in an unselected sub-block of a block of memory cells to a precharge voltage during a first portion of a programming operation. A programming voltage can then he applied to a selected memory cell in a selected sub-block of the block of memory cells during a second portion of the programming operation. The selected memory cell is coupled to a same access line as an unselected memory cell in the unselected sub-block. Additional methods and apparatus are disclosed.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: February 11, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Aaron Yip
  • Patent number: 10553294
    Abstract: A storage device with a charge trapping (CT) based memory may include improved data retention performance. Data retention problems, such as charge loss in CT memory may increase for a particular programmed state when a neighboring state is at erased state. Modifying the erase state with post write erase conditioning (PWEC) by pushing up deeply erased states can reduce the lateral charge movement and improve high temperature data retention. In particular, the erase state may be reprogrammed such that the erase distribution is tighter with a higher voltage.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: February 4, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Mohan Vamsi Dunga, Changyuan Chen, Biswajit Ray
  • Patent number: 10535405
    Abstract: A memory device and an operating method thereof are provided. A memory device may include a plurality of source lines coupled to a memory block. The memory device may include a plurality of strings coupled to each of the source lines. The memory device may include a row decoder configured to selectively transmit voltages to local lines corresponding to a selected source line among the source lines.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: January 14, 2020
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • Patent number: 10529432
    Abstract: A data storage device according to example embodiments of inventive concepts includes a nonvolatile memory and a memory controller. In the nonvolatile memory, one read unit is configured to store a plurality of codewords. If a fail occurs in one or more codewords stored in the nonvolatile memory, the memory controller may search a read voltage of the nonvolatile memory using a correctable codeword. The data storage device according to example embodiments may predict an optimum read voltage level without performing a valley search operation.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: January 7, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hyunkook Park
  • Patent number: 10522232
    Abstract: Apparatuses and techniques are described for reducing an injection type of program disturb in a memory device. A voltage on a selected word line is increased in a first step from an initial level such as 0 V to an intermediate, pass level such as Vpass, and in a second step from Vpass to a peak program level of Vpgm. A voltage on an adjacent unselected word line can be increased from the initial level to Vpass and then temporarily increased to an elevated level of Vpass_el during the second step increase on the selected word line. This helps reduce the magnitude of a channel gradient between the selected word line and the adjacent word line. The increase to Vpass_el may be implemented for program loops in the later part of a program operation, when Vpgm and the risk of program disturb is relatively high.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: December 31, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Hong-Yan Chen, Yingda Dong
  • Patent number: 10504587
    Abstract: Embodiments of the present disclosure provide methods, devices, modules, and systems for compensating for floating gate to floating gate (fg-fg) interference in flash memory cell read operations. Compensating for fg-fg interference effects can reduce or prevent read errors. Embodiments of the present disclosure can compensate for fg-fg interference by determining the programmed state of aggressor (or influencing) memory cells that are programmed after a target memory cell. If the aggressor memory cell is in the erased state of Level 0 or is in a programmed state of Level 2-15, the target memory cell is identified as undisturbed. If the aggressor memory cell is programmed to a Level 1 (instead of Level 0 or Levels 2-15), the target memory cell is identified as disturbed. If the target memory cell is disturbed, sensing parameters may be adjusted to compensate for the disruption.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: December 10, 2019
    Assignee: INTEL CORPORATION
    Inventors: Carmine Miccoli, Akira Goda
  • Patent number: 10490244
    Abstract: A nonvolatile memory device includes: a plurality of word lines that are stacked; a vertical channel region suitable for forming a cell string along with the word lines; and a voltage supplier suitable for supplying a plurality of biases required for a program operation on the word lines, where a negative bias is applied to neighboring word lines disposed adjacent to a selected word line at an end of a pulsing section of a program voltage which is applied to the selected word line.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: November 26, 2019
    Assignee: SK hynix Inc.
    Inventor: Jin Yong Oh
  • Patent number: 10481971
    Abstract: A data holding characteristic of a memory cell is improved in a memory system in which data is encoded and written to a memory cell. A first candidate parity generation unit generates, as a first candidate parity, a parity for detecting an error in an information section in which a predetermined value is assigned in a predetermined variable area. A second candidate parity generation unit generates, as a second candidate parity, a parity for detecting an error in the information section in which a value different from the predetermined value is assigned in the predetermined variable area. A selection unit selects a parity that satisfies a predetermined condition from among the first and second candidate parities as a selection parity. An output unit outputs a codeword constituted by the information section corresponding to the selection parity and the selection parity.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: November 19, 2019
    Assignee: Sony Corporation
    Inventors: Tatsuo Shinbashi, Kenichi Nakanishi, Yasushi Fujinami, Hiroyuki Iwaki, Ken Ishii, Hideaki Okubo
  • Patent number: 10482985
    Abstract: Apparatuses, systems, methods, and computer program products for a dynamic bias voltage are presented. A monitor circuit is configured to determine whether an erase loop count of an erase operation for data word lines of an erase block satisfies a threshold. A bias circuit is configured to adjust a voltage applied to one or more dummy word lines of an erase block in response to an erase loop count for data word lines satisfying a threshold. An erase circuit is configured to perform one or more subsequent erase loops of an erase operation for data word lines with an adjusted voltage applied to one or more dummy word lines.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: November 19, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Xiang Yang, Deepanshu Dutta, Huai-Yuan Tseng
  • Patent number: 10482968
    Abstract: A local X-decoder for a memory system includes a decoding unit configured to generate a word line signal to a memory cell of a memory array of the memory system; and an unselected erase detecting unit coupled to the decoding unit, and configured to increase an absolute voltage coupled to the word line signal from a well of the memory cell according to an unselected erase mode signal generated by an erase mode decoder of the memory system; wherein the word line signal is floating to a same level as the well of the memory cell when the memory cell is unselected in an erase mode of the memory system.
    Type: Grant
    Filed: November 22, 2018
    Date of Patent: November 19, 2019
    Assignee: Wuhan Xinxin Semiconductor Manufacturing Co., Ltd.
    Inventors: Yuan Tang, Jen-Tai Hsu
  • Patent number: 10482984
    Abstract: Apparatuses and techniques are described for optimizing a program operation in a memory device. A storage location stores programing data for each word line, such as a program voltage for a set of memory cells. The set of memory cells may be periodically evaluated to determine updated programming setting(s). In one approach, the evaluation involves repeatedly sensing the set of memory cells between a program pulse and a verify signal in a program loop. The word line voltage can be stepped down to an intermediate voltage, then ramped down at a controlled rate while repeatedly sensing the memory cells, such as to detect an upper or lower tail of a threshold voltage distribution. The position of the tail can indicate a degree of over programming and this information can be used to adjust the programming setting(s) in a subsequent program operation.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: November 19, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Xiang Yang, Huai-Yuan Tseng, Deepanshu Dutta
  • Patent number: 10482982
    Abstract: In a method for operating a semiconductor device, the method may include: sorting program states of a memory cell that stores multi-bit data into a plurality of groups; applying different bias voltages to bit lines corresponding to a selected group among the plurality of groups; applying a program voltage to a selected word line corresponding to the selected group; verifying whether each of selected memory cells corresponding to the selected word line is programmed to a respective target program state; applying an inhibition voltage to bit lines coupled to programmed memory cells; and selecting a next group to be programmed until the plurality of groups are programmed.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: November 19, 2019
    Assignee: SK hynix Inc.
    Inventor: Hee Youl Lee
  • Patent number: 10431312
    Abstract: A non-volatile memory apparatus and a refresh method thereof are provided. A control circuit determines whether threshold voltages of memory cells in a memory sectors are larger than a refresh read reference voltage and smaller than a refresh program verify reference voltage, and the control circuit determines that a memory cell needs refreshing if the threshold voltage of the memory cell is larger than the refresh read reference voltage and smaller than the refresh program verify reference voltage.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: October 1, 2019
    Assignee: Winbond Electronics Corp.
    Inventors: Im-Cheol Ha, Shang-Wen Chang
  • Patent number: 10431314
    Abstract: A non-volatile memory device includes multiple word lines, and a voltage generator. Some of the word lines correspond to a deterioration area. The voltage generator is configured to generate a program voltage provided to multiple memory cells through the word lines. Control logic implemented by the non-volatile memory device is configured to control a program operation and an erase operation on the word lines. The deterioration area includes word lines of a first group and word lines of a second group. The control logic is configured to control a program sequence so that each of the word lines of the second group is programmed after an adjacent word line of the first group is programmed, and to control a distribution so that a threshold voltage level corresponding to an erase state of each of the word lines of the first group is higher than a threshold voltage level corresponding to an erase state of each of the word lines of the second group.
    Type: Grant
    Filed: June 3, 2018
    Date of Patent: October 1, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Bum Kim, Deok-Woo Lee, Dong-Hun Kwak
  • Patent number: 10424384
    Abstract: A semiconductor memory device includes an n-type semiconductor region, first to fourth conductive layers above the n-type semiconductor region, a p-type semiconductor region, a semiconductor layer between the n-type semiconductor region and the p-type semiconductor region and extending through the conductive layers, charge storage regions between the conductive layers and the semiconductor layer, a control circuit that executes a first read sequence and a second read sequence following the first read sequence, a comparison circuit that compares the first data read in the first read sequence to the second data read in the second read sequence, and a determination circuit that selects one of the first data and the second data as a true read value. The first and second read sequences each have an off step and an off voltage applied during the first read sequence is different from an off voltage applied during the second read sequence.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: September 24, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Yusuke Higashi, Tomoya Sanuki
  • Patent number: 10418112
    Abstract: A semiconductor memory device includes a first circuit configured to process data received from and transmitted to an external controller, a second circuit configured to execute calibration on the first circuit, and a control circuit configured to control the second circuit to execute the calibration on the first circuit in response to a calibration command received from the external controller. In response to a first calibration command, the control circuit controls the second circuit to execute the calibration on the first circuit. In response to a second calibration command that is received after the first calibration command, the control circuit controls the second circuit to execute the calibration on the first circuit if a first condition is met and to not execute the calibration on the first circuit if the first condition is not met.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: September 17, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Kosuke Yanagidaira
  • Patent number: 10381094
    Abstract: A two-sided, staged programming operation is applied to a memory having first and second stacks of memory cells C1(i) and C2(i), i being the physical level of a cell. The staged programming operation includes applying a preliminary program stage S1, an intermediate program stage S2, and a final program stage S3 to memory cells in the first and second stacks. In a programming order the final program stage S3 is applied to memory cells in the first and second stacks at each level (i) for which the intermediate program stage S2 has already been applied to the memory cells in any neighboring levels (levels i+1 and i?1). The intermediate program stage S2 is applied only to memory cells for which the preliminary program stage S1 has already been applied to the cells in any neighboring levels (levels i+1 and i?1).
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: August 13, 2019
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chen-Jun Wu, Chih-Chang Hsieh, Tzu-Hsuan Hsu, Hang-Ting Lue
  • Patent number: 10366757
    Abstract: A non-volatile memory cell includes a selection transistor having an insulated selection gate embedded in a semiconducting substrate region. A semiconducting source region contacts a lower part of the insulated selection gate. A state transistor includes a floating gate having an insulated part embedded in the substrate region above an upper part of the insulated selection gate, a semiconducting drain region, and a control gate insulated from the floating gate and located partially above the floating gate. The source region, the drain region, the substrate region, and the control gate are individually polarizable.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: July 30, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Julien Delalleau
  • Patent number: 10354724
    Abstract: A memory device is provided that includes a memory controller coupled to a memory array. The memory controller is adapted to perform a closed loop training interval and perform an open loop programming interval. The closed loop training interval determines a corresponding first state successful voltage and a corresponding second state successful voltage for a first group of memory cells each including a barrier modulated switching structure. The open loop programming interval programs a second group of memory cells each including a barrier modulated switching structure to a first state and a second state using the corresponding first state successful voltage and the corresponding second state successful voltage, respectively.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: July 16, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Emmanuelle Merced-Grafals, Juan P. Saenz
  • Patent number: 10347342
    Abstract: The present disclosure relate a method of operating a semiconductor memory device including at least two memory blocks sharing one block word line. The method including applying an erase voltage to a source line commonly coupled to the memory blocks, one of which is a selected memory block and applying a first voltage to the block word line and a third voltage to a global word line of an unselected memory block of the memory blocks when the erase voltage is applied to the source line, wherein the first voltage is higher than a turn-on voltage to turn on a pass transistor coupled to the block word line, and wherein the third voltage floats a local word line included in the unselected memory block according to a level of the first voltage.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: July 9, 2019
    Assignee: SK hynix Inc.
    Inventor: Hee Youl Lee
  • Patent number: 10340023
    Abstract: A method and a system for determining bit values in a non-volatile memory having a number of cells each for storing a bit value are disclosed. The method includes the steps of: a) providing a first test sensing voltage to the cells and calculating a cell count; b) providing another test sensing voltage to the cells and calculating a difference of the cell counts between this step and previous step; c) providing still another test sensing voltage and calculating another difference of the cell counts between this step and previous step; d) processing step c) for N times; e) calculating differential amounts of cell counts and assigning an index number to each group of cells; f) choosing a voltage as an updated sensing voltage.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: July 2, 2019
    Assignee: Storart Technology Co., Ltd
    Inventors: Hsiang-En Peng, Sheng-Wei Yuan, Hou-Yun Lee
  • Patent number: 10332785
    Abstract: A semiconductor device includes a substrate including a memory cell region and a contact region, a string structure including conductive layers and first interlayer insulating layers alternately stacked over the substrate and protruded toward a lower layer from the memory cell region toward the contact region, barrier rib patterns spaced apart from one another over the conductive layers in the contact region and configured to open the layers of the conductive layers in the contact region through the spaced spaces, and first contact plugs filled into the space between barrier rib patterns adjacent to each other and coupled to the conductive layers in the contact region.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: June 25, 2019
    Assignee: SK hynix Inc.
    Inventor: Yong Hyun Lim
  • Patent number: 10332608
    Abstract: A storage device includes storage circuitry and multiple memory blocks. The multiple memory blocks are arranged in an array, and each of the memory blocks includes multiple memory cells. A maximal number of programming cycles that a memory block of the multiple memory blocks sustains depends on a distance of the memory block from an edge of the array. The storage circuitry is configured to apply to the memory blocks programming cycles so that a number of programming cycles that can be applied to a respective memory block is based on a respective distance of the respective memory block from the edge of the array.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: June 25, 2019
    Assignee: APPLE INC.
    Inventors: Yael Shur, Assaf Shappir, Barak Baum, Roman Guy, Michael Tsohar
  • Patent number: 10303394
    Abstract: A memory system may include: a memory device having a plurality of blocks; and a controller suitable for performing a count operation on each of the blocks in response to a preset number of write requests, and performing a wear leveling operation based on the result of the count operation on each of the blocks.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: May 28, 2019
    Assignee: SK hynix Inc.
    Inventor: Chang-Hyun Park
  • Patent number: 10297338
    Abstract: A memory system includes: a semiconductor memory device; and a controller capable of issuing a first read instruction and a second read instruction different from the first read instruction. When receiving the first read instruction, the semiconductor memory device reads first data and second data from a memory cell array, holds the first data and the second data in the latch circuit, and outputs the first data to the controller. When receiving the second read instruction, the semiconductor memory device outputs third data based on the second data held by the latch circuit to the controller. The controller performs soft decision processing using the third data.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: May 21, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Masanobu Shirakawa, Kenji Sakurada, Hitoshi Shiga
  • Patent number: 10283195
    Abstract: Methods of operating a memory include receiving data for programming to a plurality of memory cells of the memory, redistributing the received data in a reversible manner, programming the redistributed data to the plurality of memory cells, and programming respective second data to each memory cell of the plurality of memory cells containing the redistributed data, wherein the respective second data for any memory cell of the plurality of memory cells has a same data value as the respective second data for each remaining memory cell of the plurality of memory cells.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: May 7, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Preston A. Thomson, Peiling Zhang, Junchao Chen
  • Patent number: 10229741
    Abstract: When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: March 12, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Takashi Maeda
  • Patent number: 10224340
    Abstract: A planar material layer stack including a lower etch stop dielectric layer, a sacrificial semiconductor layer, and an upper etch stop dielectric layer is formed over a source semiconductor layer on a substrate. An alternating stack of insulating layers and spacer material layers is formed. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. An array of memory stack structures is formed. A source cavity is formed by removing the sacrificial semiconductor layer and portions of the memory films. Source strap structures are formed by a selective semiconductor deposition process on the vertical semiconductor channels and the source semiconductor layer. A dielectric fill material layer fills a remaining volume of the source cavity.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: March 5, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Tsuyoshi Hada, Satoshi Shimizu, Kazuyo Matsumoto
  • Patent number: 10217503
    Abstract: A reading circuit for a charge-retention circuit stage is provided with a storage capacitor coupled between a first biasing terminal and a floating node, and a discharge element coupled between the floating node and a reference terminal. The reading circuit further has an operational amplifier having a first input terminal that is coupled to the floating node and receives a reading voltage, a second input terminal receives a reference voltage, and an output terminal on which it supplies an output voltage, the value of which is a function of the comparison between the reading voltage and the reference voltage and indicative of a residual charge in the storage capacitor. A shifting stage shifts the value of the reading voltage of the floating node, before the comparison is made between the reading voltage and the reference voltage for supplying the output voltage.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: February 26, 2019
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Rousset) SAS, STMicroelectronics S.r.l.
    Inventors: Antonino Conte, Enrico Castaldo, Raul Andres Bianchi, Francesco La Rosa
  • Patent number: 10210931
    Abstract: A nonvolatile memory device includes: first memory cells connected to a first source line and a first bit line; second memory cells connected to a second source line and a second bit line; and a sense amplifier circuit connected to the first and second source lines and the first and second bit lines. The sense amplifier circuit includes: a first sense amplifier configured to apply a first read voltage to the first bit line and output a first amount of current of a selected first memory cell; a second sense amplifier configured to apply a second read voltage to the second bit line and output a second amount of current of a selected second memory cell; and a comparator configured to compare the first amount of current with the second amount of current to identify data of the selected first memory cell.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: February 19, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Daeshik Kim
  • Patent number: 10204006
    Abstract: Embodiments are related to systems and methods for data storage, and more particularly to systems and methods for storing and accessing data from a flash memory.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: February 12, 2019
    Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
    Inventors: Zhijun Zhao, Shaohua Yang
  • Patent number: 10199082
    Abstract: A computer memory system, delay calibration circuit, and method of operating a delay calibration circuit are provided. The disclosed method includes providing a delay-line ring oscillator on silicon of a chip, providing at least one counter on the silicon of the chip, and measuring a chip-specific delay for performing an operation with the chip by synchronizing the at least one counter and operation of the delay-line ring oscillator with a timing trigger.
    Type: Grant
    Filed: January 18, 2016
    Date of Patent: February 5, 2019
    Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
    Inventors: Steven Affleck, Jerome Beckmann
  • Patent number: 10198316
    Abstract: Embodiments are related to systems and methods for data storage, and more particularly to systems and methods for storing and accessing data from a flash memory.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: February 5, 2019
    Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
    Inventors: Razmik Karabed, Zhijun Zhao, Shaohua Yang
  • Patent number: 10192597
    Abstract: Provided is a semiconductor device and an operating method thereof. The operating method of the semiconductor device includes performing a soft program operation on a top dummy cell and a bottom dummy cell, among dummy cells stacked in a vertical direction, by applying a first soft program voltage to a bottom dummy word line coupled to the bottom dummy cell and a second soft program voltage greater than the first soft program voltage to a top dummy word line coupled to the top dummy cell formed above the bottom dummy cell.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: January 29, 2019
    Assignee: SK hynix Inc.
    Inventor: Hee Youl Lee
  • Patent number: 10186323
    Abstract: A memory device includes first and second memory strings, first and second word lines and a controller. The first memory string includes first and second memory cells, a first select transistor, a second select transistor, and a third select transistor between the first and second memory cells. The second memory string includes third and fourth memory cells, a fourth select transistor above the third memory cell, a fifth select transistor below the fourth memory cell, and a sixth select transistor between the third and fourth memory cells. The first word line is electrically connected to gates of the first and third memory cells. The second word line is electrically connected to gates of the second and fourth memory cells. The controller is configured to execute a read operation on one of the memory cells, the read operation including a first phase and a second phase after the first phase.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: January 22, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Hiroshi Maejima
  • Patent number: 10170189
    Abstract: Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor material), a source gate device, and a source select device coupled between the source gate device and the string. Additional apparatus and methods are described.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: January 1, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Akira Goda, Shafqat Ahmed, Khaled Hasnat, Krishna K. Parat
  • Patent number: 10163518
    Abstract: Provided is a read method for a nonvolatile memory device for reading data with an optimum read voltage. The read method includes reading data of a first set of memory cells connected to a first word line, by dividing the data of the first set of memory cells into M pages and individually reading data from the M pages. The reading data includes performing an on-chip valley search (OVS) operation on a first valley of two adjacent threshold voltage distributions of the first set of memory cells when reading each of the M pages, and performing a data recover read operation via a read operation on a second word line adjacent to the first word line, based on a result of the OVS operation. In the data recover read operation, a read operation on the first word line is not performed.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: December 25, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-jun Yoon, Il-han Park, Na-young Choi, Seung-hwan Song
  • Patent number: 10163513
    Abstract: A program method of a memory device include determining whether valid data is stored in memory cells of a word line adjacent to a selection word line upon which a program operation is to be performed; when the valid data is not stored in the memory cells of the word line adjacent to the selection word line, performing, based on data to be written to the selection word line, a pre-program operation on the word line adjacent to the selection word line; and after the performing of the pre-program operation, performing, based on a program command, the program operation on the selection word line.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: December 25, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Il-han Park, Seung-jae Lee
  • Patent number: RE47169
    Abstract: An integrated circuit includes a NAND string including a string selection transistor SST and a ground selection transistor GST disposed at either end of series-connected memory storage cells MC. Each of the memory storage cells is a memory transistor having a floating gate, and at least one of the string selection transistor SST and the ground selection transistor GST is a memory transistor having a floating gate. The threshold voltage Vth of programmable string selection transistors SST and the ground selection transistor GST is variable and user controllable and need not be established by implantation during manufacture. Each of the programmable string selection transistors SST and the ground selection transistors GST in a memory block may be used to store random data, thus increasing the memory storage capacity of the flash memory device.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: December 18, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-Yean Oh, Woon-Kyung Lee, Seung-Chul Lee