Abstract: According to one embodiment, a semiconductor storage device includes strings each with a first select transistor, memory cell transistors, and a second select transistor connected in series. Word lines are provided, each connected to memory cell transistors in a same position across the strings. A bit line is connected in common to a first end of each of the strings. A source line is connected in common to a second end of each of the strings. A control circuit is configured to perform an erase operation on strings. The control circuit adjusts, for each of the strings, either an application time of a first voltage applied to a gate of the first select transistor of the respective string in the erase operation or a voltage level of the first voltage applied to the gate of the first select transistor of the respective string in the erase operation.

Abstract: A method for programming a memory. The method includes providing a memory structure with a floating gate, and grounding a source of the memory structure; applying voltages to a drain and a bulk, forming an electric field, generating electron-hole pairs, and generating primary electrons, wherein the voltage applied to the bulk is lower than the voltage applied to the drain; making holes accelerate downward under the action of the electric field and collide with the bulk in the memory structure within a predetermined time to generate secondary electrons; applying voltages to a gate and the bulk respectively, where the voltage applied to the bulk is lower than the voltage applied to the gate, to enable the secondary electrons to generate tertiary electrons under the action of an electric field in a vertical direction, and the tertiary electrons are injected into the floating gate to complete a programming operation.

Abstract: A memory structure including a substrate and memory cells is provided. The memory cells are stacked on the substrate. Each memory cell includes a first conductive layer, a first gate, a second gate, a second conductive layer, a channel layer, and a first charge storage layer. The first conductive layer, the first gate, the second gate, and the second conductive layer are sequentially stacked. The first conductive layer and the first gate are electrically insulated from each other. The first gate and the second gate are electrically insulated from each other. The second gate and the second conductive layer are electrically insulated from each other. The first gate and the second gate are electrically insulated from the channel layer. The first conductive layer and the second conductive layer are electrically connected to the channel layer. The first charge storage layer is located between the first gate and the channel layer.

Abstract: A selective non-volatile memory programming method for a selected memory cell in a memory array is described so as to reduce or avoid program disturbance on an unselected memory cell. This selective programming method comprises: applying a programming pulse to a selected memory cell to be programmed and an unselected memory cell, wherein the programming pulse allows a change of the unselected memory cell within a range specified; boosting a region of the unselected memory cell; and setting a threshold time of the programming pulse, wherein the threshold time is defined when an absolute magnitude of a voltage difference between a floating gate of the unselected memory cell and the boosted region of the unselected memory cell reaches a threshold value defined.

Abstract: The present disclosure relates to a method for programming a NAND flash memory, which includes: providing a NAND flash memory array, and initializing a to-be-programmed memory cell; applying a drain voltage to the drain of the to-be-programmed memory cell, and floating the source of the to-be-programmed memory cell; and applying a programming voltage to the gate of the to-be-programmed memory cell, and discharging the voltage at each end of the to-be-programmed memory cell after maintaining the voltage for a first time period, to complete programming; a difference between the voltage applied to the drain and the voltage applied to the substrate of the to-be-programmed memory cell being not less than 4 V, the first time period being not longer than 100 ?s, and the programming voltage being not higher than 10 V.

Abstract: A multi-time programming non-volatile memory includes a select transistor, a floating gate transistor, a switch transistor, a capacitor and an erase gate element. The select transistor is connected with a select line and a source line. The floating gate transistor includes a floating gate. The floating gate transistor is connected with the select transistor. The switch transistor is connected with a word line, the floating gate transistor and a bit line. A first terminal of the capacitor is connected with the floating gate. A second terminal of the capacitor is connected with a control line. The erase gate element includes the floating gate, a gate oxide layer and a p-type region. The erase gate element is connected with an erase line. The floating gate of the erase gate element at least includes an n-type floating gate part.

Abstract: A system and method of fabricating a semiconductor device include forming a series of gates, and forming a gate spacer on each side of each gate of the series of gates. The method includes forming a source region on a side of each of the gates and forming a drain region on an opposite side of each of the gates. The source region or the drain region between two adjacent ones of the gates is shared and only the source region or the drain region on one side of a first gate and the source region or the drain region on one side of a last gate in the series of gates are unshared source or drain regions. A self-aligned contact (SAC) is formed on the unshared source or drain regions. An air spacer is formed between the SACs and the first gate and the last gate.

Abstract: A program method of a nonvolatile memory device that performs a plurality of program loops is provided. At least one of the plurality of program loops includes dividing a channel of a selected cell string into a first side channel and a second side channel during a first interval and a second interval, turning off a string selection transistor of the selected cell string by applying a string select line voltage of a first level during the first interval, and boosting a first voltage of the first side channel and a second voltage of the second side channel, and turning on the string selection transistor by applying the string select line voltage of a second level different from the first level during the second interval, and performing a hot carrier injection (HCI) program operation on a selected memory cell corresponding to the first side channel or the second side channel.

Abstract: A three-dimensional (3D) semiconductor device is provided, comprising a substrate having an array area and a staircase area adjacent to the array area, wherein the staircase area comprises N steps, N is an integer one or greater; a stack having multi-layers on the substrate, and the multi-layers comprising active layers alternating with insulating layers on the substrate, the stack comprising sub-stacks formed on the substrate and the sub-stacks disposed in relation to the N steps of the staircase area to form respective contact regions, wherein an uppermost active layer of each of the sub-stacks in the respective contact regions comprises a silicide layer; and multilayered connectors, formed in the respective contact regions and extending downwardly to electrically connect the silicide layer in each of the sub-stacks.

Abstract: Unit cells including a substrate having an active region, a first charge trap pattern disposed on the substrate to intersect the active region, a second charge trap pattern disposed on the substrate to intersect the active region and spaced apart from the first charge trap pattern, a first junction region disposed in the active region between the first and second charge trap patterns, a second junction region disposed in the active region adjacent to one side of the first charge trap pattern opposite to the second charge trap pattern, and a third junction region disposed in the active region adjacent to one side of the second charge trap pattern opposite to the first charge trap pattern.

Abstract: A method of operating a memory cell that comprises first and second regions spaced apart in a substrate with a channel region therebetween, a floating gate disposed over the channel region and the fir region, a control gate disposed over the channel region and laterally adjacent to the floating gate with a portion disposed over the floating gate, and a coupling gate disposed over the first region and laterally adjacent to the floating gate. A method of erasing the memory cell includes applying a positive voltage to the control gate and a negative voltage to the coupling gate. A method of reading the memory cell includes applying positive voltages to the control gate, to the coupling gate, and to one of the first and second regions.

Abstract: Methods of complementary pairing of memory cells are described. These methods include two physical memory cells in a complementary pair, a complementary pair of reference cells for each erase block, and a physical complementary pair storing multiple data bits.

Abstract: A non-volatile memory cell comprises a coupling device, a first and a second select transistor, and a first and a second floating gate transistor is disclosed. The coupling device is formed in a first conductivity region. The first select transistor is serially connected to the first floating gate transistor and the second select transistor. Moreover, the first select transistor, the first floating gate transistor, and the second select transistor are formed in a second conductivity region. The second floating gate transistor is formed in a third conductivity region, wherein the first conductivity region, the second conductivity region, and the third conductivity region are formed in a fourth conductivity region. The first conductivity region, the second conductivity region, and the third conductivity region are wells, and the fourth conductivity region is a deep well. The third conductivity region surrounds the first conductivity region and the second conductivity region.

Abstract: A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.

Abstract: A flash memory device programs cells in each row in a manner that minimizes the number of programming pulses that must be applied to the cells during programming. The flash memory device includes a pseudo pass circuit that determines the number of data errors in each of a plurality of subsets of data that has been programmed in the row. The size of each subset corresponds to the number of read data bits coupled from the memory device, which are simultaneously applied to error checking and correcting circuitry. During iterative programming of a row of cells, the pseudo pass circuit indicates a pseudo pass condition to terminate further programming of the row if none of the subsets of data have a number of data errors that exceeds the number of data errors that can be corrected by the error checking and correcting circuitry.

Abstract: A memory includes an array of memory cells with each memory cell coupled to an associated pair of bit lines. Read control circuitry is configured to activate a number of addressed memory cells in order to couple each addressed memory cell to its associated pair of bit lines. Sense amplifier circuitry is then coupled to the bit lines to determine the data value stored in each addressed memory. In a speculative read mode of operation, the sense amplifier circuitry evaluates the differential signals. Error detection circuitry is then used to capture the differential signals on the associated pair of bit lines for each addressed memory cell, and to apply an error detection operation to determine if the differential signals as evaluated by the sense amplifier circuitry had not developed to the necessary degree and, in that event, an error signal is asserted.

Abstract: An self-refresh control circuit for controlling a self-refresh operation of a memory device includes a self-refresh control logic block configured to control the memory device to perform the self-refresh operation and an initial refresh control block configured to activate the self-refresh control logic block in an initialization period of the memory device.

Abstract: Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a first region connected to a bit line extending in a first orientation and a second region connected to a source line extending in a second orientation. The direct injection semiconductor memory device may also include a body region spaced apart from and capacitively coupled to a word line extending in the second orientation, wherein the body region is electrically floating and disposed between the first region and the second region. The direct injection semiconductor memory device may further include a third region connected to a carrier injection line extending in the second orientation, wherein the first region, the second region, the body region, and the third region are disposed in sequential contiguous relationship.

Abstract: The non-volatile memory cell includes a coupling device and a first select transistor. The coupling device is formed in a first conductivity region. The first select transistor is serially connected to a first floating gate transistor and a second select transistor, all formed in a second conductivity region. An electrode of the coupling device and a gate of the first floating gate transistor are a monolithically formed floating gate; wherein the first conductivity region and the second conductivity region are formed in a third conductivity region; wherein the first conductivity region, the second conductivity region, and the third conductivity region are wells.

Abstract: A manipulating method of a nonvolatile memory is provided and comprises following steps. The nonvolatile memory having a plurality of memory cell is provided. Two adjacent memory cells correspond to one bit and comprise a substrate, a first and another first doping regions, a second doping region, a charge trapping layer, a control gate, a first bit line, a source line and a second bit line different from the first bit line. A first and a second channel are formed. The charge trapping layer is disposed on the first and the second channels. The two adjacent memory cells are programmed by following steps. A first positive and negative voltages are applied to the control gate between the first and the second doping regions and the control gate between the second and the another first doping regions, respectively. A first voltage is applied to the source line.

Abstract: A method includes receiving hard bit data and soft bit data corresponding to a portion of a memory, where each storage element of the memory stores multiple bits per storage element. The hard bit data and the soft bit data is received in connection with reading a single bit of the multiple bits from each storage element in the portion of the memory based on one or more first read voltages. One or more second read voltages based on the hard bit data and the soft bit data are generated in response to a read voltage update operation. The memory reads data from the portion of the memory using the one or more second read voltages.

Abstract: Strings of memory cells having a string select gate configured to selectively couple ends of a string to a data line and a source line concurrently, memory devices incorporating such strings and methods for accessing and forming such strings are provided. For example, non-volatile memory devices are disclosed that utilize vertical structure NAND strings of serially-connected non-volatile memory cells. One such string including two or more serially-connected non-volatile memory cells where each end of the string shares a string select gate with the other end of the string is disclosed.

Abstract: A system and method are provided for using a thermal management core to control temperature on a system-on-chip (SoC). The method provides an SoC with an internal thermal management core and an internal temperature sensor. For example, the sensor may be located on or near a processor core die. The thermal management core monitors temperatures recorded by the SoC temperature sensor, and sends commands for controlling SoC device functions. In response to these commands, the thermal management core monitors a change in the temperature at SoC temperature sensor. The temperature sensor may be monitored via a dedicated SoC internal interface connecting the processor and the thermal management core. Alternately, the thermal management core may poll for temperatures via a system management bus (SMBUS) SoC external interface connecting the processor and thermal management core. Further, a dedicated SoC external alert interface connecting the processor and thermal management core may be monitored.

Abstract: A manipulating method of a nonvolatile memory is provided and comprises following steps. The nonvolatile memory having a plurality of memory cell is provided. Two adjacent memory cells correspond to one bit and comprise a substrate, a first and another first doping regions, a second doping region, a charge trapping layer, a control gate, a first bit line, a source line and a second bit line different from the first bit line. A first and a second channel are formed. The charge trapping layer is disposed on the first and the second channels. The two adjacent memory cells are programmed by following steps. A first positive and negative voltages are applied to the control gate between the first and the second doping regions and the control gate between the second and the another first doping regions, respectively. A first voltage is applied to the source line.

Abstract: A p-channel flash memory device including a 3D NAND array has excellent performance characteristics. Techniques for operating 3D, p-channel NAND arrays include selective programming, selective (bit) erase, and block erase. Selective programming bias arrangements induce band-to-band tunneling current hot electron injection to increase threshold voltages in selected cells. Selective erase biasing arrangements induce ?FN hole tunneling to decrease threshold voltages in selected cells. Also, block erase bias arrangements induce ?FN hole tunneling in selected blocks of cells.

Abstract: N-channel multi-time programmable memory devices having an N-conductivity type substrate, first and second P-conductivity type wells in the N-conductivity type substrate, N-conductivity type source and drain regions formed in the first P-conductivity type well, the source and drain regions being separated by a channel region, an oxide layer over the N-conductivity type substrate; and a floating gate extending over the channel region and over the second P-conductivity type well in the N-conductivity type substrate, the multi-time programmable memory cell being programmable by hot electron injection and erasable by hot hole injection.

Abstract: An asymmetric non-volatile memory bitcell is described. The bitcell comprises source and drain regions comprising carriers of the same conductivity type. A floating gate rests on top of the well, and extends over a channel region, and at least a portion of the source and drain regions. The drain region comprises additional carriers of a second conductivity type, allowing band to band tunneling. The source region comprises additional carriers of a first conductivity type, thereby increasing source-gate capacitance. Thus, the bitcell incorporates a select device, thereby decreasing the overall size of the bitcell. The bitcell may be created without any additional CMOS process steps, or through the addition of a single extra mask step.

Abstract: A semiconductor memory device and a method of operating the same are disclosed. The semiconductor memory device includes a memory cell array configured to include memory cells, a peripheral circuit configured to perform an erase operation and a soft program operation and a control circuit configured to control the peripheral circuit so that the memory cells are programmed though a hot carrier injection HCI method when the soft program operation is performed.

Abstract: A control circuit for a read operation of a SERDES (SERializer and DESeriallizer) type semiconductor memory apparatus is disclosed that includes a first line driver configured to output a portion of a output signals from sense amplifier according to a first delay signal; a second line driver configured to output a rest of the output signals from the sense amplifier according to a second delay signal; and a first delay unit configured to output a second delay signal synchronized with a clock to the second line driver.

Abstract: Non-volatile memory (NVM) devices are disclosed. In one aspect, a NVM device may include a substrate, and a field-effect transistor (FET). The FET may include a first doped region in the substrate and a second doped region in the substrate. The first and the second doped regions may define a channel region of the substrate between them. An insulating layer may overlie the channel region. A floating gate may overlie the insulating layer. Charge of an amount that encodes a value may be stored on the floating gate. The floating gate and the first and the second doped regions may be shaped such that the floating gate defines with the first doped region a first border of a first length, and the floating gate defines with the second doped region a second border of a second length that is less than 90% of the first length.

Abstract: One embodiment provides a programmable logic device in which a logic switch includes: a first memory having a first terminal connected to a first wire, a second terminal connected to a second wire, and a third terminal connected to a third wire; a second memory having a fourth terminal connected to the first wire, a fifth terminal connected to a fourth wire, and a sixth terminal connected to a fifth wire; and a pass transistor having a gate connected to the first terminal, and a source and a drain respectively connected to a sixth wire and a seventh wire. A source or drain of a first select gate transistor is connected the sixth wire, and a source or drain of a second select gate transistor is connected to the seventh wire.

Abstract: A non-volatile memory system includes one or more non-volatile memory cells. Each non-volatile memory cell provides a floating gate, a coupling device, a first floating gate transistor, and a second floating gate transistor. The coupling device is located in a first conductivity region. The first floating gate transistor is located in a second conductivity region, and supplies read current sensed during a read operation. The second floating gate transistor is located in a third conductivity region. Such non-volatile memory cell further provides two transistors for injecting negative charge into the floating gate during a programming operation, and removing negative charge from the second floating gate transistor during an erase operation. The floating gate is shared by the first floating gate transistor, the coupling device, and the second floating gate transistor, and extends over active regions of the first floating gate transistor, the coupling device and the second floating gate transistor.

Abstract: A memory cell including a drain, a channel, and a floating gate. The channel surrounds the drain and includes a first rounded closed curve structure around the drain. The floating gate is situated over the channel and includes a second rounded closed curve structure over the channel.

Abstract: Disclosed is an operating method of a nonvolatile memory device, which includes programming the first selection transistors of the plurality of cell strings and programming the plurality of memory cells of the plurality of cell strings. The programming the first selection transistors comprises supplying a first voltage to a first bit line connected with a first selection transistor to be programmed and a different second voltage to a second bit line connected to a first selection transistor to be program inhibited; turning on the second selection transistors of the plurality of cell strings, and supplying a first program voltage to a selected first selection line among a plurality of first selection lines connected with the first selection transistors and a third voltage to an unselected first selection line among the plurality of first selection lines.

Abstract: The present invention provides circuits, systems, and methods for programming a floating gate. As described herein, a floating gate tunneling device is used with an analog comparison device in a circuit having a floating reference node and an offset-mitigating feedback loop for iteratively programming a floating gate or multiple floating gates.

Abstract: A non-volatile memory cell includes first and second regions and a channel region therebetween, a word line gate over a first portion of the channel region, a floating gate over another portion of the channel region and adjacent to the word line gate, a coupling gate over the floating gate, and an erase gate adjacent to the floating gate on an opposite side to the word line gate and over the second region. Programming the memory cell includes applying a first positive voltage to the word line gate, applying a voltage differential between the first and second regions, applying a second positive voltage to the coupling gate (where the voltages and the voltage differential are applied substantially at the same time), and applying a third positive voltage to the erase gate after a period of delay from the application of the first and second positive voltages and the voltage differential.

Abstract: Provided is a flash memory device including a wordline voltage generating unit, a switch unit, a row decoder and a control circuit. The wordline voltage generating unit generates at least one wordline voltage for read operations of a multi-level cell in the flash memory device. The switch unit receives the at least one wordline voltage and an initialization voltage, and selectively outputs the at least one wordline voltage and the initialization voltage through a switching operation. The row decoder operates the wordline of the multi-level cell based on an output of the switch unit. The control circuit provides at least one control signal to the switch unit, which outputs the initialization voltage in at least one section of the read operation in response to the at least one control signal.

Abstract: A method of programming a nonvolatile memory cell which comprises a select transistor and a memory transistor includes applying a preset limit current to a first input of the memory cell, applying a limit voltage to a current limiting circuit electrically connected to a second input of the memory cell, applying a limit voltage to stabilize a voltage drop of the memory cell, and applying a ramped gate voltage to the memory cell to program the memory cell with a preset limited current determined by the current limiting circuit.

Abstract: Non-volatile memory (NVM) devices are disclosed. In one aspect, a NVM device may include a substrate, and a field-effect transistor (FET). The FET may include a first doped region in the substrate and a second doped region in the substrate. The first and the second doped regions may define a channel region of the substrate between them. An insulating layer may overlie the channel region. A floating gate may overlie the insulating layer. Charge of an amount that encodes a value may be stored on the floating gate. The floating gate and the first and the second doped regions may be shaped such that the floating gate defines with the first doped region a first border of a first length, and the floating gate defines with the second doped region a second border of a second length that is less than 90% of the first length.

Abstract: Non-volatile memory is programmed using source side hot electron injection. To generate a high voltage bit line for programming, the bit line corresponding to a selected memory cell is charged to a first level using a first low voltage. A second low voltage is applied to unselected bit lines adjacent to the selected bit line after charging. Because of capacitive coupling between the adjacent bit lines and the selected bit line, the selected bit line is boosted above the first voltage level by application of the second low voltage to the unselected bit lines. The column control circuitry for such a memory array does not directly apply the high voltage and thus, can be designed to withstand lower operating voltages, permitting low operating voltage circuitry to be used.

Abstract: A non-volatile memory system includes one or more non-volatile memory cells. Each non-volatile memory cell provides a floating gate, a coupling device, a first floating gate transistor, and a second floating gate transistor. The coupling device is located in a first conductivity region. The first floating gate transistor is located in a second conductivity region, and supplies read current sensed during a read operation. The second floating gate transistor is located in a third conductivity region. Such non-volatile memory cell further provides two transistors for injecting negative charge into the floating gate during a programming operation, and removing negative charge from the second floating gate transistor during an erase operation. The floating gate is shared by the first floating gate transistor, the coupling device, and the second floating gate transistor, and extends over active regions of the first floating gate transistor, the coupling device and the second floating gate transistor.

Abstract: A non-volatile memory cell and array structure is disclosed situated within a high voltage region of an integrated circuit. The cell utilizes capacitive coupling based on an overlap between a gate and a drift region to impart a programming voltage. Programming is effectuated using a drain extension which can act to inject hot electrons. The cell can be operated as a one-time programmable (OTP) or multiple-time programmable (MTP) device. The fabrication of the cell relies on processing steps associated with high voltage devices, thus avoiding the need for additional masks, manufacturing steps, etc.

Abstract: A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.

Abstract: In a system having a plurality of non-volatile memory cells, a method includes performing hot carrier injection on a first non-volatile memory cell in a first mode of programming. In the first mode, current flows from a first current electrode to a second electrode of the first non-volatile memory cell and charge is transferred from the current to a floating gate of the first non-volatile memory cell at a location nearer the first current electrode than the second current electrode. The method further includes performing hot carrier injection on the first non-volatile memory cell in a second mode of programming. In the second mode, current flows from the second current electrode to the first electrode of the first non-volatile memory cell and charge is transferred from the current to the floating gate of the first non-volatile memory cell at a location nearer the second current electrode than the first current electrode.

Abstract: Disclosed is an operating method of a nonvolatile memory device, which includes programming the first selection transistors of the plurality of cell strings and programming the plurality of memory cells of the plurality of cell strings. The programming the first selection transistors comprises supplying a first voltage to a first bit line connected with a first selection transistor to be programmed and a different second voltage to a second bit line connected to a first selection transistor to be program inhibited; turning on the second selection transistors of the plurality of cell strings, and supplying a first program voltage to a selected first selection line among a plurality of first selection lines connected with the first selection transistors and a third voltage to an unselected first selection line among the plurality of first selection lines.

Abstract: A mobile System on Chip (SoC) comprises a microprocessor and a first memory controller configured to control a refresh of a first memory. A temperature sensor detects a temperature in the first memory. When first temperature information received from the temperature sensor indicates that the detected temperature deviates from a predetermined temperature range, the first memory controller controls the first memory so as not to perform a self refresh. When second temperature information received from the temperature sensor indicates that the detected temperature is in the predetermined temperature range, the first memory controller outputs a self refresh command to the first memory.

Abstract: A semiconductor memory device and a method of manufacturing the same.

Abstract: A single-polysilicon layer non-volatile memory having a floating gate transistor, a program gate and a control gate is provided. The floating gate transistor has a floating gate and a tunneling dielectric layer. The floating gate is disposed on a substrate. The tunneling dielectric layer is disposed between the floating gate and the substrate. The program gate, the control gate and the erase gate are respectively disposed in the substrate under the floating gate separated by the tunneling dielectric layer. Therefore, during a program operation and an erase operation, charges are injected in and expelled out through different regions of the tunneling dielectric layer, so as to increase reliability of the non-volatile memory.

Abstract: Retention of charges in a nonvolatile memory (NVM) cell having a nitride-based injector (such as SiN, SIRN, SiON) for facilitating injection of holes into a charge-storage layer (for NROM, nitride) of a charge-storage stack (for NROM, ONO) may be improved by providing an insulating layer (for NROM, oxide) between the charge-storage layer and the injector has a thickness of at least 3 nm. Top and bottom injectors are disclosed. Methods of operating NVM cells are disclosed. The NVM cell may be NROM, SONOS, or other oxide-nitride technology NVM cells such as SANOS, MANOS, TANOS.

Abstract: A semiconductor memory apparatus and refresh control method are presented. The semiconductor memory apparatus includes a memory cell block composed of a multiplicity of floating body cell (FBC) transistors. Each FBC transistor has a gate connected to a word line, a drain connected to a bit line, and a source connected to a source line. FBC transistor pairs are formed by sharing the source lines in the plurality of the floating body cell transistors. When a refresh signal is enabled, the semiconductor memory apparatus is configured to read data stored in the memory cell block by enabling a refresh read signal and then configured to rewrite the read data in the memory cell block by enabling a refresh write signal.