Program Gate Patents (Class 365/185.14)
  • Patent number: 10297336
    Abstract: Provided herein is a fail bit counter. The fail bit counter includes a pass/fail data receiver receiving pass/fail data indicating whether memory cells coupled to a bit line sequentially pass or fail, and a fail bit accumulator receiving a fail bit generation signal from the pass/fail data receiver, and accumulating and counting fail bits which are generated.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: May 21, 2019
    Assignee: SK hynix Inc.
    Inventors: Yong Hwan Hong, Byung Ryul Kim
  • Patent number: 10229745
    Abstract: Techniques for suppression of program disturb in flash memory devices are described herein. In an example embodiment, an apparatus comprises a flash memory device coupled to a microprocessor. The flash memory device comprises rows and columns of memory cells, where the memory cells in each row are coupled to a source line and to a select-gate (SG) line, and the memory cells in each column are coupled to a respective bit line (BL). A control circuit in the flash memory device is configured to regulate both a first voltage, of a selected SG line, and a second voltage, of an unselected BL, independently of a power supply voltage of the flash memory device, and to adjust at least one of the first voltage and the second voltage based on a measure of an operating temperature of the flash memory device.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: March 12, 2019
    Assignee: Cypress Semiconductor Corporation
    Inventors: Chun Chen, Kuo-Tung Chang, Yoram Betser, Shivananda Shetty, Giovanni Mazzeo, Tio Wei Neo, Pawan Singh
  • Patent number: 10224108
    Abstract: A non-volatile memory includes a first memory cell. The first memory cell includes five transistors and a first capacitor. The first transistor includes a first gate, a first terminal and a second terminal. The second transistor includes a second gate, a third terminal and a fourth terminal. The third transistor includes a third gate, a fifth terminal and a sixth terminal. The fourth transistor includes a fourth gate, a seventh terminal and an eighth terminal. The fifth transistor includes a fifth gate, a ninth terminal and a tenth terminal. The first capacitor is connected between the third gate and a control line. The third gate is a floating gate. The second terminal is connected with the third terminal. The fourth terminal is connected with the fifth terminal. The sixth terminal is connected with the seventh terminal. The eighth terminal is connected with the ninth terminal.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: March 5, 2019
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Wen-Hao Ching, Shih-Chen Wang
  • Patent number: 10163516
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a gate stack over the semiconductor substrate. The gate stack includes a first insulating layer, a charge trapping structure, a second insulating layer, and a gate electrode. The first insulating layer separates the semiconductor substrate from the charge trapping structure. The charge trapping structure is between the first insulating layer and the second insulating layer. The gate electrode is over the second insulating layer. The charge trapping structure includes a first layer and a second layer. The first layer includes zinc oxide, tin dioxide, titanium oxide, zinc tin oxide, indium oxide, indium zinc oxide, indium gallium zinc oxide, zinc oxynitride, tin oxynitride, titanium oxynitride, zinc tin oxynitride, indium oxynitride, indium zinc oxynitride, or indium gallium zinc oxynitride.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: I-Chen Huang, Kuang-Hsin Chen, Yung-Hsien Wu, Wen-Chao Shen
  • Patent number: 9990979
    Abstract: A semiconductor memory device is disclosed that can differentially control a driving ability and current consumption of the charge pump circuit according to operation state information of other memory die. The semiconductor memory device includes a plurality of charge pump circuits installed on a plurality of memory dies, and a pump managing circuit installed on each of the memory dies to control the charge pump circuits and receive operation state information with respect to other memory die to generate control signals for controlling the charge pump circuits on its own memory die.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: June 5, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Minsang Park
  • Patent number: 9928909
    Abstract: A circuit having a Resistive Random Access Memory (RRAM) cell coupled between a supply voltage and a sense node; a first transistor coupled between the sense node and a source voltage; and a sub-circuit configured to have a sense voltage at the sense node be lower than a bias voltage at the gate of the first transistor.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: March 27, 2018
    Assignee: Infineon Technologies AG
    Inventor: Ulrich Loibl
  • Patent number: 9911502
    Abstract: According to one embodiment, a data storage device includes a controller driven by a first power supply voltage, a nonvolatile memory controlled by the controller and driven by a second power supply voltage, and a switch element determining whether the second power supply voltage is applied to the nonvolatile memory. The controller is configured to turn off the switch element in a first mode and turn on the switch element in a second mode.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: March 6, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Koichi Nagai, Katsuya Murakami, Shinji Honjo, Satoru Fukuchi, Akira Tanimoto, Isao Ozawa
  • Patent number: 9887301
    Abstract: Performances of a semiconductor device are improved. The semiconductor device has: a gate electrode formed on an SOI layer of an SOI substrate via a gate insulating film having a charge storage film therein; an n-type semiconductor region and a p-type semiconductor region respectively formed on SOI layers on both sides of the gate electrode. A memory cell MC serving as a non-volatile memory cell is formed of the gate insulating film, the gate electrode, the n-type semiconductor region and the p-type semiconductor region.
    Type: Grant
    Filed: July 3, 2016
    Date of Patent: February 6, 2018
    Assignee: Renesas Electric Corporation
    Inventor: Hideki Makiyama
  • Patent number: 9865598
    Abstract: Disclosed herein are processes and structures for uniform STI recessing. A method of making a semiconductor device includes initially forming a dense region of at least two fins on a substrate. The fins have a hard mask layer on a surface. The dense region with the fins is adjacent to an isolated region without fins within a distance of a pitch of the fins. An oxide is deposited on the dense and isolated regions. The oxide is polished, stopping on the hard mask layer on the fins, and removing more oxide in the isolated region. Polishing results in forming a non-uniform oxide surface. The hard mask layer is removed from the fins. An etch process is performed to further recess the oxide in the dense and isolated regions, such that a thickness of the oxide in the dense region and the isolated region is substantially uniform.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: January 9, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zhenxing Bi, Kangguo Cheng, Juntao Li, Peng Xu
  • Patent number: 9847322
    Abstract: There is provided a structure and a method of manufacturing a semiconductor package. The method includes disposing a first semiconductor device and through mold ball connectors (TMBCs) on a first surface of an interconnection structure layer, recessing a molding layer on the first surface of the interconnection structure layer to expose a portion of each of the TMBCs, attaching outer connectors to the exposed portions of the TMBCs, and mounting a second semiconductor device on a second surface of the interconnection structure layer opposite to the molding layer.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: December 19, 2017
    Assignee: SK hynix Inc.
    Inventors: Ki Jun Sung, Jong Hoon Kim, Yeon Seung Jung, Hyeong Seok Choi
  • Patent number: 9780110
    Abstract: Some embodiments include apparatuses and methods having a conductive line, a memory cell string including memory cells located in different levels the apparatus, and a select circuit including a select transistor and a coupling component coupled between the conductive line and the memory cell string. Other embodiments including additional apparatuses and methods are described.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: October 3, 2017
    Assignee: Micron Technology
    Inventor: Toru Tanzawa
  • Patent number: 9754679
    Abstract: An OTP (One-Time Programmable) memory including OTP memory cells that utilize OTP elements fabricated in CMOS FinFET processes. The OTP memory cell can also include at least one selector built upon at least one fin structure that has at least one CMOS gate to divide the fin structure into at least a first and a second active region. The selector can be implemented as a MOS device, dummy-gate diode, or Schottky diode as selector such as by using different types of source/drain implants. The OTP element that can be implemented as polysilicon, silicided polysilicon, CMOS metal gate, any layers of metal as interconnect, or active region. In one embodiment, the OTP element can be a fin structure and can be built upon the same fin structure as the at least one of the selector. By using different source/drain implant schemes on the two active regions, the selector can be turned on as MOS device, MOS device and/or diode, dummy-gate diode, or Schottky diode.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: September 5, 2017
    Assignee: Attopsemi Technology Co., Ltd
    Inventor: Shine C. Chung
  • Patent number: 9721666
    Abstract: A memory system includes a semiconductor memory device having memory cells arranged in rows and columns, and a controller configured to issue a write command with or without a partial page program command to the semiconductor memory device. The semiconductor memory device, in response to the write command issued without the partial page command, executes a first program operation on a page of memory cells and then a first verify operation on the memory cells of the page using a first verify voltage for all of the memory cells of the page, and in response to the write command issued with the partial page command, executes a second program operation on a subset of the memory cells of the page and then a second verify operation on the memory cells of the subset using one of several different second verify voltages corresponding to the subset.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: August 1, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masanobu Shirakawa, Kenta Yasufuku, Akira Yamaga
  • Patent number: 9704593
    Abstract: According to one embodiment, a data storage device includes a controller driven by a first power supply voltage, a nonvolatile memory controlled by the controller and driven by a second power supply voltage, and a switch element determining whether the second power supply voltage is applied to the nonvolatile memory. The controller is configured to turn off the switch element in a first mode and turn on the switch element in a second mode.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: July 11, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Koichi Nagai, Katsuya Murakami, Shinji Honjo, Satoru Fukuchi, Akira Tanimoto, Isao Ozawa
  • Patent number: 9653126
    Abstract: Methods for controlling a ramp rate of an output voltage derived from one or more charge pumps and reducing variation in the ramp rate due to process, voltage, and temperature (PVT) variations are described. In some embodiments, the ramp rate of the output voltage from one or more charge pumps may be controlled using a ramp rate control circuit that uses a digital counter to adjust (or step up) the output voltage from the one or more charge pumps based on a ramp rate schedule. The ramp rate schedule may specify varying output voltage levels for the one or more charge pumps during a time period in which the output voltage charges up from a first voltage to a second voltage greater than the first voltage.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: May 16, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Qui Vi Nguyen, Steve Choi
  • Patent number: 9627074
    Abstract: A method for determining an optimal voltage pulse for programming a flash memory cell, the optimal voltage pulse being defined by a voltage ramp from a non-zero initial voltage level during a programming duration, wherein the method takes into account a set of parameters including a programming window target value and a drain current target value of the memory cell.
    Type: Grant
    Filed: April 19, 2016
    Date of Patent: April 18, 2017
    Assignee: COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES
    Inventor: Jean Coignus
  • Patent number: 9524793
    Abstract: There are provided a semiconductor memory device and an operating method thereof. A semiconductor memory device includes a memory cell array including a plurality of memory cells connected between a source select transistor and a drain select transistor, a peripheral circuit for performing a program operation on the memory cell array, and a control logic for controlling the peripheral circuit such that the potential level of a source control voltage applied to the source select transistor as a selected memory cell is closer to the drain select transistor in a program verify operation during the program operation.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: December 20, 2016
    Assignee: SK hynix Inc.
    Inventor: Hee Youl Lee
  • Patent number: 9460806
    Abstract: A method of forming an OTPROM capable of storing twice the number of bits as a conventional OTPROM without increasing the overall size of the device is provided. Embodiments include forming a OTPROM, the OTPROM array having a plurality of formed devices; receiving a binary code to program the OTPROM array; separating the binary code into a first part and a second part; programming each device with one of four data storage states by: forming a gate oxide layer of each device to a thickness corresponding to the first part of the binary code, and selectively applying a TDDB stress to the gate oxide layer corresponding to the second part of the binary code; detecting a Idsat level discharged by each device with a multi-bit sense amplifier; and reading the state of each device based on the detected Idsat level.
    Type: Grant
    Filed: April 7, 2015
    Date of Patent: October 4, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Akhilesh Gautam, Suresh Uppal
  • Patent number: 9460780
    Abstract: Methods are provided for programming multi-level non-volatile memory cells, the multi-level non-volatile memory cells accessible by a plurality of word lines. The methods include using a four-pass programming technique to program a block of the multi-level non-volatile memory cells, detecting a power cycle before completing programming of the block of the multi-level non-volatile memory cells, and upon power-up initialization, resuming programming on the block of the multi-level non-volatile memory cells.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: October 4, 2016
    Assignee: SanDisk Technologies LLC
    Inventors: Aaron Lee, Mrinal Kochar, Abhijeet Bhalerao, Mikhail Palityka
  • Patent number: 9443594
    Abstract: A logic embedded nonvolatile memory device is provided which includes a first erase gate line for erasing a plurality of first memory cells; a second erase gate line electrically separated from the first erase gate line and for erasing a plurality of second memory cells; a global erase gate line supplied with an erase voltage; and an erase gate selection switch formed between the first memory cells and the second memory cells, wherein the erase gate selection switch connects the global erase gate line to the first erase gate line or the second erase gate line according to an erase control signal.
    Type: Grant
    Filed: October 7, 2014
    Date of Patent: September 13, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: ChangMin Jeon, Teakwang Yu, Yongtae Kim, Boyoung Seo
  • Patent number: 9418744
    Abstract: An improved control gate decoding design may reduce disturbances during the programming of flash memory cells. In one embodiment, a control gate line decoder is coupled to a first control gate line associated with a row of flash memory cells in a first sector and to a second control gate line associated with a row of flash memory cells in a second sector.
    Type: Grant
    Filed: May 12, 2014
    Date of Patent: August 16, 2016
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Jinho Kim, Anh Ly, Victor Markov
  • Patent number: 9396770
    Abstract: The storage layer such as a nitride layer of a nonvolatile memory cell has two storage parts storing separately addressable data, typically respectively proximate to the source terminal and the drain terminal. The applied drain voltage while sensing the data of one of the storage parts depends on the data stored at the other storage part; the different parts can be in different, neighboring memory cells. If the data stored at the other storage part is represented by a threshold voltage exceeding a minimum threshold voltage, then the applied drain voltage is raised. This technology is useful in read operations and program verify operations to widen the threshold voltage window.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: July 19, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Han-Sung Chen, Chung-Kuang Chen, Chun-Hsiung Hung
  • Patent number: 9384799
    Abstract: Controllers, interfaces, memory devices, methods and systems are disclosed, including a controller configured to interface with a separate memory device and perform an iterative write operation to program a selected memory cell of the memory device to a target state, wherein each iteration of the write operation is configured to successively change a physical state of the selected memory cell. Other controllers, interfaces, memory device, methods and systems are also described, such as those where either a controller or a memory device can throttle a data communication operation, and/or those that utilize customized programming pulses.
    Type: Grant
    Filed: March 21, 2013
    Date of Patent: July 5, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Larry J. Koudele
  • Patent number: 9378822
    Abstract: A method for programming memory cells of a selected word line has steps of: providing a first word line programming signal being at plurality of voltage levels in different programming slots of a current programming operation to the memory cells of the selected word line, wherein the first word line programming signal is a ramping voltage signal; and providing a second line programming signal being at plurality of voltage levels in different programming slots of a next programming operation to the memory cells of the selected word line, wherein the second word line programming signal is another one ramping voltage signal; wherein the highest voltage levels of the first and second word line programming signals are identical to each other, and a number of the voltage levels of the first word line programming signal is larger than that of the second word line programming signal.
    Type: Grant
    Filed: May 17, 2014
    Date of Patent: June 28, 2016
    Assignee: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
    Inventor: Chung-Shan Kuo
  • Patent number: 9331095
    Abstract: Nonvolatile memory devices utilize vertically-stacked strings of nonvolatile memory cells (e.g., NAND-type strings) that can be selectively coupled to common source lines within a substrate. This selective coupling may be provided by lateral ground select transistors having different threshold voltages that account for different lateral spacings between the vertically-stacked strings of nonvolatile memory cells and the common source lines.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: May 3, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sunil Shim, Jaehun Jeong, Jaehoon Jang, Kihyun Kim
  • Patent number: 9245642
    Abstract: Techniques are provided for reducing program disturb in a 3D memory device. The techniques include compensating for a temperature dependence of program disturb. The techniques may include compensating for how program disturb depends on the location of the word line that is selected for programming. In one aspect, the voltage that is applied to the control gates drain side select transistors of unselected NAND strings is adjusted during programming based on temperature. Greater temperature compensation may be applied when the selected word line is closer to the drain side select transistors.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: January 26, 2016
    Assignee: SanDisk Technologies Inc.
    Inventors: Jian Chen, Yingda Dong, Jiahui Yuan
  • Patent number: 9236128
    Abstract: When applying a programming voltage at one end of a word line of a non-volatile memory circuit, if the word line has a large RC constant the far end of the word line will not rise as fast as the driven end, which can adversely affect device performance. To more quickly raise the voltage on the selected word line, a voltage kick is applied to non-selected word lines, such as dummy word lines, by way of a non-selected sub-block of the selected block. The channel of NAND strings in the non-selected sub-block is used to transfer the kick to the far end of the selected word line of the selected sub-block.
    Type: Grant
    Filed: February 2, 2015
    Date of Patent: January 12, 2016
    Assignee: SanDisk Technologies Inc.
    Inventors: Kenneth Louie, Khanh Nguyen, Man Mui
  • Patent number: 9190148
    Abstract: A semiconductor memory storage device includes first and second doped regions of a first type disposed in a semiconductor substrate. The first and second doped regions of the first type being laterally spaced from one another. A gate dielectric extends over the semiconductor substrate between the first and second doped regions, and a floating gate is disposed on the gate dielectric. An ultraviolet (UV) light blocking material is vertically disposed above the floating gate and has a size that covers the floating gate such that the floating gate remains electrically charged after the semiconductor memory storage device is exposed to UV light.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: November 17, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsiang-Tai Lu, Chih-Hsien Lin
  • Patent number: 9171944
    Abstract: The present invention provides a tunneling field effect transistor and a method for fabricating the same which refer to a field effect transistor logic device and circuit in a CMOS ultra-large integrated circuit (ULSI). The inventive concept of the invention lies in that, in a case of an N-type transistor, a side portion of a doped source region adjacent to an edge of the control gate is further implanted with P+ impurities on a basis of the doped source region being initially doped N? impurities, so that the initial N? impurities in the implanted portion are completely compensated by the P+ impurities, and in a case of a P-type transistor, a side portion of the doped source region adjacent to an edge of the control gate is implanted with N+ impurities on a basis of the doped source region being initially doped P? impurities, so that the initial P? impurities in the implanted portion are completely compensated by the N+ impurities.
    Type: Grant
    Filed: April 27, 2013
    Date of Patent: October 27, 2015
    Assignee: Peking University
    Inventors: Ru Huang, Qianqian Huang, Zhan Zhan, Yingxin Qiu, Yangyuan Wang
  • Patent number: 9142311
    Abstract: Selecting an array from among a plurality of arrays in a memory as a reference array. An exemplary method includes evaluating memory cells within the reference array to select a first reference cell associated with a first operation of the memory, and repeating the evaluating and the selecting to select a second reference cell from within the reference array, the second reference cell being associated with a second operation of the memory.
    Type: Grant
    Filed: June 13, 2013
    Date of Patent: September 22, 2015
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Zhizheng Liu, Cindy Sun, He Yi, Gulzar Kathawala
  • Patent number: 9105338
    Abstract: The present invention provides an OTP memory having higher confidentiality. A memory cell has a memory transistor forming a current path between first and second nodes, a selection transistor forming a current path between third and fourth nodes, the third node being coupled to the gate of the memory transistor via a line, and a capacitor coupled to the first node. By applying high voltage which does not break but deteriorates a gate oxide film and increases gate leak current to a memory transistor, data is written. Data can be read by the presence/absence of leak of charges accumulated in the capacitor. Since the position of deterioration in the gate oxide film cannot be discriminated by a physical analysis, confidentiality is high.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: August 11, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Kenichi Hidaka, Yoshitaka Kubota
  • Patent number: 9070459
    Abstract: Apparatus, systems, and methods may operate to receive an external erase command at a control circuit coupled to an erasable memory array located on a substrate. A global select gate voltage may thereafter be enabled for application to wordline transistors coupled to the erasable memory array after a voltage applied to the substrate has reached a preselected initiation voltage level between about zero volts and an ultimate erase voltage.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: June 30, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Xiaojun Yu, Jin-man Han, Aaron Yip
  • Patent number: 9047960
    Abstract: An apparatus includes a storage transistor. The storage transistor includes a floating gate configured to store electrical charge and a control gate. The floating gate is coupled to the control gate via capacitive coupling. The floating gate and the control gate are metal. The apparatus also includes an access transistor coupled to the storage transistor. A gate of the access transistor is coupled to a word line. The storage transistor and the access transistor are serially coupled between a bit line and a source line.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: June 2, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Xia Li, Bin Yang, Zhongze Wang
  • Patent number: 9036421
    Abstract: Strings of memory cells having a string select gate configured to selectively couple ends of a string to a data line and a source line concurrently, memory devices incorporating such strings and methods for accessing and forming such strings are provided. For example, non-volatile memory devices are disclosed that utilize vertical structure NAND strings of serially-connected non-volatile memory cells. One such string including two or more serially-connected non-volatile memory cells where each end of the string shares a string select gate with the other end of the string is disclosed.
    Type: Grant
    Filed: February 12, 2014
    Date of Patent: May 19, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Zengtao Liu
  • Patent number: 9030877
    Abstract: In an embodiment of the invention, a memory cell arrangement includes a substrate and at least one memory cell including a charge storing memory cell structure and a select structure. The memory cell arrangement further includes a first doping well, a second doping well and a third doping well arranged within the substrate, wherein the charge storing memory cell structure is arranged in or above the first doping well, the first doping well is arranged within the second doping well, and the second doping well is arranged within the third doping well. The memory cell arrangement further includes a control circuit coupled with the memory cell and configured to control the memory cell such that the charge storing memory cell structure is programmed or erased by charging or discharging the charge storing memory cell structure via at least the first doping well.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: May 12, 2015
    Assignee: Infineon Technologies AG
    Inventors: Robert Strenz, Wolfram Langheinrich, Mayk Roehrich, Robert Wiesner
  • Patent number: 9013924
    Abstract: An operating method of a semiconductor device includes precharging bit lines corresponding to selected memory cells, supplying a first verify voltage to a word line coupled to the selected memory cells and outputting programming states of the selected memory cells to the bit lines during a first time period, sensing potentials of the bit lines that have the programming states of the selected memory cells outputted to the bit lines during the first time period, supplying a first target voltage higher than the first verify voltage to the word line and outputting programming states of the selected memory cells to the bit lines during a second time period shorter than the first time period, and sensing potentials of the bit lines that have the programming states of the selected memory cells outputted to the bit lines during the second time period.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: April 21, 2015
    Assignee: SK Hynix Inc.
    Inventor: Chang Won Yang
  • Patent number: 9007833
    Abstract: Disclosed is a 2-transistor flash memory that includes a memory cell array, a row driver, a read/write circuit, a charge pump generating a high voltage, and control logic configured to transfer the high voltage to the row driver, the read/write circuit, and the memory cell array. If programming, the row driver and the read/write circuit apply voltages such that a control gate of a cell transistor in an unselected memory cell on a different row from a selected memory cell is floated.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: April 14, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang Min Jeon, Weonho Park, Byoungho Kim
  • Patent number: 8995199
    Abstract: An instruction to write to a location in the Flash memory is received. It is determining if the Flash memory exposes a level placement setting associated with defining what voltage range corresponds to what level. In the event it is determined that the Flash memory exposes a level placement setting, an accurate coarse write is performed on the location, including by configuring the level placement setting to be a first value, and after the accurate coarse write is performed on the location, a fine write is performed on the location, including by configuring the level placement setting to be a second value, in response to receiving the instruction.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: March 31, 2015
    Assignee: SK hynix memory solutions inc.
    Inventors: Meng-Kun Lee, Yingquan Wu
  • Patent number: 8995203
    Abstract: The present inventive concept provides a driving method of memory controller controlling nonvolatile memory device using variable resistive element. The memory controller may control a plurality of first memory devices and a second memory device. A number of write drivers in the second memory device may be driven when a number of first memory devices among the plurality of first memory devices are used. A different number of write drivers in the second memory device may be driven when a different number of first memory devices among the plurality of first memory devices are used.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: March 31, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Hoon Oh, Du-Eung Kim, Woo-Yeong Cho
  • Patent number: 8988104
    Abstract: Innovative Non-Volatile Look-Up-Table (NV-LUT) has been constructed by Single Gate Logic Non-Volatile Memory (SGLNVM) devices processed with the standard CMOS logic process. One of a pair of complementary SGLNVM devices is always programmed to the high threshold voltage state and the other remains in the low threshold voltage state. By applying digital voltage rail (VDD and VSS) to the input nodes of the pair of complementary SGLNVM devices, the output node of the pair of complementary SGLNVM devices outputs digital signals according to its configuration. The NV-LUT outputs digital signals from a plurality of pairs of complementary SGLNVM devices through a digital switching multiplexer. The NV-LUT is a good substitution for SRAM based LUT commonly used in Field Programmable Gate Array (FPGA).
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: March 24, 2015
    Assignee: FlashSilicon Incorporation
    Inventor: Lee Wang
  • Patent number: 8982633
    Abstract: Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a first region connected to a bit line extending in a first orientation and a second region connected to a source line extending in a second orientation. The direct injection semiconductor memory device may also include a body region spaced apart from and capacitively coupled to a word line extending in the second orientation, wherein the body region is electrically floating and disposed between the first region and the second region. The direct injection semiconductor memory device may further include a third region connected to a carrier injection line extending in the second orientation, wherein the first region, the second region, the body region, and the third region are disposed in sequential contiguous relationship.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: March 17, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Srinivasa R. Banna, Michael A. Van Buskirk
  • Patent number: 8976594
    Abstract: Apparatus and methods are disclosed, including a method that raises an electrical potential of a plurality of access lines to a raised electrical potential, where each access line is associated with a respective charge storage device of a string of charge storage devices. The electrical potential of a selected one of the access lines is lowered, and a data state of the charge storage device associated with the selected access line is sensed while the electrical potential of the selected access line is being lowered. Additional apparatus and methods are described.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: March 10, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Toru Tanzawa
  • Patent number: 8953378
    Abstract: A method for programming a split gate memory cell includes performing a first programming of the split gate memory cell in a first programming cycle of the split gate memory cell; and, subsequent to the performing the first programming of the split gate memory cell, performing a second programming of the split gate memory cell in the first programming cycle, wherein the first programming is characterized as one of source-side injection (SSI) programming and channel-initiated secondary electron (CHISEL) programming, and the second programming is characterized as the other of SSI programming and CHISEL programming.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: February 10, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Cheong Min Hong, Sung-Taeg Kang
  • Patent number: 8946809
    Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor memory device. The method includes forming a first stopper film forming a lower gate layer, making a recess in the lower gate layer, filling a sacrificial film into the recess, forming a second stopper film, making an opening in the second stopper film, forming a stacked body. The stacked body includes electrode films and insulating films. The method includes, making a slit in the stacked body, making a hole in the stacked body, removing the sacrificial film via the hole, forming a memory film including a charge storage film. The method includes forming a channel body on a side wall of the memory film. An etching rate of the first stopper film and the second stopper film is lower than an etching rate of the electrode films and the insulating films.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: February 3, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuhide Takamura, Ryota Katsumata, Masaru Kidoh, Yoshihiro Uozumi, Daigo Ichinose, Toru Matsuda
  • Patent number: 8947938
    Abstract: A memory device includes an N-channel transistor and a P-channel transistor. A word line is electrically connected to a drain terminal of the N-channel transistor, and a source terminal of the P-channel transistor. A first bit line is electrically connected to a source terminal of the N-channel transistor. A second bit line is electrically connected to a drain terminal of the P-channel transistor. Gate terminals of the N-channel transistor and the P-channel transistor are electrically connected and floating.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: February 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Te-Liang Lee, Chin-Yuan Ko, Ming-Yih Wang
  • Patent number: 8941470
    Abstract: In embodiments of the present invention improved capabilities are described for a Radio Frequency identification (RFID) tag that includes an OTP-based hardened memory system for the RFID tag.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: January 27, 2015
    Assignee: Tego Inc.
    Inventors: Timothy P. Butler, Javier Berrios, Steve Beckhardt, Robert W. Hamlin, Larry Moore, David Puleston, Leonid Mats
  • Patent number: 8929142
    Abstract: Programming accuracy is increased for select gate transistors and memory cells by using a dynamic verify voltage which increases from an initial level to a final level during a programming operation. Faster-programming transistors are locked out from programming before slower-programming transistors, but experience program disturb which increases their threshold voltage to a common level with the slower-programming transistors at the conclusion of the programming operation. For programming of memory cells to different target data states, an offset between the initial and final verify levels can be different for each data state. In one approach, the offset is greater for lower target data states. The increases in the dynamic verify voltage can be progressively smaller with each subsequent program-verify iteration of the programming operation. The start of the increase can be adapted to the programming progress or can be at a predetermined program-verify iteration.
    Type: Grant
    Filed: February 5, 2013
    Date of Patent: January 6, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Yingda Dong, Cynthia Hsu, Masaaki Higashitani, Ken Oowada
  • Patent number: 8923056
    Abstract: A non-volatile memory device includes a memory cell block including a plurality of memory cells, a plurality of page buffer groups including a plurality of page buffers coupled to bit lines of the memory cell block, a pass/fail check circuit coupled to the plurality of page buffers and configured to perform a pass/fail check operation of comparing a total amount of current varying according to verify data sensed from the memory cells and stored in the page buffers with an amount of reference current corresponding to the number of allowed bits, and a control circuit configured to control the pass/fail check circuit by stopping, when a fail signal is generated during the pass/fail check operation currently being performed on a page buffer group among the plurality of page buffer groups, the pass/fail check operation on the remaining page buffer groups.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: December 30, 2014
    Assignee: SK Hynix Inc.
    Inventor: Min Su Kim
  • Patent number: 8923047
    Abstract: A semiconductor memory device includes memory strings each of which includes a drain select transistor, memory cells, and a source select transistor, a first bit line coupled to drain select transistors of first group memory strings among the memory strings, a second bit line coupled to drain select transistors of second group memory strings among the memory strings, and source lines coupled to source select transistors of the memory strings; and peripheral circuits configured to turn on source select transistors of non-selected memory strings coupled to source lines to which a precharge voltage is supplied or turn on drain select transistors of non-selected memory strings coupled to bit lines to which a program inhibition voltage is supplied in order to precharge channel regions of non-selected memory strings before a program voltage is supplied to a memory cell included in a selected memory string among the memory strings.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: December 30, 2014
    Assignee: SK Hynix Inc.
    Inventor: Sang Moo Choi
  • Patent number: 8923070
    Abstract: According to one embodiment, a one-time programmable (OTP) device comprises a memory FinFET in parallel with a sensing FinFET. The memory FinFET and the sensing FinFET share a common source region, a common drain region, and a common channel region. The memory FinFET is programmed by having a ruptured gate dielectric, resulting in the sensing FinFET having an altered threshold voltage and an altered drain current. A method for utilizing such an OTP device comprises applying a programming voltage for rupturing the gate dielectric of the memory FinFET thereby achieving a programmed state of the memory FinFET, and detecting by the sensing FinFET the altered threshold voltage and the altered drain current due to the programmed state of the memory FinFET.
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: December 30, 2014
    Assignee: Broadcom Corporation
    Inventors: Wei Xia, Xiangdong Chen