Abstract: Provided herein is a memory device for performing a program operation on memory cells. The memory device include a plurality of memory cells configured to store data, a voltage generator configured to apply program voltages to a word line coupled to the plurality of memory cells during a program operation in which the plurality of memory cells are programmed to a plurality of program states, a cell speed determiner configured to determine a program speed of the plurality of memory cells depending on a number of pulses for the program voltages applied to the word line while the program operation is being performed, and a program manager configured to change a condition for remaining program operations depending on the program speed determined by the cell speed determiner.

Abstract: A thin-film storage transistor formed in a memory array above a planar surface of a semiconductor substrate, includes (a) first and second planar dielectric layers, each being substantially parallel the planar surface of the semiconductor substrate; (b) a first semiconductor layer of a first conductivity having an opening therein; (c) second and third semiconductor layers of a second conductivity type opposite the first conductivity type, located on two opposite sides of the first semiconductor layer; (d) a charge-storage layer provided in the opening adjacent and in contact with the first semiconductor layer; and (e) a first conductor provided in the opening separated from the first semiconductor layer by the charge storage layer, wherein the first, second and third semiconductor layers are each provided as a planar layer of materials between the first and second dielectric layers.

Abstract: According to one embodiment, a semiconductor memory device includes: a first memory cell; a second memory cell; a first word line; a second word line; and a first bit line. The device is configured to execute a first operation, a second operation, and a third operation to write data into the first memory cell. In the first operation, a first voltage is applied to the second word line. In the second operation, after the first operation, a second voltage higher than the first voltage is applied to the second word line. In the third operation, after the second operation, a third voltage higher than the second voltage is applied to the first word line, and a fourth voltage lower than both the second voltage and the third voltage is applied to the second word line.

Abstract: Systems, apparatuses, and methods of operating memory systems are described. Processing-in-memory capable memory devices are also described, and methods of performing fused-multiply-add operations within the same. Bit positions of bits stored at one or more portions of one or more memory arrays, may be accessed via data lines by activating the same or different access lines. A sensing circuit operatively coupled to a data line may be temporarily formed and measured to determine a state (e.g., a count of the number of bits that are a logic “1”) of accessed bit positions of a data line, and state information may be used to determine a computational result.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cells, a word line connected to the plurality of memory cells, a plurality of bit lines connected respectively to the plurality of memory cells, a sense amplifier connected to the plurality of bit lines, and a controller configured to execute a write operation in a plurality of program loops each including a program operation and a verify operation. The sense amplifier is configured to apply a first voltage, a second voltage higher than the first voltage, a third voltage higher than the second voltage, and a fourth voltage higher than the third voltage to first, second, third, and fourth bit lines of the plurality of bit lines, respectively, while a program voltage is applied to the word line in the program operation.

Abstract: A memory device includes a plurality of planes. A method of programming the memory device includes applying a first program pulse to one or more memory cells of a first plane of the plurality of planes, verifying whether each one of the memory cells reaches a predetermined program state, and in response to a preset number of the memory cells in the first plane failing to reach the predetermined program state after the memory cells being verified for a predetermined number of times, bypassing the first plane when applying a second program pulse after the first program pulse.

Abstract: A storage device is provided that applies pulsed biasing during power-up or read recovery. The storage device includes a memory and a controller. The memory includes a block having a word line and cells coupled to the word line. The controller applies a voltage pulse to the word line during power-up or in response to a read error. The voltage pulse may include an amplitude and a pulse width that are each a function of a number of P/E cycles of the block. The controller may also perform pulsed biasing during both power-up and read recovery by applying one or more first voltage pulses to the word line during power-up and one or more second voltage pulses to the word line in response to a read error. As a result, lower bit error rates due to wider Vt margins may occur and system power may be saved over constant biasing.

Abstract: A method is described that includes determining a number of program and erase cycles associated with a block of pages of a memory device and determining a preprogram voltage based on the number of program and erase cycles to apply to the block of pages prior to an erase operation. The method further includes applying the preprogram voltage to the block of pages and performing an erase operation on the block of pages following application of the preprogram voltage to the block of pages.

Abstract: Provided herein may be a memory device and a method of operating the memory device. The memory device includes an operation code generator configured to generate a program code and a verify code in response to a program control code and to output an operation code using the program code and the verify code, a verify counter configured to store a count value acquired by counting the number of verify operations that are performed depending on the verify code, a verify determiner configured to compare the count value with a reference value depending on the result of the verify operation and to generate the program control code to change a step voltage for raising a program voltage depending on the comparison result, and a voltage generator configured to generate the program voltage and a verify voltage depending on the operation code.

Abstract: This disclosure proposes a method to save P/E cycling information inside NAND by using 2-byte column in programmable selective devices (e.g., SGD). The proposed method is a one-way programming method, and does not perform an erase operation within the 2-byte column. The proposed methods described herein can reduce the burden of relying upon controller SRAM/DRAM. Additionally, by storing the P/E cycling information in NAND, the P/E cycling is not lost due to a power loss event. At least one application advantageous for using NAND to store P/E cycling information includes wear leveling.

Abstract: Multi-gate NOR flash thin-film transistor (TFT) string arrays are organized as three dimensional stacks of active strips. Each active strip includes a shared source sublayer and a shared drain sublayer that is connected to substrate circuits. Data storage in the active strip is provided by charge-storage elements between the active strip and a multiplicity of control gates provided by adjacent local word-lines. The parasitic capacitance of each active strip is used to eliminate hard-wire ground connection to the shared source making it a semi-floating, or virtual source. Pre-charge voltages temporarily supplied from the substrate through a single port per active strip provide the appropriate voltages on the source and drain required during read, program, program-inhibit and erase operations. TFTs on multiple active strips can be pre-charged separately and then read, programmed or erased together in a massively parallel operation.

Abstract: Devices and techniques temperature sensitive NAND programming are disclosed herein. A device controller can receive a command to write data to a component of the device. A temperature can be obtained in response to the command, and the temperature can be combined with a temperature compensation value to calculate a verification level. The command can then be executed in accordance with the verification level.

Abstract: A method of operating a memory system includes a first programming loop, which includes applying a first programming voltage to a control gate of a selected word line and applying a first bitline voltage to a bitline coupled to a first memory cell that is being programmed to a first data state and to a different bitline coupled to a second memory cell that is being programmed to a second data state. In a second programming loop, a second bitline voltage is applied to the bitline coupled to the first memory cell, and a third bitline voltage is applied to the bitline coupled to the second memory cell. The second bitline voltage is greater than the first bitline voltage to reduce a programming speed of the first bitline voltage to increase a programming speed of the second memory cell.

Abstract: In a method for reading a memory device including a first memory cell string, in a pre-verify stage, a first verify voltage is applied on a gate terminal of a selected memory cell of the first memory cell string, where the selected memory cell is programmed and arranged between a first adjacent memory cell and a second adjacent memory cell. A first bias voltage is applied on a gate terminal of at least one memory cell of the first memory cell string that is not programmed. In a verify stage, a second verify voltage is applied on the gate terminal of the selected memory cell of the first memory cell string. A second bias voltage is applied on the gate terminal of the at least one memory cell of the first memory cell string that is not programmed, where the second bias voltage is smaller than the first bias voltage.

Abstract: A method is described that includes determining a number of program and erase cycles associated with a block of pages of a memory device and determining a preprogram voltage based on the number of program and erase cycles to apply to the block of pages prior to an erase operation. The method further includes applying the preprogram voltage to the block of pages and performing an erase operation on the block of pages following application of the preprogram voltage to the block of pages.

Abstract: A method of operating a memory controller, the method including performing a state shaping operation on received data based on state shaping information in response to a write request, the received data and the write request being received from a host, the state shaping information representing a memory cell characteristic corresponding to a memory cell group on which the received data is to be programmed, and the state shaping information being received from a memory device, and transmitting transformation data to the memory device, the transformation data being generated through the state shaping operation.

Abstract: A program method of a nonvolatile memory device that performs a plurality of program loops is provided. At least one of the plurality of program loops includes dividing a channel of a selected cell string into a first side channel and a second side channel during a first interval and a second interval, turning off a string selection transistor of the selected cell string by applying a string select line voltage of a first level during the first interval, and boosting a first voltage of the first side channel and a second voltage of the second side channel, and turning on the string selection transistor by applying the string select line voltage of a second level different from the first level during the second interval, and performing a hot carrier injection (HCI) program operation on a selected memory cell corresponding to the first side channel or the second side channel.

Abstract: Apparatus and methods are described to program memory cells and verify stored values programmed into the cells. The next stage in stored memory can be moved to the current verification iteration when certain conditions are met. Verification can include counting bits that exceed a voltage value for a stage being verified to produce a bit count number and determining if the bit count number for the stage being verified meets a threshold value. If the bit count number does not meet the threshold, the verification process can continue with a current verify iteration and thereafter move to a next verify iteration. If the bit count number does meet the threshold, the process can add a next stage to the current verify iteration and thereafter move to a next verify iteration.

Abstract: According to one embodiment, the semiconductor memory medium includes a first memory cell, a first word line coupled to the first memory cell, and a row decoder coupled to the first word line. A write operation is executed multiple times on the first memory cell within a first period from after an execution of an erase operation to an execution of a next erase operation. The write operation includes at least one of program loops each including a program operation and a verify operation. In the verify operation, the row decoder applies a verify voltage to the first word line. The verify voltage is set in accordance with a number of executed write operations on the first memory cell within the first period.

Abstract: A method for programming a non-volatile memory device is provided. The method comprises applying a program word line voltage with a voltage level changed stepwise to a selected word line connected to a plurality of memory cells, and applying a program bit line voltage to a first bit line of a plurality of bit lines connected to a plurality of first memory cells, while the program word line voltage is applied to the selected word line. The program bit line voltage transitions from a first voltage level to one of a program inhibit voltage level, a program voltage level, and a second voltage level. The first and second voltage levels are between the program inhibit voltage level and program voltage level.

Abstract: A memory device includes a memory array comprising a plurality of wordlines and a regulator circuit selectively coupled to the plurality of wordlines, wherein the regulator circuit is configured to perform a detection routine to sample a load current from a selected wordline of the plurality of wordlines and generate a measured output voltage, wherein the measured output voltage modulates with respect to the load current. The memory device further includes a comparator circuit coupled to the regulator circuit, wherein the comparator circuit is configured to generate a comparison result based on a difference between the measured output voltage and a reference voltage and a local media controller coupled to the comparator circuit, wherein the local media controller is configured to identify a presence of a defect on the selected wordline in response to the comparison result satisfying a threshold condition.

Abstract: An embodiment non-volatile memory device includes an array of memory cells, coupled to word lines, and a row decoder including a pull-down stage and a pull-up stage, which includes, for each word line: a corresponding control circuit, which generates a corresponding control signal; and a corresponding pull-up switch circuit, which is controlled via the control signal so as to couple/decouple the word line to/from the supply. The control circuit includes: a current mirror, which injects a current into an internal node; and a series circuit, which couples/decouples the corresponding internal node to/from ground, on the basis of selection/deselection of the corresponding word line so as to cause a decrease/increase in a voltage on the corresponding internal node. Each control signal is a function of the voltage on the corresponding internal node.

Abstract: A memory device may include: memory cells each having any one of first and second programmed states as a target programmed state; a peripheral circuit configured to perform a program operation so that each memory cell has a threshold voltage corresponding to the target programmed state; and a control circuit configured to control the peripheral circuit. The control circuit may include a program operation controller configured to control the peripheral circuit so that, during the program operation, an intermediate program operation is performed on the memory cells using an intermediate verify voltage, an additional program operation is performed on memory cells each having the second programmed state as a target programmed state if an intermediate verify operation passes, and a final program operation is performed on the memory cells such that each memory cell has a threshold voltage corresponding to the target programmed state.

Abstract: The present technology relates to an electronic device. More specifically, the present technology relates to a storage device and a method of operating the same. A memory device according to an embodiment includes a memory cell array including a plurality of memory cells, a peripheral circuit configured to perform a program operation, a program verifier configured to calculate difference values, each of which is between a first pass loop count and a second pass loop count of a respective one of program states, when the program operation is completed, and output a pass status or a fail status according to whether at least one of the difference values exceeds a reference value.

Abstract: An example apparatus includes a controller and a memory device. The memory device is configured to maintain, internal to the memory device, a status of a number of open blocks in the memory device. The status can include a programming operation being initiated in the respective number of open blocks. Responsive to receipt of, from the controller, a request to direct initiation of the programming operation to a word line, determine a group of memory cells associated with the word line that programs first relative to other groups of memory cells associated with the word line and maintain, included in the status of an open block, a voltage at which the group of memory cells is the first group to program.

Abstract: A semiconductor storage device includes a bit line driver, and a control circuit configured to be able to execute a writing sequence for repeating at least one loop including a program operation for writing data into at least one of the plurality of memory cells and a verify operation for verifying the data a plurality of times while increasing a program voltage by a step-up voltage. The bit line driver can obtain a number of memory cells into which writing is completed or a number of memory cells into which writing is insufficient for each of the at least two consecutive loops from a result of the verify operation, and the control circuit can determine the step-up voltage in the subsequent loop based on a result obtained by the bit line driver.

Abstract: A storage device for verifying whether memory cells have been programmed. The storage device may be configured to use a verification technique, that is part of a set of verification techniques, to verify data states of a set of memory cells of a selected word line. The one or more verification techniques may be utilized based on an iteration of the verify operation that is to be performed. The storage device may be further configured to perform, using the verification technique, a next iteration of the program-verify operation to verify whether one or more memory cells have been programmed. Using the verification technique and performing the next-iteration of the program-verify operation are to be repeated until the set of memory cells have been verified.

Abstract: A memory device including at least one dummy word line over a substrate; a plurality of word lines over the dummy word line; and a plurality of vertical holes extending through the at least one dummy word line and the plurality of word lines in a direction perpendicular to the substrate and classified into channel holes and dummy holes, each of the channel holes being connected to a bit line. The method including performing an erase operation on dummy cells formed as the dummy word line and the dummy holes; verifying the erase operation; and performing a program operation on at least one of the dummy cells such that the at least one dummy cell has a higher threshold voltage than main cells formed as the dummy word line and the channel holes.

Abstract: According to one embodiment, the semiconductor memory medium includes a first memory cell, a first word line coupled to the first memory cell, and a row decoder coupled to the first word line. A write operation is executed multiple times on the first memory cell within a first period from after an execution of an erase operation to an execution of a next erase operation. The write operation includes at least one of program loops each including a program operation and a verify operation. In the verify operation, the row decoder applies a verify voltage to the first word line. The verify voltage is set in accordance with a number of executed write operations on the first memory cell within the first period.

Abstract: A method of operating a semiconductor memory device includes dummy-programming selected memory cells representing all the memory cells to be programmed for a programming operation. The method also includes determining as a first group of memory cells those selected memory cells having threshold voltages less than or equal to a reference threshold voltage and determining as a second group of memory cells those selected memory cells having threshold voltages greater than the reference threshold voltage. The method further includes programming the selected memory cells by applying a first bit line voltage to the memory cells of the first group, applying a second bit line voltage different from the first bit line voltage to the memory cells of the second group, and applying a same program pulse to the memory cells of the first and second groups.

Abstract: A program effective time (PET) for programming at least a portion of a plurality of memory cells based on one or more program step characteristics is determined. The determined PET and a target PET is compared. In response to the determined PET being different than the target PET, the one or more program step characteristics is adjusted to adjust the determined PET to the target PET.

Abstract: A method for error correction of logical pages of an erase block of a solid state drive (SSD) memory, the method may include determining an erase block score of the erase block, wherein the calculating is based on a program erase (PE) cycle of the erase block and one or more erase block error correction parameter; determining, based on (a) the erase block score, and (b) a mapping between the erase block score and one or more page error correction parameters for each page type out of multiple pages types, the one or more page error correction parameter for each page type; and allocating, within each page of the erase block, an overprovisioning space and an error correction space, based on at least one page error correction parameter related to a page type of the page.

Abstract: Provided are a memory controller and memory system having an improved threshold voltage distribution characteristic and an operating method of the memory system. As a write request of data with respect to a first block is received, an erase program interval (EPI) is determined denoting a time period elapsed after erasure of the first block. When the determined EPI is equal to or less than a reference time, data is programmed to the first block based on a first operation condition selected from among a plurality of operation conditions. when the When the determined EPI is greater than the reference time, the data is programmed to the first block based on a second operation condition selected from among the plurality of operation conditions.

Abstract: A program method of a nonvolatile memory device including a plurality of memory cells, each storing at least two bits of data, includes performing a first program operation based on a plurality of program voltages having a first pulse width to program first page data into selected memory cells connected to a selected word line among the plurality of memory cells; and performing a second program operation based on a plurality of program voltages having a second pulse width different from the first pulse width to program second page data into the selected memory cells in which the first page data is programmed.

Abstract: An operating method of a non-volatile memory includes: generating a first programming pulse with a first time period to a target memory cell in a memory array; reading and verifying whether a threshold voltage of the target memory cell reaches a target voltage level; and generating a second programming pulse with a second time period to the target memory cell when the threshold voltage of the target memory cell does not reach the target voltage level, wherein the second time period is longer than the first time period.

Abstract: A semiconductor device includes a source layer; a plurality of channel structures; a plurality of gate electrodes; and a common source line. At least one of the plurality of gate electrodes provides a GIDL line. For an erasing operation, an erasing voltage applied to the common source line reaches a target voltage, and, after the erasing voltage reaches the target voltage, a step increment voltage is applied to the erasing voltage, such that the erasing voltage has a voltage level higher than a voltage level of the target voltage. After the step increment voltage has been applied for a desired time period, the voltage level of the erasing voltage is decreased to the target voltage level for the remainder of the erasing operation.

Abstract: A memory device includes a channel element, a memory element, and an electrode element. The channel element includes a first channel portion, a second channel portion, and a middle channel portion between the first channel portion and the second channel portion. The first channel portion has a first sidewall channel surface and a second sidewall channel surface opposing to the first sidewall channel surface. The middle channel portion has a third sidewall channel surface and a fourth sidewall channel surface opposing to the third sidewall channel surface. The first sidewall channel surface and the second sidewall channel surface of the first channel portion are outside the third sidewall channel surface and the fourth sidewall channel surface of the middle channel portion respectively. A memory cell is defined in the memory element between the channel element and the electrode element.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. The alternating stack includes a first region in which all layers of the alternating stack are present and a second region in which at least a topmost one of the electrically conductive layers is absent. First memory opening fill structures extend through the first region of the alternating stack, and second memory opening fill structures extend through the second region of the alternating stack. The first memory opening fill structures have a greater height than the second memory opening fill structures. Pocket doping regions extending over a respective subset of topmost electrically conductive layers for the memory opening fill structures can be formed to provide higher threshold voltages and to enable selective activation of vertical semiconductor channels connected a same bit line.

Abstract: A method of concurrently programming a memory. Various methods include: applying a non-negative voltage on a first bit line coupled to a first memory cell; applying a negative voltage on a second bit line coupled to a second memory cell, where the negative voltage is generated using triple-well technology; then applying a programming pulse to the first and second memory cells concurrently; and in response, programming the first and second memory cells to different states. The methods also include applying a quick pass write operation to the first and second memory cells, by: applying a quick pass write voltage to the first bit line coupled to the first memory cell, where the quick pass write voltage is higher than the non-negative voltage; applying a negative quick pass write voltage to the second bit line coupled to the first memory cell, where the negative quick pass write voltage is generated using triple-well technology.

Abstract: Provided herein may be a memory device and a method of operating the memory device. The memory device includes a memory cell, a page buffer coupled to the memory cell through a bit line and configured to perform a read operation of sensing data stored in the memory cell, wherein the page buffer includes a data storage configured to store data sensed from the memory cell, the read operation includes a precharge period during which a precharge voltage is applied to the bit line, an evaluation period during which a state of the memory cell is incorporated into a voltage of the bit line, and a data storage period during which the data sensed through the bit line is stored in the data storage, and the data storage is initialized during the evaluation period.

Abstract: A memory device that has been programmed to store a single bit or multiple bits can perform a determination of a number of threshold voltages in one or more threshold voltage level regions. Based on the number of threshold voltages meeting or exceeding a threshold level, a page of bits can be read and if the bit error rate of the page of bits is below a threshold rate, the page of bits can be stored in the cells together with other bits stored in the cells and a provided additional page of bits. However, if the bit error rate of the page of bits is at or above the threshold rate, then the bit or bits stored in the cells can be error corrected and stored together with a provided additional page of bits.

Abstract: A memory device includes a memory cell array including a plurality of memory cells; a peripheral circuit configured to perform a program operation on selected memory cells among the plurality of memory cells; a program pulse information generator configured to generate program pulse information indicating whether a number of program pulses applied to the selected memory cells during the program operation has exceeded a reference value; and a status register configured to store status information and the program pulse information, wherein the memory device provides the status information and the program pulse information to an external controller in response to a command from the external controller.

Abstract: A method for performing a physical unclonable function generated by a non-volatile memory write delay difference includes a resetting step, a writing step, a detecting step, a terminating step and a write-back operating step. The resetting step includes resetting two non-volatile memory cells controlled by a bit line and a bit line bar, respectively. The writing step includes performing a write operation on each of the two non-volatile memory cells. The detecting step includes detecting a voltage drop of each of the bit line and the bit line bar, and comparing the voltage drop and a predetermined voltage difference value to generate a comparison flag. The terminating step includes terminating the write operation on one of the two non-volatile memory cells according to the comparison flag. The write-back operating step includes performing a write-back operation on another of the two non-volatile memory cells.

Abstract: A driving method of a nonvolatile memory device including multiple memory planes includes following operations: precharging at least one word line and at least one bit line of a first memory plane; if the at least one word line and the at least one bit line of the first memory plane have been precharged for a first time length or to respective voltage thresholds, precharging at least one word line and at least one bit line of a second memory plane; conducting a first data operation to at least one memory cell of the first memory plane disposed at intersections of the at least one word line and the at least one bit line thereof; conducting a second data operation to at least one memory cell of the second memory plane disposed at intersections of the at least one word line and the at least one bit line thereof.

Abstract: Methods of operating a memory include applying a programming pulse having a particular voltage level to a selected access line connected to a plurality of memory cells selected for programming during a programming operation, concurrently enabling for programming each memory cell of the plurality of memory cells selected for programming while applying the programming pulse, applying a subsequent programming pulse having a plurality of different voltage levels to the selected access line, and, for each group of memory cells of a plurality of groups of memory cells of the plurality of memory cells selected for programming, enabling that group of memory cells for programming while the subsequent programming pulse has a corresponding voltage level of the plurality of different voltage levels.

Abstract: Techniques are provided for optimizing a program operation in a memory device to compensate for program speed variations due to block oxide thinning. In one approach, during a program operation, a program voltage which indicates program speed is acquired from sub-blocks with the highest and lowest program speeds. An initial program voltage for intermediate sub-blocks can be determined based on the acquired program voltages and the positions of the intermediate sub-blocks. The technique can accommodate a loss of one or both acquired program voltages if the programming is interrupted. In another approach, a program voltage which indicates program speed is acquired from one sub-block, and for a later-programmed sub-block, an appropriate offset is located from a table and summed with the acquired program voltage to determine an optimum initial program voltage.

Abstract: Provided herein may be a semiconductor memory device and a method of operating the semiconductor memory device to program a selected physical page of the semiconductor memory device. The method may include performing a plurality of program loops. Each of the program loops may include: applying a bit line voltage based on data input to a page buffer of the semiconductor memory device; applying a two-step program pulse to a word line coupled to the selected physical page; performing a program verify operation on the selected physical page using a double verify scheme; and determining a bit line voltage to be applied in a subsequent program loop based on a result of the program verify operation.

Abstract: An apparatus includes a programming circuit configured to supply a program pulse to increase a threshold voltage of a memory cell. The apparatus also includes a sensing circuit configured to determine that the threshold voltage of the memory cell satisfies a trigger threshold voltage in response to the program pulse. The apparatus further includes a damping circuit configured to increase a voltage of a bit line connected to the memory cell after initiation of and during a second program pulse in response to the threshold voltage of the memory cell satisfying the trigger threshold voltage, the second program pulse being sent by the programming circuit.

Abstract: A memory data management method includes the following steps reading a plurality of data of a plurality of memory cells of a memory block; determining whether error bits of the data exceed an error correction code (ECC) threshold; if the error bits of the data exceed the ECC threshold, a programming process being executed to increase a first threshold voltage of a first state data of the data for exceeding a first threshold, to increase a second threshold voltage of a second state data of the data for exceeding a second threshold, and to increase a third threshold voltage of a third state data of the data for exceeding a third threshold.

Abstract: Memory devices with controlled wordline ramp rates and associated systems and methods are disclosed herein. In one embodiment, a memory device includes at least one voltage regulator and a plurality of wordlines. The memory device is configured, during a programming operation of the memory region, to ramp a selected wordline to a desired programming voltage while ramping one or more adjacent, unselected wordlines electrically coupled to the selected wordline to desired inhibit voltage(s) using the at least one voltage regulator. In some embodiments, the memory device ramps the selected wordline and the one or more adjacent, unselected wordlines such that the one or more adjacent, unselected wordlines reach the desired inhibit voltage(s) when the selected wordline reaches the desired programming voltage. In these and other embodiments, the memory device ramps the selected wordline to the desired programming voltage without floating the selected wordline.