Multiple Pulses (e.g., Ramp) Patents (Class 365/185.19)
  • Patent number: 11114165
    Abstract: A semiconductor device includes a source layer; a plurality of channel structures; a plurality of gate electrodes; and a common source line. At least one of the plurality of gate electrodes provides a GIDL line. For an erasing operation, an erasing voltage applied to the common source line reaches a target voltage, and, after the erasing voltage reaches the target voltage, a step increment voltage is applied to the erasing voltage, such that the erasing voltage has a voltage level higher than a voltage level of the target voltage. After the step increment voltage has been applied for a desired time period, the voltage level of the erasing voltage is decreased to the target voltage level for the remainder of the erasing operation.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: September 7, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Doohee Hwang, Taehun Kim, Minkyung Bae, Myunghun Woo, Bongyong Lee
  • Patent number: 11094715
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. The alternating stack includes a first region in which all layers of the alternating stack are present and a second region in which at least a topmost one of the electrically conductive layers is absent. First memory opening fill structures extend through the first region of the alternating stack, and second memory opening fill structures extend through the second region of the alternating stack. The first memory opening fill structures have a greater height than the second memory opening fill structures. Pocket doping regions extending over a respective subset of topmost electrically conductive layers for the memory opening fill structures can be formed to provide higher threshold voltages and to enable selective activation of vertical semiconductor channels connected a same bit line.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: August 17, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Zhixin Cui, Masatoshi Nishikawa, Ken Oowada
  • Patent number: 11094711
    Abstract: A memory device includes a channel element, a memory element, and an electrode element. The channel element includes a first channel portion, a second channel portion, and a middle channel portion between the first channel portion and the second channel portion. The first channel portion has a first sidewall channel surface and a second sidewall channel surface opposing to the first sidewall channel surface. The middle channel portion has a third sidewall channel surface and a fourth sidewall channel surface opposing to the third sidewall channel surface. The first sidewall channel surface and the second sidewall channel surface of the first channel portion are outside the third sidewall channel surface and the fourth sidewall channel surface of the middle channel portion respectively. A memory cell is defined in the memory element between the channel element and the electrode element.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: August 17, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Wei Jiang, Jia-Rong Chiou
  • Patent number: 11081184
    Abstract: A method of concurrently programming a memory. Various methods include: applying a non-negative voltage on a first bit line coupled to a first memory cell; applying a negative voltage on a second bit line coupled to a second memory cell, where the negative voltage is generated using triple-well technology; then applying a programming pulse to the first and second memory cells concurrently; and in response, programming the first and second memory cells to different states. The methods also include applying a quick pass write operation to the first and second memory cells, by: applying a quick pass write voltage to the first bit line coupled to the first memory cell, where the quick pass write voltage is higher than the non-negative voltage; applying a negative quick pass write voltage to the second bit line coupled to the first memory cell, where the negative quick pass write voltage is generated using triple-well technology.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: August 3, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Zhiping Zhang, Muhammad Masuduzzaman, Huai-Yuan Tseng, Dengtao Zhao, Deepanshu Dutta
  • Patent number: 11069396
    Abstract: Provided herein may be a memory device and a method of operating the memory device. The memory device includes a memory cell, a page buffer coupled to the memory cell through a bit line and configured to perform a read operation of sensing data stored in the memory cell, wherein the page buffer includes a data storage configured to store data sensed from the memory cell, the read operation includes a precharge period during which a precharge voltage is applied to the bit line, an evaluation period during which a state of the memory cell is incorporated into a voltage of the bit line, and a data storage period during which the data sensed through the bit line is stored in the data storage, and the data storage is initialized during the evaluation period.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: July 20, 2021
    Assignee: SK hynix Inc.
    Inventors: Hyung Jin Choi, Sung Mook Lim
  • Patent number: 11061757
    Abstract: A memory device includes a memory cell array including a plurality of memory cells; a peripheral circuit configured to perform a program operation on selected memory cells among the plurality of memory cells; a program pulse information generator configured to generate program pulse information indicating whether a number of program pulses applied to the selected memory cells during the program operation has exceeded a reference value; and a status register configured to store status information and the program pulse information, wherein the memory device provides the status information and the program pulse information to an external controller in response to a command from the external controller.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: July 13, 2021
    Assignee: SK hynix Inc.
    Inventor: Un Sang Lee
  • Patent number: 11061762
    Abstract: A memory device that has been programmed to store a single bit or multiple bits can perform a determination of a number of threshold voltages in one or more threshold voltage level regions. Based on the number of threshold voltages meeting or exceeding a threshold level, a page of bits can be read and if the bit error rate of the page of bits is below a threshold rate, the page of bits can be stored in the cells together with other bits stored in the cells and a provided additional page of bits. However, if the bit error rate of the page of bits is at or above the threshold rate, then the bit or bits stored in the cells can be error corrected and stored together with a provided additional page of bits.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: July 13, 2021
    Assignee: Intel Corporation
    Inventors: Naveen Prabhu Vittal Prabhu, Bharat M. Pathak, Aliasgar S. Madraswala, Yogesh B. Wakchaure, Violante Moschiano, Walter Di Francesco, Michele Incarnati, Antonino Giuseppe La Spina
  • Patent number: 11057224
    Abstract: A method for performing a physical unclonable function generated by a non-volatile memory write delay difference includes a resetting step, a writing step, a detecting step, a terminating step and a write-back operating step. The resetting step includes resetting two non-volatile memory cells controlled by a bit line and a bit line bar, respectively. The writing step includes performing a write operation on each of the two non-volatile memory cells. The detecting step includes detecting a voltage drop of each of the bit line and the bit line bar, and comparing the voltage drop and a predetermined voltage difference value to generate a comparison flag. The terminating step includes terminating the write operation on one of the two non-volatile memory cells according to the comparison flag. The write-back operating step includes performing a write-back operation on another of the two non-volatile memory cells.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: July 6, 2021
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventor: Meng-Fan Chang
  • Patent number: 11056195
    Abstract: A driving method of a nonvolatile memory device including multiple memory planes includes following operations: precharging at least one word line and at least one bit line of a first memory plane; if the at least one word line and the at least one bit line of the first memory plane have been precharged for a first time length or to respective voltage thresholds, precharging at least one word line and at least one bit line of a second memory plane; conducting a first data operation to at least one memory cell of the first memory plane disposed at intersections of the at least one word line and the at least one bit line thereof; conducting a second data operation to at least one memory cell of the second memory plane disposed at intersections of the at least one word line and the at least one bit line thereof.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: July 6, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yi-Ching Liu, Chin-Ming Yang
  • Patent number: 11043272
    Abstract: Methods of operating a memory include applying a programming pulse having a particular voltage level to a selected access line connected to a plurality of memory cells selected for programming during a programming operation, concurrently enabling for programming each memory cell of the plurality of memory cells selected for programming while applying the programming pulse, applying a subsequent programming pulse having a plurality of different voltage levels to the selected access line, and, for each group of memory cells of a plurality of groups of memory cells of the plurality of memory cells selected for programming, enabling that group of memory cells for programming while the subsequent programming pulse has a corresponding voltage level of the plurality of different voltage levels.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: June 22, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Aaron S. Yip
  • Patent number: 11024387
    Abstract: Techniques are provided for optimizing a program operation in a memory device to compensate for program speed variations due to block oxide thinning. In one approach, during a program operation, a program voltage which indicates program speed is acquired from sub-blocks with the highest and lowest program speeds. An initial program voltage for intermediate sub-blocks can be determined based on the acquired program voltages and the positions of the intermediate sub-blocks. The technique can accommodate a loss of one or both acquired program voltages if the programming is interrupted. In another approach, a program voltage which indicates program speed is acquired from one sub-block, and for a later-programmed sub-block, an appropriate offset is located from a table and summed with the acquired program voltage to determine an optimum initial program voltage.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: June 1, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Ching-Huang Lu, Ashish Baraskar, Vinh Diep
  • Patent number: 11017861
    Abstract: Provided herein may be a semiconductor memory device and a method of operating the semiconductor memory device to program a selected physical page of the semiconductor memory device. The method may include performing a plurality of program loops. Each of the program loops may include: applying a bit line voltage based on data input to a page buffer of the semiconductor memory device; applying a two-step program pulse to a word line coupled to the selected physical page; performing a program verify operation on the selected physical page using a double verify scheme; and determining a bit line voltage to be applied in a subsequent program loop based on a result of the program verify operation.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: May 25, 2021
    Assignee: SK hynix Inc.
    Inventor: In Gon Yang
  • Patent number: 11010244
    Abstract: A memory data management method includes the following steps reading a plurality of data of a plurality of memory cells of a memory block; determining whether error bits of the data exceed an error correction code (ECC) threshold; if the error bits of the data exceed the ECC threshold, a programming process being executed to increase a first threshold voltage of a first state data of the data for exceeding a first threshold, to increase a second threshold voltage of a second state data of the data for exceeding a second threshold, and to increase a third threshold voltage of a third state data of the data for exceeding a third threshold.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: May 18, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yung-Chun Li, Ping-Hsien Lin, Kun-Chi Chiang, Chien-Chung Ho
  • Patent number: 11011242
    Abstract: An apparatus includes a programming circuit configured to supply a program pulse to increase a threshold voltage of a memory cell. The apparatus also includes a sensing circuit configured to determine that the threshold voltage of the memory cell satisfies a trigger threshold voltage in response to the program pulse. The apparatus further includes a damping circuit configured to increase a voltage of a bit line connected to the memory cell after initiation of and during a second program pulse in response to the threshold voltage of the memory cell satisfying the trigger threshold voltage, the second program pulse being sent by the programming circuit.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: May 18, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Xiang Yang, Deepanshu Dutta, Gerrit Jan Hemink, Tai-Yuan Tseng, Yan Li
  • Patent number: 11004485
    Abstract: A memory system includes: a plurality of memory dies, and a controller selects a second read request, including at least a portion of a plurality of first read requests, so that the memory dies interleave and output data corresponding to the first read requests, and performs a correlation operation for the selected second read request, when the second read request is selected, the controller determines whether the correlation operation is performed or not before a time at which the second read request is selected, determines whether the correlation operation is successful or not, determines a pending credit in response to an operation state of the memory dies at the time at which the second read request is selected, and determines whether to perform the correlation operation or not for the second read request that is selected at the time at which the second read request is selected based on the pending credit.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: May 11, 2021
    Assignee: SK hynix Inc.
    Inventor: Jeen Park
  • Patent number: 11004513
    Abstract: Memory devices with controlled wordline ramp rates and associated systems and methods are disclosed herein. In one embodiment, a memory device includes at least one voltage regulator and a plurality of wordlines. The memory device is configured, during a programming operation of the memory region, to ramp a selected wordline to a desired programming voltage while ramping one or more adjacent, unselected wordlines electrically coupled to the selected wordline to desired inhibit voltage(s) using the at least one voltage regulator. In some embodiments, the memory device ramps the selected wordline and the one or more adjacent, unselected wordlines such that the one or more adjacent, unselected wordlines reach the desired inhibit voltage(s) when the selected wordline reaches the desired programming voltage. In these and other embodiments, the memory device ramps the selected wordline to the desired programming voltage without floating the selected wordline.
    Type: Grant
    Filed: January 27, 2020
    Date of Patent: May 11, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Allahyar Vahidimowlavi, Kalyan C. Kavalipurapu
  • Patent number: 10957364
    Abstract: Memory devices may have internal circuitry that employs voltages higher and/or lower than voltages provided by an external power source. Charge pumps are DC/DC converters that may be used to generate the higher voltages internally. The number of available charge pumps in a memory device may be conservatively dimensioned to be high, in some systems to protect yields. Some of the available charge pumps may be disabled during manufacturing or testing to reduce the number of active charge pumps. The testing process may employ dedicated logic in the memory device and the disabling may employ fuse circuitry.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: March 23, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Christian N. Mohr, John E. Riley
  • Patent number: 10937512
    Abstract: A method of managing programming errors in a multilevel NAND flash memory is provided. The multilevel NAND flash memory uses a two-pass programming algorithm—e.g., a first programming pass and a second programming pass—for programming a memory block being organized in pages, sharing a word line. The method comprises performing the first programming pass for at least one memory page, reading the at least one memory page between the first programming pass and the second programming pass, determining an error count value for the at least one programmed memory page, and responsive to determining that the error count value is below a threshold value, performing the second programming pass with active data.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: March 2, 2021
    Assignee: International Business Machines Corporation
    Inventors: Nikolaos Papandreou, Thomas Mittelholzer, Roman Alexander Pletka
  • Patent number: 10937503
    Abstract: A memory device may include: memory cells each having any one of first and second programmed states as a target programmed state; a peripheral circuit configured to perform a program operation so that each memory cell has a threshold voltage corresponding to the target programmed state; and a control circuit configured to control the peripheral circuit. The control circuit may include a program operation controller configured to control the peripheral circuit so that, during the program operation, an intermediate program operation is performed on the memory cells using an intermediate verify voltage, an additional program operation is performed on memory cells each having the second programmed state as a target programmed state if an intermediate verify operation passes, and a final program operation is performed on the memory cells such that each memory cell has a threshold voltage corresponding to the target programmed state.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: March 2, 2021
    Assignee: SK hynix Inc.
    Inventors: Un Sang Lee, Chi Wook An
  • Patent number: 10923179
    Abstract: A memory device includes a page with plurality of memory cells and a peripheral circuit that performs at least one program loop. The at least one program loop includes a program voltage applying phase for applying, during a program operation, a program voltage to a word line to which the plurality of memory cells are coupled and a program verify phase for determining whether a selected memory cell among the plurality of memory cells has been completely programmed. The memory device includes control logic that controls the peripheral circuit to: perform an auxiliary verify operation of applying an auxiliary verify voltage to the word line; perform a main verify operation of applying a main verify voltage larger than the auxiliary verify voltage to the word line; and determine a fail of the program operation, based on verify data obtained by performing the auxiliary verify operation and the main verify operation.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: February 16, 2021
    Assignee: SK hynix Inc.
    Inventors: Young Jin Woo, Won Yeol Choi
  • Patent number: 10891052
    Abstract: A system and method for optimization of non-volatile storage operational parameters is provided. The method may utilize a crowdsourcing server to gather performance data for multiple storage devices connected to respective remotely located host systems. The performance data may be transmitted at regular intervals or at predefined events and the crowdsourcing server may aggregate and determine improved operating parameters for each different type of storage device based on the data gathered for multiple instances of that type of storage device. The optimized operating parameters may be selected from pre-stored and pre-qualified operating parameter sets on the respective storage devices that the crowdsourcing server is aware of. The system includes a non-volatile memory and a controller that is configured to log performance data and transmit at least a portion of that logged data to the crowdsourcing server.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: January 12, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ariel Navon, Alex Bazarsky, Judah Gamliel Hahn, Eran Sharon
  • Patent number: 10885967
    Abstract: A memory device may include a phase driver circuit that may output a first voltage for refreshing a plurality of memory cells. The memory device may also include a plurality of word line driver circuits that may receive the first voltage via the phase driver circuit, such that each word line driver circuit of the plurality of word line driver circuits may provide the first voltage to a respective word line associated with a respective portion of the plurality of memory cells. In addition, each word line driver circuit may refresh the respective portion of the plurality of memory cells based on a respective word line enable signal provided to a first switch of the respective word line driver circuit.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: January 5, 2021
    Assignee: Micron Technology, Inc.
    Inventors: James S. Rehmeyer, Debra M. Bell, George B. Raad, Brian P. Callaway, Joshua E. Alzheimer
  • Patent number: 10885994
    Abstract: A circuit includes a program controller configured to perform a program operation with interleaved program-verify loops to program memory cells in a same block. During each program-verify loop, a control gate line voltage supply circuit first supplies a program pulse to a first cell of the block and then, before verifying the first cell, supplies a program pulse to a second cell of the block. After the program pulses are sent, the control gate line supply circuit consecutively supplies verify pulses to the first cell and the second cell such that a delay is introduced between the respective program and verify stages of the first and second cells. Additionally, a constant voltage bias on common control gate lines of the first and second memory cells is applied during the consecutive verify stages. Further, an order of verify pulses may be applied in a reverse order during a verify stage.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: January 5, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Xiang Yang, Huai-Yuan Tseng, Deepanshu Dutta
  • Patent number: 10885998
    Abstract: A circuit may include a voltage line and latch circuitry. The latch circuitry may be characterized by a switching voltage threshold and may be coupled to the voltage line. The latch circuitry may generate an output used to determine a state of a fuse. The circuit may also include generation circuitry coupled to the latch circuitry via the voltage line, wherein the generation circuitry is configured to pre-charge the voltage line to a first voltage between a system logical low voltage and the switching voltage threshold.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: January 5, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Wei Lu Chu, Dong Pan
  • Patent number: 10872672
    Abstract: A nonvolatile memory device includes a memory cell array includes memory cells, a row decoder, a page buffer circuit and a control logic circuit. The row decoder is connected to the memory cells through word lines and includes switches configured to select the word lines, respectively. The page buffer circuit is connected to the memory cell array through bit lines. The control logic circuit is configured to perform operational functions when the row decoder turns on a switch corresponding to a particular word line among the word lines.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: December 22, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Deahan Kim, Minsoo Kim, Kyunghoon Sung
  • Patent number: 10861556
    Abstract: In general, embodiments of the technology relate to a method for adjusting solid state memory write parameters. The method includes obtaining a performance goal for the solid state memory, receiving a client write request for data from a client, where the client write request comprises a logical address and data to be written. The method further includes determining a physical address corresponding to the logical address, where the physical address comprises a page number for a physical page in the persistent storage, obtaining at least one verify threshold value using the performance goal, issuing a control module program request including the data to be written and the at least one verify threshold value to a storage module, where the storage module comprises the physical page, and programming the data into the physical page of the storage module using the at least one verify threshold value.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: December 8, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Haleh Tabrizi, Seungjune Jeon, Andrew Cullen
  • Patent number: 10839893
    Abstract: A memory cell includes a first charge trap transistor and a second charge trap transistor. The first charge trap transistor has a substrate, a first terminal coupled to a first bitline, a second terminal coupled to a signal line, a control terminal coupled to a wordline, and a dielectric layer formed between the substrate of the first charge trap transistor and the control terminal of the first charge trap transistor. The second charge trap transistor has a substrate, a first terminal coupled to the signal line, a second terminal coupled to a second bitline, a control terminal coupled to the wordline, and a dielectric layer between the substrate of the second charge trap transistor and the control terminal of the second charge trap transistor. Charges are either trapped to or detrapped from the dielectric layer of the first charge trap transistor when writing data to the memory cell.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: November 17, 2020
    Assignee: Kneron (Taiwan) Co., Ltd.
    Inventors: Yuan Du, Mingzhe Jiang, Junjie Su, Chun-Chen Liu
  • Patent number: 10832778
    Abstract: A methodology and structure for driving a selected wordline to a negative voltage without the need for a negative wordline voltage generator. The methodology includes the step of boosting a non-selected wordline to a first positive voltage. The methodology proceeds with holding a selected wordline, which is adjacent to and capacitively coupled with the non-selected wordline, at zero voltage. The methodology continues with floating the selected wordline. The methodology proceeds with driving the non-selected wordline to a lower voltage to shift the selected wordline to less than zero volts due to capacitance effects. The methodology continues with the step of accelerating charge loss in a defective memory cell connected to the selected wordline while at a negative voltage during a soft erase operation.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: November 10, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Xiang Yang, Huai-yuan Tseng, Deepanshu Dutta
  • Patent number: 10825532
    Abstract: A method of operating a memory device includes performing a data read operation on at least one victim sub-block within a memory block containing a plurality of sub-blocks therein, in response to an erase command directed to a selected sub-block within the plurality of sub-blocks. Next, a soft program operation is performed on the at least one victim sub-block. This soft programming operation is then followed by an operation to erase the selected sub-block within the plurality of sub-blocks. This operation to erase the selected sub-block may include providing an erase voltage to a bulk region of a substrate on which the memory block extends, and the at least one victim sub-block may be disposed between the selected sub-block and the substrate.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: November 3, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-Bo Shim, Sang-Wan Nam, Ji-Ho Cho
  • Patent number: 10811098
    Abstract: Methods of operating a memory device include programming a page of a memory block of the memory device using a particular starting programming voltage, determining a programming voltage indicative of a programming efficiency of the page of the memory block during programming of the page of the memory block, storing a representation of the programming voltage indicative of the programming efficiency of the page of the memory block, setting a starting programming voltage for a different page of the memory block in response to the stored representation of the programming voltage indicative of the programming efficiency of the page of the memory block, and programming the different page of the memory block using its starting programming voltage.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: October 20, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Silvia Beltrami, Angelo Visconti
  • Patent number: 10796761
    Abstract: Technology for a memory device is described. The memory device can include an array of memory cells and a memory controller. The memory controller can receive a request to program a memory cell within the array of memory cells. The memory controller can select a current magnitude and a duration of the current magnitude for a programming set pulse based on a polarity of access for the memory cell, a number of prior write cycles for the memory cell, and electrical distances between the memory cell and wordline/bitline decoders within the array of memory cells. The memory controller can initiate, in response to the request, the programming set pulse to program the memory cell within the array of memory cells. The selected current magnitude and the selected duration of the current magnitude can be applied during the programming set pulse.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: October 6, 2020
    Assignee: Intel Corporation
    Inventors: Koushik Banerjee, Lu Liu, Sanjay Rangan
  • Patent number: 10777264
    Abstract: A program verification method for a nonvolatile memory device includes performing a first failure bit counting operation about a first stage to generate a first failure bit accumulated value and comparing the first failure bit accumulated value and a first failure reference value to determine a program failure. When the first failure bit accumulated value is less than the first failure reference value, a second failure bit counting operation for a second stage is performed to generate a second failure bit accumulated value. The second failure bit accumulated value is compared to a second reference value to determine a program failure. The second failure reference value is different from the first failure reference value.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: September 15, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyejin Yim, Sung-Won Yun, Il Han Park
  • Patent number: 10770145
    Abstract: Method of operating a memory include increasing respective threshold voltages of a first subset of memory cells of a plurality of memory cells to threshold voltage levels higher than a particular voltage level in response to applying a first plurality of programming pulses, and subsequently increasing respective threshold voltages of a second subset of memory cells of the plurality of memory cells to threshold voltage levels lower than the particular voltage level in response to applying a second plurality of programming pulses, wherein the first plurality of programming pulses have respective voltage levels within a first range of voltage levels, the second plurality of programming pulses have respective voltage levels within a second range of voltage levels, and a lowest voltage level of the first range of voltage levels is lower than or equal to a highest voltage level of the second range of voltage levels.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: September 8, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sarin, Allahyar Vahidimowlavi
  • Patent number: 10754583
    Abstract: A level width corresponding to a group of memory cells of a memory component is determined. The determined level width and a target level width is compared. In response to the determined level width being different than the target level width, one or more program step characteristics are adjusted to adjust the determined level width to the target level width.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: August 25, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Bruce A. Liikanen
  • Patent number: 10732846
    Abstract: A computer-implemented method according to one embodiment includes determining, after writing data to a non-volatile memory block, one or more delta threshold voltage shift (TVS?) values. One or more overall threshold voltage shift values for the data written to the non-volatile memory block are calculated, the values being a function of the one or more TVS? values to be used when writing data to the non-volatile memory block. The overall threshold voltage shift values are stored. A base threshold voltage shift (TVSBASE) value, the one or more TVS? values, or both the TVSBASE value and the one or more TVS? values are re-calibrated during a background health check after a predetermined number of background health checks without calibration are performed.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: August 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Camp, Timothy J. Fisher, Aaron D. Fry, Nikolas Ioannou, Ioannis Koltsidas, Nikolaos Papandreou, Thomas Parnell, Roman A. Pletka, Charalampos Pozidis, Sasa Tomic
  • Patent number: 10705986
    Abstract: Embodiments of this application provide a flash interface controller and an operation command processing method, and relate to the field of data storage. Programmable first type microcode and second type microcode are introduced to a flash interface controller. The first type microcode can be modified through programming to adapt to a procedure of parsing an operation command of a new protocol, and the second type microcode can be modified through programming to adapt to a flash bus operation required by a new flash interface standard. An operation command can be parsed by only fixing logics of physical modules in the flash interface controller and reading first type microcode and second type microcode that are related to the operation command. Therefore, various protocols and flash interface standards can be adapted to, and flexibility is good.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: July 7, 2020
    Assignee: Huawei Technologies Co. Ltd.
    Inventors: Xianhui Wang, Rui Huang, You Li
  • Patent number: 10698761
    Abstract: A method for operating a semiconductor memory device may include applying a program pulse for programming data of a first page included in the semiconductor memory device. The method may include determining whether the number of times of applying the program pulse has exceeded a first critical value. The method may include performing an error bit check on a second page coupled to the same word line as the first page, based on the determined result of whether the first critical value has been exceeded.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: June 30, 2020
    Assignee: SK hynix Inc.
    Inventors: Nam Hoon Kim, Min Kyu Lee
  • Patent number: 10685726
    Abstract: According to one embodiment, a semiconductor storage device includes: a NAND string with a first set of memory cells including a first memory cell; and a second set of memory cells including a second memory cell disposed above the first memory cell. The number of memory cells included in the first set is different from that of memory cells included in the second set. During a program verify operation when a data item of a level is written to a memory cell of the first set and a memory cell of the second set, a first verify voltage is applied to the gate of the memory cell of the first set and a second verify voltage different from the first verify voltage is applied to the gate of the memory cell of the second set.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: June 16, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yuichiro Suzuki, Noboru Ooike, Masashi Yoshida
  • Patent number: 10679723
    Abstract: Disclosed is a system and method for performing direct memory characterization of memory cells in a memory array using peripheral transistors. A memory array is fabricated using a mask layer defining routing for a set of first stage periphery transistors electrically connected to the word lines of the memory array. A revised mask is used for defining a different routing for a set of second stage periphery transistors including different characteristics than the first stage periphery transistors. Testing is conducted by applying a simulated Erase signal to the nonvolatile memory cells and determining which cells are erased. Based on this test, certain characteristics of the first and/or second stage periphery transistors can be identified that provide improved conditions for the nonvolatile memory cells. A product chip can be manufactured using modified versions of the first stage periphery transistors that incorporate the characteristics that provide the improved condition(s).
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: June 9, 2020
    Assignee: PDF SOLUTIONS, INC.
    Inventors: Dong Kyu Lee, Kelvin Yih-Yuh Doong, Tuan Pham, Klaus Schuegraf, Christoph Dolainsky, Huan Tsung Huang, Hendrik Schneider
  • Patent number: 10672447
    Abstract: Disclosed is a memory device. The memory device includes a memory cell array that includes a target cell, a row decoder that drive a word line, and a write driver and sense amplifier that are configured to drive a bit line and a source line. The row decoder is configured to drive the word line in a first program operation and a second program operation. Between a start of the first program operation and an end of the second program operation, the write driver and sense amplifier are configured to continuously drive a bit line connected to the target cell with a second driving voltage or drive a source line connected to the target cell with a third driving voltage.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: June 2, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyunsung Jung, Hyemin Shin, Yoonjong Song, Jung Hyuk Lee
  • Patent number: 10664432
    Abstract: Apparatuses and methods of data transmission between semiconductor chips are described. An example apparatus includes: a data bus inversion (DBI) circuit that receives first, second and third input data in order, and further provides first, second and third output data, either with or without data bus inversion. The DBI circuit includes a first circuit that latches the first input data and the third input data; a second circuit that latches the second input data; a first DBI calculator circuit that performs first DBI calculation on the latched first input data and the latched second input data responsive to the first circuit latching the first input data and the second circuit latching the second input data, respectively; and a second DBI calculator circuit that performs second DBI calculation on the latched second data and the latched third input data responsive to the first circuit latching the third input data.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: May 26, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Yuki Ebihara, Seiji Narui
  • Patent number: 10658051
    Abstract: Provided herein may be a memory controller and a method of operating the same. The memory controller may include a control component configured to control an operation of a semiconductor memory device including a plurality of memory cells in response to a request from a host. The control component may be configured to select a subset of memory cells, among all memory cells in a selected page of the semiconductor memory device, and to determine an optimal read voltage based on the select subset of memory cells.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: May 19, 2020
    Assignee: SK hynix Inc.
    Inventor: Ji Man Hong
  • Patent number: 10658050
    Abstract: Provided herein may be a memory controller and a method of operating the same. The memory controller may include a control component configured to control an operation of a semiconductor memory device including a plurality of memory cells in response to a request from a host. The control component may be configured to select a subset of memory cells, among all memory cells in a selected page of the semiconductor memory device, and to determine an optimal read voltage based on the select subset of memory cells.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: May 19, 2020
    Assignee: SK hynix Inc.
    Inventor: Ji Man Hong
  • Patent number: 10658043
    Abstract: A method of operating a memory device includes performing a data read operation on at least one victim sub-block within a memory block containing a plurality of sub-blocks therein, in response to an erase command directed to a selected sub-block within the plurality of sub-blocks. Next, a soft program operation is performed on the at least one victim sub-block. This soft programming operation is then followed by an operation to erase the selected sub-block within the plurality of sub-blocks. This operation to erase the selected sub-block may include providing an erase voltage to a bulk region of a substrate on which the memory block extends, and the at least one victim sub-block may be disposed between the selected sub-block and the substrate.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: May 19, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-Bo Shim, Sang-Wan Nam, Ji-Ho Cho
  • Patent number: 10658049
    Abstract: Provided herein may be a memory controller and a method of operating the same. The memory controller may include a control component configured to control an operation of a semiconductor memory device including a plurality of memory cells in response to a request from a host. The control component may be configured to select a subset of memory cells, among all memory cells in a selected page of the semiconductor memory device, and to determine an optimal read voltage based on the select subset of memory cells.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: May 19, 2020
    Assignee: SK hynix Inc.
    Inventor: Ji Man Hong
  • Patent number: 10643720
    Abstract: An apparatus includes a programming circuit configured to supply a program pulse to increase a threshold voltage of a memory cell. The apparatus also includes a sensing circuit configured to determine that the threshold voltage of the memory cell satisfies a trigger threshold voltage in response to the program pulse. The apparatus further includes a damping circuit configured to increase a voltage of a bit line connected to the memory cell after initiation of and during a second program pulse in response to the threshold voltage of the memory cell satisfying the trigger threshold voltage, the second program pulse being sent by the programming circuit.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: May 5, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Xiang Yang, Deepanshu Dutta, Gerrit Jan Hemink, Tai-Yuan Tseng, Yan Li
  • Patent number: 10636501
    Abstract: Techniques are described for reducing program disturb including neighbor word interference in a memory device. Voltages applied to the word lines adjacent to the selected word line WLn during program and read operations are adjusted. The adjacent word lines include WLn?1, a source-side adjacent word line of WLn, and WLn+1, a drain side adjacent word line of WLn. In one aspect, VWLn?1<VWLn+1 during the verify tests of the program operation for the data states above the lowest programmed data state and VWLn?1=VWLn+1 during the verify test for the lowest programmed data state. Also, VWLn?1<VWLn+1 during a read operation which distinguishes between the programmed data states and VWLn?1=VWLn+1 during a read operation which distinguishes between erased state and the lowest programmed data state.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: April 28, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Han-Ping Chen, Ching-Huang Lu, Vinh Diep, Changyuan Chen
  • Patent number: 10629278
    Abstract: Described herein are embodiments related to first-pass dynamic program targeting (DPT) operations on memory cells of memory systems. A processing device determines that a first programming pass of a programming operation has been performed on a memory cell of a memory component. The processing device performs a DPT operation on the memory cell to calibrate a first program-verify (PV) target corresponding to a first first-pass programming distribution and a second PV target corresponding to a second first-pass programming distribution before a second programming pass of the programming operation is performed on the memory cell.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: April 21, 2020
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Michael Sheperek, Larry J. Koudele, Bruce A. Liikanen
  • Patent number: 10622374
    Abstract: A method of forming a vertical string of memory cells comprises forming a lower stack comprising first alternating tiers comprising vertically-alternating control gate material and insulating material. An upper stack is formed over the lower stack, and comprises second alternating tiers comprising vertically-alternating control gate material and insulating material having an upper opening extending elevationally through multiple of the second alternating tiers. The lower stack comprises a lower opening extending elevationally through multiple of the first alternating tiers and that is occluded by occluding material. At least a portion of the upper opening is elevationally over the occluded lower opening. The occluding material that occludes the lower opening is removed to form an interconnected opening comprising the unoccluded lower opening and the upper opening.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: April 14, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Hongbin Zhu, Charles H. Dennison, Gordon A. Haller, Merri L. Carlson, John D. Hopkins, Jia Hui Ng, Jie Sun
  • Patent number: 10622368
    Abstract: Azimuthally-split metal-semiconductor alloy floating gate electrodes can be formed by providing an alternating stack of insulating layers and spacer material layers, forming a dielectric separator structure extending through the alternating stack, and forming memory openings that divides the dielectric separator structure into a plurality of dielectric separator structures. The spacer material layers are formed as, or are replaced with, electrically conductive layers, which are laterally recessed selective to the insulating layers and the plurality of dielectric separator structures to form a pair of lateral cavities at each level of the electrically conductive layers in each memory opening. After formation of a blocking dielectric layer, a pair of physically disjoined metal-semiconductor alloy portions are formed in each pair of lateral cavities as floating gate electrodes. A tunneling dielectric layer and a semiconductor channel layer is subsequently formed in each memory opening.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: April 14, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Senaka Kanakamedala, Raghuveer S. Makala, Rahul Sharangpani, Somesh Peri, Yao-Sheng Lee, James Kai