Particular Biasing Patents (Class 365/185.18)
  • Patent number: 10438658
    Abstract: Provided is a non-volatile memory device comprising a plurality of memory cells and memory control logic that when executed performs operations comprising initiating a refresh operation; in response to the refresh operation, performing a read of the memory cells to read values of the memory cells; determining whether the read memory cells have a first value or a second value; and for the memory cells determined to have the first value, rewriting the determined first value to the memory cell, wherein the rewriting operation is not performed with respect to memory cells determined to have the second value.
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: October 8, 2019
    Assignee: INTEL CORPORATION
    Inventors: Ningde Xie, Robert W. Faber
  • Patent number: 10431313
    Abstract: A three-dimensional stacked memory device is configured to provide uniform programming speeds of different sets of memory strings formed in memory holes. In a process for removing sacrificial material from word line layers, a block oxide layer in the memory holes is etched away relatively more when the memory hole is relatively closer to an edge of the word line layers where an etchant is introduced. A thinner block oxide layer is associated with a faster programming speed. To compensate, memory strings at the edges of the word line layers are programmed together, separate from the programming of interior memory strings. A program operation can use a higher initial program voltage for programming the interior memory strings compared to the edge memory strings.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: October 1, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Zhengyi Zhang, Yingda Dong, James Kai, Johann Alsmeier
  • Patent number: 10431319
    Abstract: The present disclosure includes apparatuses and methods related to selectable trim settings on a memory device. An example apparatus can store a number of sets of trim settings and select a particular set of trims settings of the number of sets of trim settings based on desired operational characteristics for the array of memory cells.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: October 1, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Aswin Thiruvengadam, Daniel L. Lowrance, Peter Feeley
  • Patent number: 10424596
    Abstract: Some embodiments include a conductive structure of an integrated circuit. The conductive structure includes an upper primary portion, with the upper primary portion having a first conductive constituent configured as a container. The container has a bottom, and a pair of sidewalls extending upwardly from the bottom. An interior region of the container is over the bottom and between the sidewalls. The upper primary portion includes a second conductive constituent configured as a mass filling the interior region of the container. The second conductive constituent is a different composition than the first conductive constituent. One or more conductive projections join to the upper primary portion and extend downwardly from the upper primary portion. Some embodiments include assemblies comprising memory cells over conductive structures. Some embodiments include methods of forming conductive structures.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: September 24, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Nancy M. Lomeli, Tom George, Jordan D. Greenlee, Scott M. Pook, John Mark Meldrim
  • Patent number: 10424378
    Abstract: In one example in accordance with the present disclosure a control circuit is described. The control circuit includes a source following component to receive an input voltage and output a switching voltage. The circuit also includes an input leg of a current mirror coupled to the source following component. The input leg of the current mirror replicates the switching voltage to an output leg of the current mirror of a memristive bit cell. The circuit also includes a number of current control components. At least one of the current control components enforces a constant current through the source following component and other current control components maintain the input leg of the current mirror and the output leg of the current mirror at the same current.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: September 24, 2019
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Brent Buchanan, Le Zheng, John Paul Strachan
  • Patent number: 10418101
    Abstract: In one embodiment, a device includes a memory cell for storing “0” or “1” as stored data, and a control circuit for reading out the stored data. The memory cell includes area C1/C3 where a cell current increases as a voltage across the cell increases, area C2/C4 where the current is larger than that in C1/C3 and the voltage decreases while the current increases, and area C5 where the current is larger than that in C2/C4 and increases as the voltage increases. The control circuit performs first processing of reading out the stored data such that the current when the data is “0” and the current when the data is “1” take values in C1/C3, and second processing of reading out the stored data such that the current when the data is “0” or the current when the data is “1” takes a value in C2/C4 or C5.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: September 17, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Takayuki Miyazaki
  • Patent number: 10418114
    Abstract: A semiconductor memory device includes first and second memory cell transistors between first and second select transistors, third and fourth memory cell transistors between third and fourth select transistors, a first word line for first and third memory cell transistors, a second word line for second and fourth memory cell transistors, first to fourth selection gate lines respectively for first through fourth select transistors, a bit line, and a source line. During a read operation, while a voltage applied to the second word line is boosted, voltages applied to the first word line and the third and fourth selection gate line are also boosted, after which the voltage applied to the first word line is lowered, and the third and fourth selection gate lines are discharged. After the time the third and fourth selection gate lines are discharged, voltages applied to the bit line and the source line are boosted.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: September 17, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Takeshi Hioka
  • Patent number: 10409515
    Abstract: A nonvolatile memory device includes a memory cell array including a plurality of first segments having a write data, and a plurality of second segments having a programmed information defining a programmed segment from the plurality of first segments. A randomizer is configured to randomize the write data. An error correction circuit is configured to perform an error correction operation on the write data. A control logic is configured to determine the programmed information from an address received from a memory controller, and to determine whether to operate the randomizer and the error correction circuit based on the determination of the programmed information during the program operation. A page buffer is configured to store the write data and the programmed information during the randomizing and the error correction operation.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: September 10, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung Sunwoo, Makoto Hirano
  • Patent number: 10410692
    Abstract: Provided herein may be a memory device and a method of operating the same. The memory device may include a memory block including a plurality of pages coupled to word lines, respectively, peripheral circuits configured to, during a program operation, perform program, verify, and discharge operations on memory cells coupled to a word line selected from among the word lines, and a control logic configured to control the peripheral circuits such that, during the discharge operation performed after the verify operation, word lines, included in a region in which the program operation has not completed, and word lines, included in a region in which the program operation has completed, among the word lines, are discharged at different times.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: September 10, 2019
    Assignee: SK hynix Inc.
    Inventors: Hee Youl Lee, Sung In Hong
  • Patent number: 10410728
    Abstract: A nonvolatile memory device for reducing hot-carrier injection (HCI) and a programming method of the nonvolatile memory device, the programming method of the nonvolatile memory device includes programming memory cells included in a cell string in a direction from an upper memory cell adjacent to a string selection transistor to a lower memory cell adjacent to a ground selection transistor from among a plurality of memory cells; when a selected memory cell is programmed, applying a first inhibition voltage to first non-selected word lines connected to first non-selected memory cells located over the selected memory cell; and applying a second inhibition voltage to second non-selected word lines connected to second non-selected memory cells located under the selected memory cell when a predetermined delay time elapses after the first inhibition voltage is applied.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: September 10, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sang-Won Shim
  • Patent number: 10402247
    Abstract: A non-volatile memory includes a page buffer array in which page buffers are arranged in a matrix form. A method of operating the non-volatile memory includes selecting columns from among multiple columns of the page buffer array, and counting fail bits stored in page buffers included in the selected columns.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: September 3, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bong-Soon Lim, Sang-Hyun Joo, Kee-Ho Jung
  • Patent number: 10403346
    Abstract: According to one embodiment, a semiconductor memory device comprises a first bank and a second bank. Each of the first bank and the second bank comprises a memory cell having a variable resistor element, a reference cell, a sense amplifier having a first input terminal electrically coupled to the memory cell and a second input terminal electrically coupled to the reference cell, and a first transistor electrically coupling the memory cell and the first input terminal of the sense amplifier. A gate of the first transistor of the first hank and a gate of the first transistor of the second bank are independently supplied with a voltage.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: September 3, 2019
    Assignees: TOSHIBA MEMORY CORPORATION, SK HYNIX INC.
    Inventors: Katsuyuki Fujita, Hyuck Sang Yim
  • Patent number: 10396089
    Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: August 27, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Tsutomu Okazaki, Daisuke Okada, Kyoya Nitta, Toshihiro Tanaka, Akira Kato, Toshikazu Matsui, Yasushi Ishii, Digh Hisamoto, Kan Yasui
  • Patent number: 10394649
    Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of a memory cell can shift depending on when the read operation occurs. A memory cell is sensed by discharging a sense node into a bit line and detecting an amount of discharge at two sense times relative to a trip voltage. A bit of data is stored in first and second latches based on the two sense times, to provide first and second pages of data. The pages are evaluated using parity check equations and one of the pages which satisfies the most equations is selected. In another option, word line voltages are grounded and then floated to prevent coupling up of the word line. A weak pulldown to ground can gradually discharge a coupled up voltage of the word lines.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: August 27, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Idan Alrod, Eran Sharon, Alon Eyal, Liang Pang, Evgeny Mekhanik
  • Patent number: 10388367
    Abstract: A nonvolatile memory device includes a voltage generator that sequentially provides a first setup voltage and second setup voltage to a word line of a memory cell array, and control logic including a time control unit that determines a word line setup time for the word line in relation to the second setup voltage based on a difference between the first and second setup voltages.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: August 20, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Won Park, Dongkyo Shim, Kitae Park, Sang-Won Shim
  • Patent number: 10388381
    Abstract: A semiconductor memory device includes a memory cell array coupled to a plurality of word lines, a voltage generator generating a program voltage and first and second pass voltages in response to voltage generation control signals, an address decoder selectively applying the program voltage and the first and second pass voltages to the plurality of word lines in response to address decoder control signals, and a control logic controlling the voltage generator and the address decoder to perform a program operation.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: August 20, 2019
    Assignee: SK hynix Inc.
    Inventors: Jae Hyeon Shin, Sung Hyun Hwang
  • Patent number: 10373687
    Abstract: A semiconductor memory device includes a cell string and a peripheral circuit. The cell string includes a plurality of memory cells coupled between a common source line and a bit line. The peripheral circuit controls a voltage supplied to the cell string to program a selected memory cell of the cell string by performing a program loop including a program section, a detrap section, and a verify section. Also, the peripheral circuit is configured to supply a program voltage to a word line coupled to the selected memory cell among the plurality of memory cells during the program section. The peripheral circuit further supplies a detrap voltage to the cell string during the detrap section and supplies a verify voltage to the word line during the verify section.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: August 6, 2019
    Assignee: SK hynix Inc.
    Inventor: Hee Youl Lee
  • Patent number: 10372373
    Abstract: Apparatus, systems, methods, and computer program products for adaptive power balancing in memory device operations are disclosed. One apparatus includes a power balancing component for the memory device. A power balancing component is configured to determine a first amount of power consumed by each respective operation in a set of operations for a memory device for at least one previous iteration of each respective operation. A power balancing component utilizes a second amount of power to perform a next iteration of each respective operation based on a first amount of power consumed by each respective operation in at least one previous iteration.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: August 6, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Shay Benisty, Yoav Weinberg, Ariel Navon
  • Patent number: 10372536
    Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of a memory cell can shift depending on when the read operation occurs. A memory cell is sensed by discharging a sense node into a bit line and detecting an amount of discharge at two sense times relative to a trip voltage. A bit of data is stored in first and second latches based on the two sense times, to provide first and second pages of data. The pages are evaluated using parity check equations and one of the pages which satisfies the most equations is selected. In another option, word line voltages are grounded and then floated to prevent coupling up of the word line. A weak pulldown to ground can gradually discharge a coupled up voltage of the word lines.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: August 6, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Idan Alrod, Eran Sharon, Alon Eyal, Liang Pang, Evgeny Mekhanik
  • Patent number: 10366728
    Abstract: Apparatuses and methods for providing a program voltage responsive to a voltage determination are described. An example apparatus includes a memory array comprising a plurality of access lines. The example apparatus further includes a memory access circuit coupled to the memory array. The memory access circuit is configured to, during a memory program operation, provide an inhibit voltage to the plurality of access lines. The memory access circuit is further configured to, during the memory program operation, provide a program voltage to a target access line of the plurality of access lines responsive to a determination that an access line of the plurality of access lines has a voltage equal to or greater than a threshold voltage. The threshold voltage is less than the inhibit voltage.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: July 30, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Jae-Kwan Park
  • Patent number: 10366758
    Abstract: A storage device includes a data memory unit and a status memory unit. The data memory unit includes a pair of flash memory cells to be read by a complementary read mode, and 1-bit data is stored therein by the pair of flash memory cells. The status memory unit includes a flash memory cell to be read by a reference read mode, and a status flag is stored therein by the flash memory cell.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: July 30, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takashi Kurafuji, Tomoya Ogawa, Yasuhiko Taito
  • Patent number: 10360983
    Abstract: In a method of programming a three-dimensional nonvolatile memory device, a program loop is executed at least one time. The program loop includes a programming step for programming selected memory cells among memory cells and a verifying step for verifying whether the selected memory cells are program-passed or not. In programming the selected memory cells, a level of a voltage being applied to a common source line connected to the memory cells in common may be changed. Thus, in a program operation, power consumption which is needed to charge-discharge the common source line can be decreased while increasing boosting efficiency.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: July 23, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yoon-Hee Choi, Sungyeon Lee, Sang-Hyun Joo
  • Patent number: 10353622
    Abstract: Systems and methods for internal copy-back with read-verify are described. In one embodiment, a storage device includes a controller to select a first single level cell (SLC) page of a plurality of SLC pages on the storage device to transfer to a triple level cell (TLC) page. The controller, in conjunction with an error correcting code (ECC) decoder, read-verifies the first SLC page. Read-verifying the first SLC page includes reading the first SLC page to an internal page buffer, decoding the first SLC page read into the internal page buffer, determining a number of errors contained in the first SLC page based at least in part on the decoding, and verifying whether the number of errors contained in the first SLC page satisfies an error threshold. The controller transfers the first SLC page to the TLC page according to a result of read-verifying the first SLC page.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: July 16, 2019
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Erich F. Haratsch, Zhengang Chen, Stephen Hanna, Abdelhakim Alhussien
  • Patent number: 10354735
    Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: July 16, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Toshihiro Tanaka, Yukiko Umemoto, Mitsuru Hiraki, Yutaka Shinagawa, Masamichi Fujito, Kazufumi Suzukawa, Hiroyuki Tanikawa, Takashi Yamaki, Yoshiaki Kamigaki, Shinichi Minami, Kozo Katayama, Nozomu Matsuzaki
  • Patent number: 10353598
    Abstract: Systems, apparatuses, and methods are provided that refresh data in a memory. Data is programmed into the memory. After which, part or all of the data may be refreshed. The refresh of the data may be different from the initial programming of the data in one or more respects. For example, the refresh of the data may include fewer steps than the programming of the data and may be performed without erasing a section of memory. Further, the refresh of the data may be triggered in one of several ways. For example, after programming the data, the data may be analyzed for errors. Based on the number of errors found, the data may be refreshed.
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: July 16, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Jianmin Huang, Bo Lei, Jun Wan, Niles Yang
  • Patent number: 10347340
    Abstract: A memory array and a method for reading, programming and erasing the same are provided. The memory array includes flash memory cells arranged in an array, each flash memory cell includes a first and a second split-gate flash memory cell; a first control gate of the first split-gate flash memory cell is connected with a first control gate of the second split-gate flash memory cell and a first control gate line, a second control gate of the first split-gate flash memory cell is connected with a second control gate of the second split-gate flash memory cell and a second control gate line; a word line gate of the first split-gate flash memory cell is connected with a word line gate of the second split-gate flash memory cell and a word line; two drains of the first and second split-gate flash memory cells share a same bit line.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: July 9, 2019
    Assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corporation
    Inventor: Jian Hu
  • Patent number: 10325664
    Abstract: According to an embodiment, a semiconductor memory, on receiving a first command, applies a voltage within a first range and a voltage within a second range to a word line and reads a first bit from a memory cell, and, on receiving a second command, applies a voltage within a third range to the word line and reads a second bit from the memory cell. The controller issues the first command a plurality of times and changes the voltages to be applied to the word line within the first range and the second range in accordance with the plurality of first commands, specifies a first and second voltage within the first and the second range, respectively, and estimates a third voltage within the third range. The voltage applied to read the second bit is the estimated third voltage.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: June 18, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Tsukasa Tokutomi, Masanobu Shirakawa, Marie Takada
  • Patent number: 10311957
    Abstract: The disclosed technology relates to a memory device configured to perform multiple access operations in response to a single command received through a memory controller and a method of performing the multiple access operations. In one aspect, the memory device includes a memory array comprising a plurality of memory cells and a memory controller. The memory controller is configured to receive a single command which specifies a plurality of memory access operations to be performed on the memory array. The memory controller is further configured to cause the specified plurality of memory access operations to be performed on the memory array.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: June 4, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Daniele Balluchi, Corrado Villa
  • Patent number: 10304502
    Abstract: The present disclosure includes apparatuses and methods related to accessing data in memory. One example method comprises storing data associated with a first operation in a first sense amplifier responsive to receiving a request to perform a second operation, and performing the second operation associated with a row of memory cells while the data associated with the first operation is being stored in the first sense amplifier.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: May 28, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Timothy P. Finkbeiner, Glen E. Hush, David L. Pinney
  • Patent number: 10297493
    Abstract: The present disclosure includes semiconductor structures and methods of forming semiconductor structures for trench isolation interfaces. An example semiconductor structure includes a semiconductor substrate having a shallow trench isolation (STI) structure with a trench formed therein. An material in the trench forms a charged interface by interaction with the semiconductor substrate of the STI structure. The formed charged interface raises a parasitic threshold of the STI structure.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: May 21, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Arup Bhattacharyya
  • Patent number: 10298263
    Abstract: A data processing system includes a likelihood input operable to receive encoded data, a decoder operable to apply a decoding algorithm to likelihood values for the received encoded data and to yield a decoded output, and a decoder input initialization circuit operable to generate new decoder input values based in part on the likelihood values for the received encoded data after the likelihood values for the received encoded data have failed to converge in the decoder.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: May 21, 2019
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Sundararajan Sankaranarayanan, AbdelHakim S. Alhussien, Erich F. Haratsch, Earl Cohen
  • Patent number: 10290642
    Abstract: Flash memory technology is disclosed. In one example, a flash memory cell can include a charge storage structure, a control gate laterally separated from the charge storage structure, and at least four dielectric layers disposed between the control gate and the charge storage structure. Associated systems and methods are also disclosed.
    Type: Grant
    Filed: September 30, 2017
    Date of Patent: May 14, 2019
    Assignee: Intel Corporation
    Inventors: Haitao Liu, Guangyu Huang, Krishna K. Parat, Shrotri B. Kunal, Srikant Jayanti
  • Patent number: 10291414
    Abstract: An approach is provided in which an information handling system performs multiple tests on a memory device using different supply voltage levels. The information handling system identifies a set of memory cells in the memory that produce a same result during each of the memory tests at the different supply voltage levels, and generates a unique identifier based on the set of memory cells. In turn, the information handling system uses the unique identifier in one or more processes executed by the information handling system.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: May 14, 2019
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 10277119
    Abstract: A charge pump that can be configured to operate in a first mode and a second mode is disclosed. The charge pump can comprise a charging capacitor coupled to a first node and configured to transfer a first DC voltage to the first node. The charge pump can also comprise a first output node and a second output node coupled to the first node. During the first mode, the first output node can be configured to output a second DC voltage based on the first DC voltage, and the second output node can be configured to output a third DC voltage based on the first DC voltage. During the second mode, the first output node can be configured to output the second DC voltage, and the second output node can be configured to output an AC voltage, the AC voltage being offset by the third DC voltage.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: April 30, 2019
    Assignee: Apple Inc.
    Inventors: Weijun Yao, David A. Stronks, Hopil Bae, Kingsuk Brahma, Wei Hsin Yao, Yafei Bi, Yingxuan Li
  • Patent number: 10276250
    Abstract: A memory device includes a plurality of memory cells arranged in series in a semiconductor body. First and second dummy memory cells arranged in series between a first string select switch and a first edge memory cell at a first end of the plurality of memory cells. The first dummy memory cell is adjacent the first edge memory cell, and the second dummy memory cell is adjacent the first string select switch. A channel line includes channels for the plurality of memory cells and the first and second dummy memory cells. Control circuitry is adapted for programming a selected memory cell in the plurality of memory cells corresponding to a selected word line by applying a switching voltage to the first dummy memory cell, the switching voltage having a first voltage level during a first time interval, and thereafter changing to a second voltage level higher than the first voltage level.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: April 30, 2019
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Wei-Chen Chen, Hang-Ting Lue
  • Patent number: 10269434
    Abstract: According to one embodiment, a memory system includes a semiconductor memory including a memory cell, and a controller configured to control the semiconductor memory and capable of creating second data based on first data read from the memory cell. Upon receiving a physical erase request for the first data held in the memory cell from an external device, the controller transmits one of an erase instruction and a write instruction for the second data to the semiconductor memory.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: April 23, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Katsuhiko Iwai, Takashi Ogasawara
  • Patent number: 10268407
    Abstract: In one embodiment, an apparatus comprises a memory array and a controller. The controller is to receive a first read command specifying a read voltage offset profile identifier; identify a read voltage offset profile associated with the read voltage offset profile identifier, the read voltage offset profile comprising at least one read voltage offset; and perform a first read operation specified by the first read command using at least one read voltage adjusted according to the at least one read voltage offset of the read voltage offset profile.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: April 23, 2019
    Assignee: Intel Corporation
    Inventors: Aliasgar S. Madraswala, Xin Guo, Naveen Vittal Prabhu, Yu Du, Purval Shyam Sule
  • Patent number: 10256110
    Abstract: A multiple patterning process is provided with a self-aligned blocking (SAB) technique. The SAB technique trades off difficult overlay requirements for more manageable etch selectivity requirements between the various layers utilized for the patterning process. As disclosed herein, damage to sidewalls resulting from etching at the self-aligned block masking step may still occur. Damage is repaired by providing a plug layer that fills the areas of the damaged spacers. The plug layer may be the same material as forms the spacers. In this manner, the fill process provides a self-healing mechanism for damaged spacers.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: April 9, 2019
    Assignee: Tokyo Electron Limited
    Inventor: Nihar Mohanty
  • Patent number: 10255959
    Abstract: A memory device may include a selected bit line connected to a first node and configured to receive a first current, a selected memory cell connected to the selected bit line, a reference bit line connected to a second node and configured to receive a second current, a reference memory cell connected between the reference bit line and a reference source line, a sub bit line connected to the second node, a sub memory cell connected between the sub bit line and a sub source line, and a sense amplifier configured to sense a voltage difference between the first node and the second node to determine data read from a selected memory cell connected to the selected bit line. The sub memory cell may include a cell transistor. A gate electrode of the cell transistor may be connected to the sub source line.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: April 9, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung Min Lee, Hyemin Shin, Jung Hyuk Lee, Hyunsung Jung
  • Patent number: 10249376
    Abstract: A flash memory storage device including a memory cell array and a memory control circuit is provided. The memory cell array includes a plurality of memory blocks and a redundant memory block. The memory blocks are configured to store data. The memory control circuit is coupled to the memory cell array. The memory control circuit is configured to perform an erase operation to a current memory block of the memory blocks and record an erase retry count of the current memory block. The memory control circuit determines whether the erase retry count exceeds a threshold value. If the erase retry count exceeds the threshold value, the memory control circuit replaces the current memory block by the redundant memory block erased in advance during a time interval of the erase operation. In addition, an operating method of a flash memory storage device is also provided.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: April 2, 2019
    Assignee: Winbond Electronics Corp.
    Inventor: Jun-Lin Yeh
  • Patent number: 10248499
    Abstract: A first phase of a programming process is performed to program data into a set of non-volatile memory cells using a set of verify references and allowing for a first number of programming errors. After completing the first phase of programming, an acknowledgement is provided to the host that the programming was successful. The memory system reads the data from the set of non-volatile memory cells and uses an error correction process to identify and correct error bits in the data read. When the memory system is idle and after the acknowledgement is provided to the host, the memory system performs a second phase of the programming process to program the corrected error bits into the set of the non-volatile memory cells using the same set of verify references and allowing for a second number of programming errors.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: April 2, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rohit Sehgal, Nian Niles Yang
  • Patent number: 10243560
    Abstract: Systems and methods for maintaining a slew rate while loading flash memory dies are described. In one embodiment, the systems and methods may include placing one or more comparator circuits connectively between one or more channel controllers and a plurality of flash memory dies and maintaining a slew rate in relation to the one or more channel controllers writing data to a plurality of flash memory dies inside the solid state drive. In some cases, a hardware controller of a solid state drive may include the one or more channel controllers. In some cases, the plurality of flash memory dies may include at least one NAND die.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: March 26, 2019
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Vinod Arjun Huddar, Abhishek Laguvaram
  • Patent number: 10236064
    Abstract: A semiconductor memory device includes a cell string and a peripheral circuit. The cell string includes a plurality of memory cells coupled between a common source line and a bit line. The peripheral circuit controls a voltage supplied to the cell string to program a selected memory cell of the cell string by performing a program loop including a program section, a detrap section, and a verify section. Also, the peripheral circuit is configured to supply a program voltage to a word line coupled to the selected memory cell among the plurality of memory cells during the program section. The peripheral circuit further supplies a detrap voltage to the cell string during the detrap section and supplies a verify voltage to the word line during the verify section.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: March 19, 2019
    Assignee: SK hynix Inc.
    Inventor: Hee Youl Lee
  • Patent number: 10236058
    Abstract: A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL to the memory cell, continuing the writing of the data in the memory cell by changing the value of the write control voltage VBL in response to an advent of a first write state of the memory cell and inhibiting any operation of writing a data to the memory cell by further changing the value of the write control voltage VBL to Vdd in response to an advent of a second write state of the memory cell.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: March 19, 2019
    Assignees: Toshiba Memory Corporation, SanDisk Technologies LLC
    Inventors: Tomoharu Tanaka, Jian Chen
  • Patent number: 10229749
    Abstract: A nonvolatile memory storage system includes a plurality of memory cells and a memory controller configured to transmit a read command to a nonvolatile memory device based on a plurality of read voltages. The nonvolatile memory device performs a first read operation on a first level among the N levels based on a first read voltage among the plurality of read voltages, counts the number of on-cells that respond to the first read voltage among the plurality of memory cells, and adjusts a level of a second read voltage to be used to perform a second read operation on the first level or a second level among the N levels among the plurality of read voltages according to a comparison result of the counted number of on-cells and the number of reference cells.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: March 12, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun Chu Oh, Pilsang Yoon, Jun Jin Kong, Hong Rak Son, Dongsup Jin
  • Patent number: 10228713
    Abstract: A current mirror includes a first pair of transistors, wherein gates of the first pair of transistors are connected together, and a second pair of transistors coupled to the first pair of transistors. Gates of the second pair of transistors are connected together. A first resistive device is coupled across a drain and a source of one of the transistors of the second pair of transistors. A second resistive device is coupled across a drain and a source of the other transistor of the second pair of transistors. The first pair of transistors are configured to operate in weak inversion at an input current to the current mirror within a first current range and the second pair of transistors are configured to operate in strong inversion at an input current within a second current range.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: March 12, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Michael Ryan Hanschke, Salvatore Giombanco, Timothy Bryan Merkin
  • Patent number: 10229740
    Abstract: An apparatus of a memory system and an operating method thereof include: memory blocks, each of the memory blocks includes strings, each of the stings has flash cells and select gates thereon, wherein the select gates of each of the strings with a same index number in each of the memory blocks are connected with each other, in each of the memory blocks, the strings are divided into groups, each of the groups includes at least one string, and each of the groups has own read counts management thereof.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: March 12, 2019
    Assignee: SK hynix Inc.
    Inventors: Yu Cai, Haibo Li, Fan Zhang, June Lee
  • Patent number: 10224103
    Abstract: In an example, a memory device has a first string of memory cells selectively connected to a first data line, a second string of memory cells selectively connected to a second data line, and a transistor that selectively connects the first data line to the second data line, thereby permitting connecting the first and second data lines in series before programming or sensing memory cells of the first and second strings of memory cells.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: March 5, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Toru Tanzawa
  • Patent number: 10224110
    Abstract: A memory card is provided to include a substrate having two pairs of edges facing each other, a plurality of first row terminals that are arranged adjacent to an edge at an insertion side of the substrate and include a first voltage power terminal for applying a first voltage and a first ground terminal, a plurality of second row terminals that are spaced farther apart from the edge at the insertion side than the plurality of first row terminals and include a second voltage power terminal for applying a second voltage and first data terminals, and a plurality of third row terminals that are spaced farther apart from the edge at the insertion side than the plurality of second row terminals and include second data terminals.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: March 5, 2019
    Assignee: Samsung Electroncis Co., Ltd.
    Inventors: Seok-jae Han, Il-mok Kang, Gwang-man Lim, Seok-heon Lee, Jae-bum Lee
  • Patent number: 10210939
    Abstract: A data management method for a solid state storage device is provided. The solid state storage device includes a memory cell array. The memory cell array is divided into first-portion logical blocks and second-portion logical blocks. The data management method includes the following steps. Firstly, a write data of plural pages from a host are stored into a first logical block of the first-portion logical blocks. Then, a specified operation is performed on the write data of the plural pages, so that a parity data is acquired. Then, the parity data is stored into a second logical block of the second-portion logical blocks.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: February 19, 2019
    Assignees: LITE-ON ELECTRONICS (GUANGZHOU) LIMITED, LITE-ON TECHNOLOGY CORPORATION
    Inventors: Ya-Ping Pan, Po-Yen Chen, Min-I Hung