Particular Biasing Patents (Class 365/185.18)
  • Patent number: 10923193
    Abstract: Provided herein may be a memory device including a voltage generating circuit. The memory device may include a memory block including a channel layer formed between junctions included in a well, and a source select line, word lines, and drain select lines that are sequentially stacked on the well while enclosing the channel layer, a first voltage source configured to generate a first operating voltage to be applied to the well during a program operation or an erase operation, and a second voltage source configured to generate a second operating voltage to be applied to source lines that are coupled to the junctions during the program operation or the erase operation.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: February 16, 2021
    Assignee: SK hynix Inc.
    Inventor: Hee Youl Lee
  • Patent number: 10923209
    Abstract: A semiconductor memory device that can reduce power consumption and precisely perform a power-down operation while a testing operation is underway is provided. A flash memory of the invention has a low-power voltage-detection circuit, a high-precision voltage-detection circuit, and a controller. The low-power voltage-detection circuit detects the supply voltage falling to a constant voltage. The high-precision voltage-detection circuit detects the supply voltage falling to the constant voltage. The controller selects the high-precision voltage-detection circuit when the internal circuit is being tested, and it selects the low-power voltage-detection circuit when the internal circuit is not undergoing a test. The controller responds to the detection result from the low-power voltage-detection circuit or the high-precision voltage-detection circuit by performing a power-down operation.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: February 16, 2021
    Assignee: WINBOND ELECTRONICS CORP.
    Inventor: Naoaki Sudo
  • Patent number: 10910394
    Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: February 2, 2021
    Assignee: Renesas Electronics Corporation
    Inventors: Tsutomu Okazaki, Akira Kato, Kan Yasui, Kyoya Nitta, Digh Hisamoto, Yasushi Ishii, Daisuke Okada, Toshihiro Tanaka, Toshikazu Matsui
  • Patent number: 10910366
    Abstract: A three-dimensional stacked integrated circuit (3D SIC) for implementing an artificial neural network (ANN) having a memory die having an array of memory partitions. Each partition of the array of memory partitions is configured to store parameters of a set of neurons. The 3D SIC also has a processing logic die having an array of processing logic partitions. Each partition of the array of processing logic partitions is configured to: receive input data, and process the input data according to the set of neurons to generate output data.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: February 2, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Tony M. Brewer
  • Patent number: 10892269
    Abstract: According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: January 12, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Yoshiaki Fukuzumi, Hideaki Aochi, Mie Matsuo, Kenichiro Yoshii, Koichiro Shindo, Kazushige Kawasaki, Tomoya Sanuki
  • Patent number: 10885984
    Abstract: A memory device comprising a semiconductor substrate in which a memory cell region and a peripheral circuitry region are defined, wherein the memory cell region has a plurality of non-volatile memory cells arranged in one or more arrays and the peripheral circuitry region has at least one sense amplifier region comprised of at least one low voltage transistor. Further, a deep N-well region is formed in the substrate, wherein the memory cell region and the peripheral circuitry region are placed on the deep N-well region such that, in the event that a high erase voltage (VERA) is applied to the memory cell region during an erase operation, the high erase voltage is applied to all terminals of the at least one low voltage resistor, thereby protecting the low voltage transistor by preventing it from experiencing a large voltage difference between its terminals.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: January 5, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Hiroki Yabe, Koichiro Hayashi, Takuya Ariki, Yuki Fujita, Naoki Ookuma, Kazuki Yamauchi, Masahito Takehara, Toru Miwa
  • Patent number: 10886297
    Abstract: A plurality of semiconductor layers have longitudinally a first direction, have a peripheral area surrounded by the plurality of control gate electrodes, and are arranged in a plurality of rows within the laminated body. A controller controls a voltage applied to the control gate electrodes and bit lines. The controller, during a writing operation, applies a first voltage to a first bit line connected to the semiconductor layer positioned in a first row closer to the insulation separating layer, and applies a second voltage larger than the first voltage to a second bit line connected to the semiconductor layer positioned in a second row positioned further from the insulation separating layer with respect to the first row, among the plurality of rows.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: January 5, 2021
    Assignee: Toshiba Memory Corporation
    Inventor: Yasuhiro Shimura
  • Patent number: 10885983
    Abstract: A nonvolatile memory device includes a first memory stack including first memory cells vertically stacked on each other, a second memory stack including memory cells vertically stacked on each other, and a control logic configured to set a voltage level of a second voltage applied for a second memory operation to one of the second memory cells in the second memory stack based on a first voltage applied to one of the first memory cells in the first memory stack in a first memory operation. The second memory stack is vertically stacked on the first memory stack. Cell characteristics of the one of the first memory cells is determined using the first voltage.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: January 5, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong-chul Park, Youn-yeol Lee, Seul-bee Lee, Kyung-sub Lim
  • Patent number: 10885993
    Abstract: A method of operating a semiconductor memory device includes dummy-programming selected memory cells representing all the memory cells to be programmed for a programming operation. The method also includes determining as a first group of memory cells those selected memory cells having threshold voltages less than or equal to a reference threshold voltage and determining as a second group of memory cells those selected memory cells having threshold voltages greater than the reference threshold voltage. The method further includes programming the selected memory cells by applying a first bit line voltage to the memory cells of the first group, applying a second bit line voltage different from the first bit line voltage to the memory cells of the second group, and applying a same program pulse to the memory cells of the first and second groups.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: January 5, 2021
    Assignee: SK hynix Inc.
    Inventor: Hee Youl Lee
  • Patent number: 10886287
    Abstract: One illustrative MPT device disclosed herein includes an active region and an inactive region, isolation material positioned between the active region and the inactive region, the isolation material electrically isolating the active region from the inactive region, and an FG MTP cell formed in the active region. In this example, the FG MTP cell includes a floating gate, wherein first, second and third portions of the floating gate are positioned above the active region, the inactive region and the isolation material, respectively, and a control gate positioned above at least a portion of the inactive region, wherein the control gate is positioned above an upper surface and adjacent opposing sidewall surfaces of at least a part of the second portion of the floating gate.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: January 5, 2021
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Xuan Anh Tran, Sunil Kumar Singh, Shyue Seng Tan
  • Patent number: 10872673
    Abstract: A semiconductor memory cell includes a memory cell, a word line and a source line both connected to the memory cell, and a control circuit. During a read operation on the memory cell, the control circuit applies a first voltage to the word line, applies a second voltage greater than the first voltage to the word line, and then applies a third voltage which is greater than the first voltage and smaller than the second voltage to the word line. During the read operation on the memory cell, the control circuit also applies a fourth voltage to the source line according to a timing at which the second voltage is applied to the word line, and then applies a fifth voltage smaller than the fourth voltage to the source line.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: December 22, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Toshifumi Watanabe, Naofumi Abiko, Mario Sako
  • Patent number: 10872674
    Abstract: A voltage generation system might include a resistive voltage divider having a first resistance connected between its output and a first feedback node and a second resistance connected between the first feedback node and a first voltage node, a capacitive voltage divider having a first capacitance connected between its output and a second feedback node and a second capacitance connected between the second feedback node and the first voltage node, a comparator having an input connected to the second feedback node, and a voltage generation circuit configured to generate a voltage level at its output responsive to an output of the comparator and to a clock signal, wherein the first feedback node is selectively connected to the second feedback node and selectively connected to a second voltage node, wherein the first resistance is selectively connected to the first feedback node, and wherein the second resistance is selectively connected to the first voltage node.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: December 22, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Manan Tripathi, Michele Piccardi, Xiaojiang Guo
  • Patent number: 10872666
    Abstract: Methods, systems, and devices for source line configurations for a memory device are described. In some cases, a memory cell of the memory device may include a first transistor having a floating gate for storing a logic state of the memory cell and a second transistor coupled with the floating gate of the first transistor. The memory cell may be coupled with a word line, a digit line, and a source line. During a write operation, the source line may be clamped to the digit line using one or more memory cells in the memory device. During a read operation, the source line may be grounded using one or more memory cells in the memory device.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: December 22, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Richard E. Fackenthal
  • Patent number: 10872985
    Abstract: A non-volatile memory cell and array structure is disclosed situated within a high voltage region of an integrated circuit. The cell utilizes capacitive coupling based on an overlap between a gate and a drift region to impart a programming voltage. Programming is effectuated using a drain extension which can act to inject hot electrons. The cell can be operated as a one-time programmable (OTP) or multiple-time programmable (MTP) device. The fabrication of the cell relies on processing steps associated with high voltage devices, thus avoiding the need for additional masks, manufacturing steps, etc.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: December 22, 2020
    Assignee: JONKER LLC
    Inventor: David Liu
  • Patent number: 10868037
    Abstract: According to one embodiment, a semiconductor memory device includes: a first interconnecting layer; a first signal line; a first memory cell that stores first information between the first interconnecting layer and the first signal line; second to fourth interconnecting layers provided above the first interconnecting layer; fifth to seventh interconnecting layers disposed apart from the second to fourth interconnecting layers; a second signal line coupled to the first signal line; a third signal line coupled to the first and second signal lines and the sixth interconnecting layer; and, first to fifth transistors.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: December 15, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Fumitaka Arai, Masakazu Goto, Masaki Kondo, Keiji Hosotani, Nobuyuki Momo
  • Patent number: 10861573
    Abstract: Apparatuses and methods related to a memory system including a controller and an array of memory cells. An example apparatus can include a controller configured to receive operational characteristics of an array of memory cells based on prior operations performed by the array of memory cells, determine a set of trim settings for the array of memory cells based on the operational characteristics of the array of memory cells, wherein the set of trim settings are associated with desired operational characteristics for the array of memory cells, and send the set of trim settings to the array of memory cells.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: December 8, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Aswin Thiruvengadam, Daniel L. Lowrance, Peter Feeley
  • Patent number: 10861558
    Abstract: A memory device includes an erase operation controller for performing an erase operation on a memory block; an erase suspend count manager for managing an erase suspend count representing a number of times the erase operation is suspended until the erase operation on the memory block is completed; and a program parameter value determiner for determining a parameter value to be used for a program operation on the memory block, based on the erase suspend count.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: December 8, 2020
    Assignee: SK hynix Inc.
    Inventor: Se Chang Park
  • Patent number: 10861566
    Abstract: A semiconductor memory device includes first and second memory cell transistors between first and second select transistors, third and fourth memory cell transistors between third and fourth select transistors, a first word line for first and third memory cell transistors, a second word line for second and fourth memory cell transistors, first to fourth selection gate lines respectively for first through fourth select transistors, a bit line, and a source line. During a read operation, while a voltage applied to the second word line is boosted, voltages applied to the first word line and the third and fourth selection gate line are also boosted, after which the voltage applied to the first word line is lowered, and the third and fourth selection gate lines are discharged. After the time the third and fourth selection gate lines are discharged, voltages applied to the bit line and the source line are boosted.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: December 8, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Takeshi Hioka
  • Patent number: 10854745
    Abstract: A semiconductor memory cell comprising an electrically floating body having two stable states is disclosed. A method of operating the memory cell is disclosed.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: December 1, 2020
    Assignee: Zeno Semiconductor, Inc.
    Inventors: Jin-Woo Han, Dinesh Maheshwari, Yuniarto Widjaja
  • Patent number: 10854296
    Abstract: A semiconductor device includes strings each having a plurality of memory cells. The strings are coupled between a common source line and a bit line. A method of operating the semiconductor device includes applying a pre-program voltage to a selected word line coupled to a selected memory cell and to an unselected word line coupled to an unselected memory cell adjacent to the selected memory cell among the plurality of memory cells. The method further includes applying a first program voltage to the selected word line.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: December 1, 2020
    Assignee: SK hynix Inc.
    Inventors: Ji Hyun Seo, Bong Yeol Park, Hee Youl Lee, Han Soo Joo
  • Patent number: 10847232
    Abstract: A semiconductor memory device includes a differential waveform shaping circuit including first and waveform shaping circuits connected in parallel. The first waveform shaping circuit has a first inverting amplifier, and two inverters connected in series. The first inverting amplifier inverts and differentially amplifies an input signal having a rectangular waveform. Then, the output of the first inverting amplifier is passed through the two inverters. The second waveform shaping circuit has a first inverter, a second inverting amplifier, and a second inverter connected in series. The second inverting amplifier inverts and differentially amplifies the output signal from the first invertor, and the second inverter inverts the output signal from the second inverting amplifier. The differential waveform shaping circuit generates an output signal by averaging the output signal from the first waveform shaping circuit and the output signal from the second waveform shaping circuit.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: November 24, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kei Shiraishi, Masaru Koyanagi, Mikihiko Ito, Yumi Takada, Yasuhiro Hirashima, Satoshi Inoue, Kensuke Yamamoto, Shouichi Ozaki, Taichi Wakui, Fumiya Watanabe
  • Patent number: 10847523
    Abstract: Roughly described, the invention involves a device including a memory chip having a memory array, bit lines in communication with data carrying nodes of the memory array, and word lines in communication with certain gate control nodes of the memory array. The memory chip has bonding pads formed on an interconnect surface at respective memory chip interconnect locations. Each of the bit lines and each of the word lines of the memory array includes a respective landing pad in a conductive layer of the chip, and these landing pads connected via redistribution conductors to respective ones of the set of memory chip bonding pads. The redistribution conductors for the bit lines have a positive average lateral signal travel distance which is less than that of the redistribution conductors for the word lines.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: November 24, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Teng-Hao Yeh, Chih-Wei Hu, Hang-Ting Lue
  • Patent number: 10847241
    Abstract: A method performed in a computing device. The computing device is configured to store data and retrieve stored data from storage. The computing device further stores parameters for use in soft decoding stored data. The method comprises retrieving data from storage using soft decoding based on the stored soft decoding parameters, using retrieved, soft decoded data to estimate updates of one or more of the parameters for soft decoding and storing the updates.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: November 24, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Memory Corporation
    Inventor: Hachem Yassine
  • Patent number: 10839926
    Abstract: A semiconductor memory device includes a memory cell array including first and second groups of memory strings respectively coupled to first and second groups of bit-lines, wherein the first and second groups of memory strings respectively include first and second groups of selection transistor cells; a peripheral circuit suitable for applying a program voltage, and performing program verification operation for the memory cell array; and a control logic suitable for controlling the peripheral circuit to perform a first program verification operation for the first group of selection transistor cells and a second program verification operation for the second group of selection transistor cells.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: November 17, 2020
    Assignee: SK hynix Inc.
    Inventor: Eun Young Park
  • Patent number: 10839918
    Abstract: Boost converter in memory chip. A non-volatile memory including an in-chip boost converter includes: a first memory structure defines control circuitry disposed on a first substrate, and a first metal layers disposed adjacent the control circuitry, where the first metal layer couples elements of the control circuitry; and a second memory structure defines a memory array disposed on a second substrate, and a second metal layer disposed adjacent the memory array, where the first and second metal layers are bonded together by a permanent physical bond formed between the first and second metal layers; and a boost converter defining an inductor disposed in the first and second metal layers, and a transistor circuit disposed in the control circuitry. The non-volatile memory, where the inductor further defines a first terminal coupled to a voltage source, and a second terminal coupled to a load by way of a transistor circuit.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: November 17, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Hardwell Chibvongodze, Masatoshi Nishikawa
  • Patent number: 10830731
    Abstract: A sensor device may include a substrate, and first and second semiconductor structures arranged over the substrate. The first semiconductor structure may be an ion-sensitive field effect transistor and may include a floating gate, and a sensing element electrically coupled to the floating gate. The second semiconductor structure may be capacitively coupled to the first semiconductor structure, and may include a first diffusion region and a second diffusion region having opposite polarity type dopants, and a channel region arranged therebetween. The second semiconductor structure may be configured to receive a bias voltage to tune an electrical characteristic of the first semiconductor structure through the first diffusion region and the second diffusion region and the channel region. In some embodiments, the substrate may be a crystalline-on-insulator substrate which may be coupled to a back gate bias to reduce an effective total capacitance of the ISFET and further improve the coupling ratio.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: November 10, 2020
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Xinshu Cai, Shyue Seng Tan, Eng Huat Toh
  • Patent number: 10832780
    Abstract: A method can be used for programming a group of memory cells of a non-volatile memory device in a programming window that has a duration longer than a programming duration of a memory cell. The programming window is subdivided into a number of time intervals. A programming profile that was determined by simulation while taking into account a reference criterion is retrieved. The programming profile includes, for each time interval, a maximum number of memory cells that can be triggered for programming within each time interval. The memory device is programmed in the programming window, interval-wise, using the programming profile.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: November 10, 2020
    Assignees: STMICROELECTRONICS (ALPS) SAS, STMICROELECTRONICS (GRENOBLE2) SAS
    Inventors: Leonardo Valencia Rissetto, Elise Le Roux, Christophe Forel
  • Patent number: 10826752
    Abstract: A method for determining degradation in performance of an electronic device connected to a communication network for an aerial vehicle includes monitoring, by one or more computing device(s), communications on the communication network during a validation period. The method further includes generating, by the computing device(s), a baseline operating profile of the electronic device based, at least in part, on the communications monitored during the validation period. In addition, the method includes monitoring, by the computing device(s), communications on the communication network during a post-validation period. The method further includes determining, by the computing device(s), a present operating profile of the electronic device based, at least in part, on the communications monitored during the post-validation period.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: November 3, 2020
    Assignee: GE Aviation Systems Limited
    Inventors: Stefan Alexander Schwindt, Barry Foye
  • Patent number: 10818686
    Abstract: According to one embodiment, a semiconductor memory device includes: a substrate; a first conductive layer arranged above the substrate; a stacked body arranged on the first conductive layer with a plurality of dielectric layers and a plurality of second conductive layers being alternately stacked; a pillar-shaped channel extending in a stacking direction of the stacked body, penetrating through the stacked body, and protruding into the first conductive layer; and a memory layer covering a side surface of the channel, in which a bottom surface of the channel and the side surface of the channel protruding into the first conductive layer are in contact with the first conductive layer, and in which the first conductive layer includes: an upper layer; and a lower layer having a protrusion penetrating through the upper layer.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: October 27, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Shunsuke Hazue
  • Patent number: 10818366
    Abstract: A storage device with a charge trapping (CT) based memory may include improved data retention performance. Data retention problems, such as charge loss in CT memory may increase for a particular programmed state when a neighboring state is at erased state. Modifying the erase state with post write erase conditioning (PWEC) by pushing up deeply erased states can reduce the lateral charge movement and improve high temperature data retention. In particular, the erase state may be reprogrammed such that the erase distribution is tighter with a higher voltage.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: October 27, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Mohan Vamsi Dunga, Changyuan Chen, Biswajit Ray
  • Patent number: 10818685
    Abstract: A non-volatile storage apparatus comprises a non-volatile memory structure and an I/O interface. A portion of the memory die is used as a pool capacitor for the I/O interface.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: October 27, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Mohan Dunga, James Kai, Venkatesh P. Ramachandra, Piyush Dak, Luisa Lin, Masaaki Higashitani
  • Patent number: 10802736
    Abstract: Systems and method are directed to Universal Flash Storage (UFS) memory system configured to support deep power-down modes wherein the UFS memory system is not required to be responsive to commands received from a host device coupled to the UFS memory system. Correspondingly, in the deep power-down modes, a link or interface between the UFS memory system and the host device may also be powered down. The UFS memory system may enter the deep power-down modes based on a command received from the host device or a hardware reset assertion, and exit the deep power-down modes based on a hardware reset de-assertion or power cycling. While in deep power-down modes, the power consumption of the UFS memory device is substantially lower than the power consumption of the UFS memory device in conventional power modes.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: October 13, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Hyunsuk Shin, Todd Christopher Reynolds, Hung Vuong
  • Patent number: 10802961
    Abstract: An apparatus and a method for accessing a plurality of memory blocks is disclosed. The An apparatus comprises: a memory circuit configured to store a recording table, wherein the recording table corresponds to quality index of the plurality of memory blocks; and a control circuit configured to group the plurality of memory blocks to a first memory group and a second memory group according to the quality index; to enable to access the memory blocks in the first memory group, and to disable to access the memory blocks in the second memory group.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: October 13, 2020
    Assignee: RAYMX MICROELECTRONICS CORP.
    Inventors: Yen-Chung Chen, Chih-Ching Chien, Li-Chun Huang, Han-Ting Tsai, Wei-Ren Hsu
  • Patent number: 10803947
    Abstract: A nonvolatile memory device performs a read operation comprising first and second intervals. In the first interval the device applies a turn-on voltage to string selection lines and ground selection lines connected to the string selection transistors and the ground selection transistors, respectively. In the second interval, the device applies a turn-off voltage to unselected string selection lines and unselected ground selection lines while continuing to apply the turn-on voltage to a selected string selection line and a selected ground selection line. In both the first and second intervals, the device applies a first read voltage to a selected wordline connected to memory cells to be read by the read operation and applying a second read voltage to unselected wordlines among connected to memory cells not to be read by the read operation.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: October 13, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Wan Nam, Won-Taeck Jung
  • Patent number: 10796768
    Abstract: It is to optimize the initial threshold voltages of each memory area in a semiconductor memory device including a plurality of memory areas. A semiconductor memory device according to the embodiment includes a first memory area for storing data and a second memory area for storing the information related to the first memory area. In the respective memory cells arranged in the first and the second memory areas, the initial threshold voltages of the memory cells arranged in the second memory area are designed to be higher than those of the memory cells arranged in the first memory area.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: October 6, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tomoya Saito, Naoki Takizawa
  • Patent number: 10790028
    Abstract: An AND type flash memory includes a memory cell array, a plurality of page buffers and a plurality of voltage shifting circuits. The memory cell array is coupled to a plurality of bits lines and source lines. The page buffers are respectively coupled to the bit lines through a plurality of switches, and respectively provides a plurality of control signals. The control signals are transited between a first voltage and a reference voltage. The voltage shifting circuits respectively receive the control signals, generates a plurality of driving signals by shifting voltage values of the control signals, and provides the driving signals to the bit lines. Wherein, the driving signals are transited between a second voltage and the reference voltage, the second voltage is larger than the first voltage.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: September 29, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Teng-Hao Yeh, Hang-Ting Lue, Lee-Yin Lin
  • Patent number: 10782920
    Abstract: A data access method, a memory storage apparatus and a memory control circuit unit are provided. The memory storage apparatus includes a rewritable non-volatile memory module and the memory control circuit unit for controlling the rewritable non-volatile memory module. The data access method includes: receiving an access command; detecting a temperature of the memory storage apparatus; determining whether the temperature of the memory storage apparatus is lower than a first threshold; if the temperature of the memory storage apparatus is lower than the first threshold, performing a dummy access command or adjusting an operating voltage. The data access method further includes performing the access command after the dummy access command is performed or the operating voltage is adjusted.
    Type: Grant
    Filed: November 12, 2018
    Date of Patent: September 22, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 10777279
    Abstract: A non-volatile memory device includes a substrate; a memory cell array on the substrate; a control logic circuit configured to output an erase enable signal for controlling an erase operation with respect to the memory cell array; a substrate bias circuit configured to, in response to the erase enable signal, output a first target voltage to the substrate as a substrate bias voltage during a first delay time and, after the first delay time, output the substrate bias voltage to the substrate while gradually increasing a level of the substrate bias voltage to that of an erase voltage having a higher level than the first target voltage; and a row decoder configured to apply a ground voltage to the ground select line based on control of the control logic circuit during the first delay time.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: September 15, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun-Gyu Lee, Sung-Whan Seo
  • Patent number: 10777292
    Abstract: The present disclosure includes apparatuses and methods related to selectable trim settings on a memory device. An example apparatus can store a number of sets of trim settings and select a particular set of trims settings of the number of sets of trim settings based on desired operational characteristics for the array of memory cells.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: September 15, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Aswin Thiruvengadam, Daniel L. Lowrance, Peter Feeley
  • Patent number: 10777568
    Abstract: A semiconductor device that has a split gate charge trapping memory cell having select and memory gates of different heights is presented herein. In an embodiment, the semiconductor device also has a low voltage transistor and a high voltage transistor. In one embodiment, the gates of the transistors are the same height as the select gate. In another embodiment, the gates of the transistors are the same height as the memory gate.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: September 15, 2020
    Assignee: Cypress Semiconductor Corporation
    Inventors: Chun Chen, Mark Ramsbey, Shenqing Fang
  • Patent number: 10770150
    Abstract: In a method of reading initialization information from a non-volatile memory device, when power-up is detected, the non-volatile memory device divides a source voltage to generate a low read pass voltage which is to be provided to unselected word lines in an initialization information read operation. The low read pass voltage is set as at least one voltage between a ground voltage and the source voltage. The non-volatile memory device allows the source voltage not to be pumped in the initialization information read operation, based on the power-up. In the initialization information read operation, the non-volatile memory device provides the low read pass voltage to the unselected word lines and provides a read voltage to a selected word line to read initialization information stored in the memory cells.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: September 8, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Youn-Yeol Lee, Wook-Ghee Hahn
  • Patent number: 10761980
    Abstract: The present disclosure includes apparatuses and methods related to determining trim settings on a memory device. An example apparatus can determine a set of trim settings for the array of memory cells based on the operational characteristics of the array of memory cells, wherein the set of trim settings are associated with desired operational characteristics for the array of memory cells.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: September 1, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Aswin Thiruvengadam, Daniel L. Lowrance, Peter Feeley
  • Patent number: 10746691
    Abstract: An ion-sensitive field effect transistor (ISFET) is provided that has enhanced sensitivity due to an increased passivation capacitance, Cp. The increased Cp is obtained by increasing the surface area of the passivation layer by forming particles (metallic, semiconductor or dielectric) in a micro-well, and by embedding the particles in an electrically conductive liner that is formed under the passivation layer and within the micro-well.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: August 18, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Chanro Park, Ruilong Xie, Juntao Li
  • Patent number: 10748926
    Abstract: According to one embodiment, a semiconductor memory device includes the following configuration. A second word line is provided above a first word line on a substrate. A third word line is provided above the second word line. A semiconductor layer includes a first part that passes through the first word line, a second part that passes through the second and the third word lines, and is provided above the first part, and a joint provided between the first and second parts. When a write operation is performed on a memory cell of the third word line, prior to applying a write voltage to the third word line, a first voltage is applied to a bit line, a second voltage is applied to the third word line, and a third voltage higher than the second voltage is applied to the second word line.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: August 18, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Kota Nishikawa, Hiroshi Tsubouchi, Kenri Nakai
  • Patent number: 10741248
    Abstract: A global word line decoder may include a voltage switching unit and a plane switching unit. The voltage switching unit may decode a plurality of operating voltages to output a selected voltage and an unselected voltage, and the plane switching unit may receive the selected voltage and the unselected voltage, and decode the selected voltage and the unselected voltage to output decoded voltages to a global word line coupled to a selected plane, among a plurality of planes. The selected voltage may include a first pre-decoded voltage and a second pre-decoded voltage, and the plane switching unit may swap and output the first pre-decoded voltage and the second pre-decoded voltage according to a position of a selected word line.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: August 11, 2020
    Assignee: SK hynix Inc.
    Inventor: Moon Soo Sung
  • Patent number: 10734088
    Abstract: A CMOS anti-fuse cell is disclosed. In one aspect, an apparatus includes an N? well and an anti-fuse cell formed on the N? well. The anti-fuse cell includes a drain P+ diffusion deposited in the N? well, a source P+ diffusion deposited in the N? well, and an oxide layer deposited on the N? well and having an overlapping region that overlaps the drain P+ diffusion. A control gate is deposited on the oxide layer. A data bit of the anti-fuse cell is programmed when a voltage difference between the control gate and the drain P+ diffusion exceeds a voltage threshold of the oxide layer and forms a leakage path from the control gate to the drain P+ diffusion. The leakage path is confined to occur in the overlapping region.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: August 4, 2020
    Assignee: NEO Semiconductor, Inc.
    Inventor: Fu-Chang Hsu
  • Patent number: 10727249
    Abstract: Some embodiments include a memory cell which has, in the following order; a control gate, charge-blocking material, charge-trapping material, a first oxide, a charge-passage structure, a second oxide, and channel material. The charge-passage structure has a central region sandwiched between first and second regions. The central region has a lower probability of trapping charges and/or a lower rate of trapping charges than the first and second regions. Some embodiments include an integrated structure having a vertical stack of alternating conductive levels and insulative levels, and having a charge-passage structure extending vertically along the vertical stack. Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and wordline levels, and having a charge-passage structure extending vertically along the vertical stack.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: July 28, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Chris M. Carlson, M. Jared Barclay
  • Patent number: 10720219
    Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cells, a word line connected in common to gates of the memory cells, and a control circuit configured to execute a read operation on the memory cells by applying a first read voltage to the word line to determine for each of the memory cells whether or not the memory cell has a threshold voltage that is below the first read voltage and a second read voltage to the word line to determine for each of the memory cells whether or not the memory cell has a threshold voltage that is below the second read voltage. The control circuit determines the first read voltage by applying at least first to third voltages to the word line, and determines the second read voltage based on the first read voltage.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: July 21, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Yoshikazu Harada
  • Patent number: 10718820
    Abstract: The embodiments of the present disclosure disclose a DC/DC test system and a method. In the solution, based on a test system composed of a test host, a main control unit, a DC/DC unit, a programmable power supply, an input monitoring unit, an output monitoring unit and a load unit, the efficiency test of the DC/DC unit can be automatically realized, the test of linear adjustment rate and load regulation rate can be realized, and the test efficiency can be improved.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: July 21, 2020
    Assignees: BOE Technology Group Co., Ltd., Chengdu BOE Optoelectronics Technology Co., Ltd.
    Inventor: Dongxiao Shan
  • Patent number: 10714187
    Abstract: A memory control device includes a memory and a controller. The memory includes a plurality of memory blocks. The controller is coupled to the memory and configured to select a first memory block from the memory blocks and program data into the first memory block. When the memory control device is deactivated and re-activated, the controller is further configured to read a voltage distribution of the first memory block to determine a deactivation interval, and determine a reference time according to the deactivation interval and an initial time, and the voltage distribution of the first memory block correspond to the data.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: July 14, 2020
    Assignee: RAYMX MICROELECTRONICS CORP.
    Inventors: Yi-Lin Hsieh, Jing-Long Xiao, Cheng-Yu Chen, Wang-Sheng Lin