Particular Biasing Patents (Class 365/185.18)
  • Patent number: 11328775
    Abstract: A ternary content addressable memory and a memory cell thereof are provided. The ternary content addressable memory cell includes a first transistor and a second transistor. The first transistor has a gate to receive a selection signal. A first end of the first transistor is coupled to a match line. A second end of the first transistor is coupled to a source line. The second transistor has a gate to receive an inverted selection signal. A first end of the second transistor is coupled to the match line. A second end of the second transistor is coupled to the source line. The first and second transistors have charge storage structures.
    Type: Grant
    Filed: October 7, 2020
    Date of Patent: May 10, 2022
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Po-Hao Tseng, Ming-Hsiu Lee, Feng-Min Lee
  • Patent number: 11322209
    Abstract: A memory device includes a memory array comprising a plurality of planes, a plurality of voltage generation systems, and a controller. Each voltage generation system is electrically coupled to a corresponding plane. The controller is configured to turn on and warm up each voltage generation system of the plurality of voltage generation systems in response to a first command to access any plane of the plurality of planes and turn off and slowly discharge each voltage generation system of the plurality of voltage generation systems into an idle state in response to no commands being processed. In response to receiving a subsequent command to access any plane of the plurality of planes prior to the voltage generation systems reaching the idle state, a warm up period of the plurality of voltage generation systems is reduced.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: May 3, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Michele Piccardi, Kalyan C. Kavalipurapu, Xiaojiang Guo
  • Patent number: 11315651
    Abstract: A non-volatile memory device includes a first and a second memory regions including first and second memory cells and first and second analog circuits, respectively; a control logic circuit determining on/off states of the analog circuits, and converting an external power supply voltage into an internal operating voltage for operation of each of the memory cells; and input/output circuit selecting an input/output memory region for performing input/output of data using the internal operating voltage, wherein input/output of data for the first and second memory cells are sequentially performed, and at least one of the each of the first and second analog circuits are turned on together while the input/output of data for the first memory cells is performed.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: April 26, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Bongkil Jung, Dongjin Shin, Manjae Yang, Byungsun Lee, Dongsu Jang
  • Patent number: 11309324
    Abstract: An illustrative device disclosed herein includes a first memory cell comprising a first memory gate positioned above an upper surface of a semiconductor substrate and a second memory cell comprising a second memory gate positioned above the upper surface of the semiconductor substrate. In this example, the device also includes a conductive word line structure positioned above the upper surface of the semiconductor substrate between the first and second memory gates, wherein the conductive word line structure is shared by the first and second memory cells.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: April 19, 2022
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Yongshun Sun, Eng Huat Toh, Shyue Seng Tan, Kiok Boone Elgin Quek
  • Patent number: 11295822
    Abstract: The present disclosure includes apparatuses, methods, and systems for multi-state programming of memory cells. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to program a memory cell of the plurality of memory cells to one of four possible data states by applying a first voltage pulse to the memory cell wherein the first voltage pulse has a first polarity and a first magnitude, and applying a second voltage pulse to the memory cell wherein the second voltage pulse has a second polarity and a second magnitude, and the second voltage pulse is applied for a shorter duration than the first voltage pulse.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: April 5, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Karthik Sarpatwari, Nevil N. Gajera
  • Patent number: 11289500
    Abstract: A memory device comprises a peripheral circuit region including a first substrate and circuit elements on the first substrate, the circuit elements including a row decoder, and a memory cell region including a cell array region and a cell contact region, wherein the cell array region includes wordlines, stacked on a second substrate on the peripheral circuit region, and channel structures extending in a direction perpendicular to an upper surface of the second substrate and penetrating the wordlines, wherein the cell contact region includes cell contacts connected to the wordlines and on both sides of the cell array region in a first direction parallel to the upper surface of the second substrate, the cell contacts including a first cell contact region and a second cell contact region, the first and second cell contact regions having different lengths to each other in the first direction, wherein each of the first and second cell contact regions includes first pads having different lengths than each other in
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: March 29, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyunghwa Yun, Pansuk Kwak, Chanho Kim, Dongku Kang
  • Patent number: 11281400
    Abstract: Systems, apparatus, and methods are disclosed comprising receiving temperature information corresponding to a write temperature of at least one of multiple pages of non-volatile memory cells of a group of non-volatile memory cells, determining a statistical measure of temperature information for the group non-volatile memory cells using the received temperature information, and storing the determined statistical measure of temperature information for the group of non-volatile memory cells. The stored determined statistical measure of temperature information can be used to optimize or improve one or more storage system operations.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: March 22, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Giuseppe Cariello
  • Patent number: 11270767
    Abstract: A non-volatile memory device having processing logic embedded within a memory bank of the non-volatile memory device is disclosed herein. By way of example, commands for controlling the processing logic can be exposed to a host device, enabling the host device to activate processing capacity of the memory bank in conjunction with a memory operation. The processing capacity can be directed by a data command, transmitted by the host device, at read or write data identified by the memory operation. Read data can be processed by the memory bank before being output onto a data interface connected to the memory bank. Likewise, write data received at the memory bank can be processed in conjunction with storing the write data in the non-volatile memory device. A disclose memory device can therefore implement internal processing in conjunction with reading or writing data to a memory device comprising respective banks of two-terminal non-volatile memory.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: March 8, 2022
    Assignee: Crossbar, Inc.
    Inventor: Mehdi Asnaashari
  • Patent number: 11269556
    Abstract: A memory controller for controlling an operation of a semiconductor memory device including a memory block including a plurality of sub-blocks. The memory controller includes a randomizer. The randomizer includes: seed table storage configured to store a plurality of seed tables respectively corresponding to the plurality of sub-blocks, and to generate a seed, based on sub-block information of received original data; a random sequence generator configured to generate a random sequence, based on the seed generated by the seed table storage; and an operating component configured to generate random data, based on the random sequence and the original data.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: March 8, 2022
    Assignee: SK hynix Inc.
    Inventor: Jiman Hong
  • Patent number: 11270775
    Abstract: A semiconductor memory device includes first and second memory cell transistors between first and second select transistors, third and fourth memory cell transistors between third and fourth select transistors, a first word line for first and third memory cell transistors, a second word line for second and fourth memory cell transistors, first to fourth selection gate lines respectively for first through fourth select transistors, a bit line, and a source line. During a read operation, while a voltage applied to the second word line is boosted, voltages applied to the first word line and the third and fourth selection gate line are also boosted, after which the voltage applied to the first word line is lowered, and the third and fourth selection gate lines are discharged. After the time the third and fourth selection gate lines are discharged, voltages applied to the bit line and the source line are boosted.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: March 8, 2022
    Assignee: KIOXIA CORPORATION
    Inventor: Takeshi Hioka
  • Patent number: 11257550
    Abstract: Disclosed herein are related to a memory device including a memory cell and a bias supply circuit providing a bias voltage to the memory cell. In one aspect, the bias supply circuit includes a bias memory cell coupled to the memory cell, where the bias memory cell and the memory cell may be of a same semiconductor conductivity type. The memory cell may include at least two gate electrodes, and the bias memory cell may include at least two gate electrodes. In one configuration, the bias memory cell includes a drain electrode coupled to one of the at least two gate electrodes of the bias memory cell. In this configuration, the bias voltage provided to the memory cell can be controlled by regulating or controlling current provided to the drain electrode of the bias memory cell.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: February 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Szu-Chun Tsao, Jaw-Juinn Horng
  • Patent number: 11250911
    Abstract: An operating method of a storage device comprising a nonvolatile memory device comprising a first memory stack and a second memory stack, and a memory controller coupled to control the nonvolatile memory device, the operating method includes determining a first read voltage level with which a first memory cell of the first memory stack is successfully read, and performing a read operation on a second memory cell of the second memory stack using a second read voltage determined based on the first read voltage level.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: February 15, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong-chul Park, Youn-yeol Lee, Seul-bee Lee, Kyung-sub Lim
  • Patent number: 11249931
    Abstract: The present invention provides a pin multiplexer including a multiplexing circuit, a control circuit and a detecting circuit. The multiplexing circuit includes a first port, a second port and a third port, wherein the first port, the second port and the third port are coupled to a first device, a second device and a third device, respectively. The control circuit is configured to control the multiplexing circuit to operate in a first mode or a second mode, wherein when the multiplexing circuit operates in the first mode, the first port is coupled the second port; and when the multiplexing circuit operates in the second mode, the first port is coupled to the third port. When operating in the second mode, the detecting circuit detects a signal of the first port to generate a detection result for dynamically switching the data transmission direction between the third device and the first device.
    Type: Grant
    Filed: March 8, 2020
    Date of Patent: February 15, 2022
    Assignee: Realtek Semiconductor Corp.
    Inventors: Li Tong, Zuohui Peng
  • Patent number: 11251199
    Abstract: A semiconductor structure includes vertically-alternating stacks of insulating strips and electrically conductive strips located over a substrate and laterally spaced apart from each other by line trenches. Laterally-alternating sequences of semiconductor region assemblies and dielectric pillar structures are located within a respective one of the line trenches. Memory films are located between each neighboring pair of the vertically-alternating stacks and the laterally-alternating sequences. Each of the semiconductor region assemblies includes a source pillar structure, a drain pillar structure, and a channel structure including a pair of lateral semiconductor channels that laterally connect the source pillar structure and the drain pillar structure. The memory films may include a charge storage layer or a ferroelectric material layer.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: February 15, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yanli Zhang, Johann Alsmeier
  • Patent number: 11237578
    Abstract: A voltage regulator includes a programming interface via which programming instructions may be applied to a processor of the voltage regulator. The voltage regulator operates the processor according to the programming instructions to select one of multiple active internally-generated analog voltage levels to determine an output voltage level of the voltage regulator.
    Type: Grant
    Filed: April 2, 2021
    Date of Patent: February 1, 2022
    Assignee: TAMIRAS PER PTE. LTD., LLC
    Inventor: David G. Wright
  • Patent number: 11237906
    Abstract: Methods, systems, and devices for generating a balanced codeword protected by an error correction code are described. A memory device may receive data bits for storage. Based on the data bits, the memory device may generate a codeword that includes the data bits, parity bits, and placeholder bits. The memory device may balance the codeword by inverting one or more packets of the codeword. After balancing the codeword, the memory device may store at least a portion of the codeword in memory so that a later operation or a decoding process reveals the packets that were inverted as part of the balancing process. Accordingly, the memory device may re-invert the appropriate packets to recover the original data bits.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: February 1, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Christophe Vincent Antoine Laurent
  • Patent number: 11237766
    Abstract: Provided herein may be a storage device and a method of operating the storage device. A memory device may include a memory cell array including a plurality of memory cells, a peripheral circuit configured to perform an operation on memory cells selected from among the plurality of memory cells, a voltage variation detector configured to generate voltage variation information indicating whether a voltage variation has occurred in a supply voltage during performance of the operation, a power register configured to store the voltage variation information, a status register configured to store status information indicating an operating status of the memory device, and a register output controller configured to update the status information provided from the status register based on the voltage variation information.
    Type: Grant
    Filed: May 1, 2020
    Date of Patent: February 1, 2022
    Assignee: SK hynix Inc.
    Inventors: Jin Yong Seong, Kyu Tae Park
  • Patent number: 11227658
    Abstract: A flash memory having high reliability and a method for controlling the flash memory is provided for seeking stability of memory cell threshold voltage distribution. A NAND string of the flash memory has: a source-line-side select transistor; a source-line-side dummy cell; a plurality of memory cells; a bit-line-side dummy cell; and a bit-line-side select transistor. A method for controlling the flash memory includes the following step: after erasing a selected block, programming the dummy cell of the selected block into a programmed state by applying a programming voltage to a dummy word line which is connected to the dummy cell.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: January 18, 2022
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Kenichi Arakawa, Sho Okabe
  • Patent number: 11227655
    Abstract: A semiconductor memory device includes a memory cell array including one or more memory cells each coupled between a wordline and a bitline, a sense amplifier configured to amplify a voltage of a global wordline, a wordline decoder including a plurality of wordline switches coupling the wordline and the global wordline, and a control circuit configured to control the wordline decoder and the sense amplifier.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: January 18, 2022
    Assignees: SK hynix Inc., Seoul National University R&DB Foundation
    Inventors: Hyungrok Do, Hong Seok Choi, Deog-Kyoon Jeong
  • Patent number: 11217295
    Abstract: Apparatuses and methods for address detection are disclosed herein. An example apparatus it an address filter and an address tracking circuit. The address filter may be configured to receive a first address and to determine whether the first address matches an address of a plurality of addresses associated with the address filter. The address tracking circuit may be coupled to the address filter and configured to store the first address responsive to a determination that the first address matches an address of the plurality of addresses associated with the address filter. The address tracking circuit may further be configured to receive a second address and to change a count associated with the first address based on the second address matching the first address. The address tracking circuit may be configured to selectively provide the first address responsive to the count.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: January 4, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Kallol Mazumder, Jason M. Brown, Derek R. May, Jeffrey E. Koelling, Roger D. Norwood
  • Patent number: 11217317
    Abstract: A memory device according to an embodiment includes a memory cell block including a plurality of pages with each page corresponding to a word line of a plurality of word lines, a peripheral circuit configured to perform a program operation on the plurality of pages, and control logic configured to control the peripheral circuit to perform the program operation. The control logic changes and sets a bit line voltage applied to bit lines of the memory cell block during a program verify operation of the program operation according to a program order of each of the plurality of pages.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: January 4, 2022
    Assignee: SK hynix Inc.
    Inventors: Jong Kyung Park, Ji Hyun Seo
  • Patent number: 11210168
    Abstract: A system includes a memory device having blocks of memory cells. A processing device is operatively coupled to the memory device, the processing device to detect an error event triggered within a source block of the memory cells. In response to detection of the error event, the processing device is to read data from the source block; write the data into a mitigation block that is different than the source block; and replace, in a block set map data structure, a first identifier of the source block with a second identifier of the mitigation block. The block set map data structure includes block location metadata for a data group, of the memory device, that includes the data.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: December 28, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Johnny A. Lam
  • Patent number: 11205681
    Abstract: Memory devices for embedded applications are described. A memory device may include an array of memory cells having a first area and configured to operate at a first voltage, and circuitry having a second area that at least partially overlaps the first area. The circuitry may be configured to operate at a second voltage lower than the first voltage. The circuitry maybe be further configured to access the array of memory cells using decoder circuitry configured to operate at the first voltage. The array of memory cells and the circuitry may be on a single substrate. The circuitry may include microcontroller circuitry, cryptographic controller circuitry, and/or memory controller circuitry. The memory cells may be self-selecting memory cells that each include a storage and selector element having a chalcogenide material. The memory cells may not include separate cell selector circuitry.
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: December 21, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Andrea Redaelli
  • Patent number: 11201162
    Abstract: For erasing four-terminal semiconductor Non-Volatile Memory (NVM) devices, we apply a high positive voltage bias to the control gate with source, substrate and drain electrodes tied to the ground voltage for moving out stored charges in the charge storage material to the control gate. For improving erasing efficiency and NVM device endurance life by lowering applied voltage biases and reducing the applied voltage time durations, we engineer the lateral impurity profile of the control gate near dielectric interface such that tunneling occurs on the small lateral region of the control gate near the dielectric interface. We also apply the non-uniform thickness of coupling dielectric between the control gate and the storage material for the NVM device such that the tunneling for the erase operation occurs within the small thin dielectric areas, where the electrical field in thin dielectric is the strongest for tunneling erase operation.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: December 14, 2021
    Assignee: FLASHSILICON INCORPORATION
    Inventor: Lee Wang
  • Patent number: 11189359
    Abstract: Methods, systems, and devices for techniques for data programming are described for programming data to a memory system using a second programming mode associated with a higher error rate than a first programming mode. The second programming mode may include skipping one or more voltage calibration procedures included in the first programming mode, as well as performing one or more data verification procedures once a larger set of the data is programmed. The second programming mode may also include using a higher programming voltage pulse to program data and the programming pulse may last for a longer period of time than a programming pulse for the first programming mode. A memory system may receive data, determine to write the data to a memory device using the second programming mode, write the data using the second programming mode, and verify whether the data satisfies an error threshold.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: November 30, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Giuseppe Cariello
  • Patent number: 11182288
    Abstract: A method of decoding data from high density memory includes reading voltage levels from a first memory cell and a set of one or more neighboring memory cells of flash memory in response to a read command with an address corresponding to the first memory cell, inputting the voltage levels into a trained model that has been trained on the flash memory to estimate bit values written to a memory cell based on respective voltage values read from the first memory cell and from the neighboring memory cells according to a layout of memory cells of the flash memory, obtaining from the trained model an estimated bit value written to the first memory cell based on the respective voltage levels of the first memory cell and the neighboring memory cells having been input into the trained model, and outputting the estimated hit value in response to the read command.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: November 23, 2021
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: B Hari Ram, Vijay Ahirwar, Sri Varsha Rottela, Nilesh N. Khude
  • Patent number: 11183242
    Abstract: The present disclosure includes apparatuses, methods, and systems for preventing parasitic current during program operations in memory. An embodiment includes a sense line, an access line, and a memory cell. The memory cell includes a first transistor having a floating gate and a control gate, wherein the control gate of the first transistor is coupled to the access line, and a second transistor having a control gate, wherein the control gate of the second transistor is coupled to the access line, a first node of the second transistor is coupled to the sense line, and a second node of the second transistor is coupled to the floating gate of the first transistor. The memory cell also includes a diode, or other rectifying element, coupled to the sense line and a node of the first transistor.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: November 23, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Daniele Vimercati
  • Patent number: 11176998
    Abstract: A semiconductor memory device includes a memory cell array having memory strings that include memory cells and first and second selection transistors. During a read operation, a controller applies a first voltage higher than ground to a source line, and a second voltage to a first and second selection gate lines that are connected to a selected memory string. The second voltage is also applied to the first selection gate lines connected to non-selected memory strings during a first period of the read operation. A third voltage higher than ground and lower than the second voltage is applied to the first selection gate lines connected to non-selected memory strings during a second period of the read operation subsequent to the first period.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: November 16, 2021
    Assignee: KIOXIA CORPORATION
    Inventor: Hiroshi Maejima
  • Patent number: 11170837
    Abstract: Methods, systems, and devices related to identifying high impedance faults in a memory device are described. A memory device may perform a first write operation to write a first logic state to a memory cell. During the first write operation, the memory device may establish a connection between a supply line and a control line associated with applying an output of a driver of a digit line coupled to the memory cell. After performing the first operation, the memory device may configure the supply line in a floating state. After the supply line is floated, the memory device may perform a second write operation to write a second logic state to the memory cell. The memory device may perform a third operation for reading the memory cell. The memory device may determine the condition of the supply line or control based on the result of the read operation.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: November 9, 2021
    Assignee: Micron Technology
    Inventors: Daniel S. Miller, Yoshinori Fujiwara
  • Patent number: 11170838
    Abstract: A memory system having a temperature effect compensation mechanism is provided. The memory system may include a plurality of memory cells, where the memory cells are organized in an array having two or more rows of memory cells arranged horizontally and two or more columns of memory cells arranged vertically. The plurality of memory cells may have an operating temperature range. The memory system may also include a temperature-dependent biasing circuit that is configured to reduce a biasing voltage to the plurality of memory cells when the temperature of the array is at or near an upper end of the operating temperature range and increase the biasing voltage to the plurality of memory cells when the temperature of the array is at or near a lower end of the operating temperature range.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: November 9, 2021
    Assignee: MENTIUM TECHNOLOGIES INC.
    Inventors: Farnood Merrikh Bayat, Jaroslaw Sulima, Mirko Prezioso
  • Patent number: 11164636
    Abstract: A nonvolatile memory device includes a memory cell array, an erase body voltage generator, and an erase source voltage generator. The memory cell array includes memory blocks, each of which includes cell strings each including a ground selection transistor, memory cells, and a string selection transistor stacked in a direction perpendicular to a substrate. The erase body voltage generator applies an erase body voltage to the substrate during an erase operation. The erase source voltage generator applies an erase source voltage to a common source line connected with ground selection transistors of the cell strings during the erase operation.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: November 2, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sunyeong Lee, Kyungmoon Kim, Woojae Jang, Chanjong Ju
  • Patent number: 11158384
    Abstract: An apparatus is provided that includes a plurality of NAND strings having a common set of word lines. Each NAND string includes data memory cells for data storage and dummy memory cells connected in series with the data memory cells. A first group of NAND strings includes dummy memory cells with a first pattern of threshold voltages and a second group of NAND strings includes dummy memory cells with a second pattern of threshold voltages for separate isolation of data memory cells of the first and second groups of NAND strings from corresponding bit lines.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: October 26, 2021
    Assignee: SanDisk Technologies LLC
    Inventor: Hiroki Yabe
  • Patent number: 11158387
    Abstract: Methods, systems, and devices for techniques for determining memory cell read offsets are described to support determining voltage offsets and corresponding read voltage levels for one or more memory cell levels using a relationship between read voltage levels and voltage offsets. A memory device may estimate first voltage offsets using a first procedure and may perform a read operation using the first voltage offsets. If a first voltage offset results in a read error for a corresponding memory cell level, the memory device may determine an updated voltage offset using the relationship. The relationship may predict a voltage offset for a given read voltage level, such that the memory device may use the relationship to predict an updated voltage offset for a memory cell level. The memory device may use the updated voltage offset(s) to perform a second read operation for the one or more memory cells.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: October 26, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Deping He, Jingyuan Miao
  • Patent number: 11158648
    Abstract: A semiconductor device includes a substrate, a fin structure, an insulating layer, a select gate, a memory gate, and a charge trapping layer. The fin structure includes a first portion and a second extend from the substrate. Each of the first portion and the second portion includes a first sidewall and a second sidewall, and the second sidewalls are between the first sidewalls. The insulating layer is disposed between the second sidewalls of the first and second portions. The select gate and the memory gate extend across the fin structure and the insulating layer. The charge trapping layer is disposed between the memory gate and the select gate, between the memory gate and the insulating layer, and between the memory gate and the fin structure, and the second sidewalls of the first and second portions are free from in contact with the charge trapping layer.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: October 26, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Shu Huang, Ming-Chyi Liu
  • Patent number: 11152070
    Abstract: The present disclosure relates to a memory device. The memory device includes first memory cell strings, second memory cell strings, a peripheral circuit, and a control logic. The peripheral circuit is connected to first drain select transistors of each of the first memory cell strings through first bit lines, and is connected to second drain select transistors of each of the second memory cell strings through second bit lines. The control logic controls the peripheral circuit to increase a potential of a program inhibit bit line among the first bit lines to a first voltage, and float the program inhibit bit line and increase a potential of the second bit line to a second voltage after the potential of the program inhibit bit line increases to the first voltage.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: October 19, 2021
    Assignee: SK hynix Inc.
    Inventor: Soo Yeol Chai
  • Patent number: 11152069
    Abstract: According to one embodiment, a semiconductor storage device includes a first memory string including a first memory transistor, a first word line connected to a gate electrode of the first memory transistor, a source line connected to one end of the memory string, and a first connection transistor connected between the first word line and the source line.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: October 19, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Sanad Bushnaq, Noriyasu Kumazaki, Masashi Yamaoka
  • Patent number: 11139378
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer, a charge storage layer provided on the surface of the semiconductor layer via a first insulating film, and an electrode layer provided on the surface of the charge storage layer via a second insulating film. The first insulating film includes a first region where the compositional ratio of nitrogen to silicon, oxygen and nitrogen varies from a first value to a second value, which is lower than the first value, along a first direction from the semiconductor layer toward the charge storage layer.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: October 5, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Masaki Noguchi, Tatsunori Isogai, Tomonori Aoyama
  • Patent number: 11132037
    Abstract: An operating temperature of a memory sub-system is identified. It is determined that the identified operating temperature satisfies a first temperature condition. Upon determining that the identified operating temperature satisfies the first temperature condition, operations are performed at the memory sub-system until the operating temperature changes to satisfy a second temperature condition.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: September 28, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Shane Nowell, Sivagnanam Parthasarathy
  • Patent number: 11133792
    Abstract: A level shifter includes a compact bias generator. The compact bias generator generates a first bias signal and a second bias signal, in the absence of a buffer. The level shifter also includes a first latch in a first stage to translate a first voltage to a second voltage based on the first bias signal. The level shifter further includes a second latch in a second stage to translate the first voltage to a third voltage based on the second bias signal. The first bias signal is independent of the second bias signal.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: September 28, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Qubo Zhou, Sherif Galal
  • Patent number: 11127472
    Abstract: A memory device includes a voltage generator that provides a read voltage to a selected word line and provides a pass voltage to a plurality of unselected word lines, and a deterioration level detection circuit. The selected word line and the unselected word lines are connected to a plurality of memory cells. The deterioration level detection circuit detects a deterioration level of memory cells connected to the selected word line based on data of memory cells that receive the read voltage. The memory cells connected to the selected word line and the memory cells that receive the read voltage are included in the plurality of memory cells. The voltage generator changes the pass voltage provided to the unselected word lines based on the deterioration level.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: September 21, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Han Jun Lee, Seung Bum Kim, Il Han Park
  • Patent number: 11113198
    Abstract: A memory sub-system configured to schedule the transfer of data from a host system for write commands to reduce the amount and time of data being buffered in the memory sub-system. For example, after receiving a plurality of streams of write commands from a host system, the memory sub-system identifies a plurality of media units in the memory sub-system for concurrent execution of a plurality of write commands respectively. In response to the plurality of commands being identified for concurrent execution in the plurality of media units respectively, the memory sub-system initiates communication of the data of the write commands from the host system to a local buffer memory of the memory sub-system. The memory sub-system has capacity to buffer write commands in a queue, for possible out of order execution, but limited capacity for buffering only the data of a portion of the write commands that are about to be executed.
    Type: Grant
    Filed: May 1, 2020
    Date of Patent: September 7, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Sanjay Subbarao
  • Patent number: 11114162
    Abstract: According to the present embodiment, a semiconductor memory device includes a first memory bunch including a first source line, a first source side selecting gate transistor, a first source side selecting gate line, a plurality of first non-volatile memory cells, a plurality of first word lines, a first drain side selecting gate transistor, a first drain side selecting gate line, and a first bit line; a second memory bunch including, a second source line, a second source side selecting gate transistor, a second source side selecting gate line, a plurality of second non-volatile memory cells, a plurality of second word lines, a second drain side selecting gate transistor, a second drain side selecting gate line, and a second bit line; a common bit line; a first bit line transfer transistor; and a second bit line transfer transistor.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: September 7, 2021
    Assignee: Kioxia Corporation
    Inventor: Yoshikazu Hosomura
  • Patent number: 11107542
    Abstract: A semiconductor memory device includes a word line connected to memory cells, bit lines respectively connected to the memory cells, and a control circuit configured to control voltages applied to the word line and the bit lines during a write operation. When writing data into a target memory cell, the control circuit executes first and second loops in sequence. In executing the first loop, the control circuit applies a first program voltage to the word line during the program operation, and applies a verify voltage to the word line during the verify operation, and upon detecting that the verify operation neither passed nor failed, the control circuit selects one of two pass write voltages to be applied to the bit line connected to the target memory cell during the program operation of the second loop according to a sequential position of the first loop in the sequence of loops.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: August 31, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Mario Sako
  • Patent number: 11107522
    Abstract: Disclosed are systems and methods for providing programming of multi-level memory cells using an optimized multiphase mapping with a balanced Gray code. A method includes programming, in a first phase, a first portion of data into memory cells in a first-level cell mode. The method may also include reading, from the memory cells, the programmed first portion of the data. The method may also include programming, in a second phase, a second portion of the data into the memory cells in a second-level cell mode, wherein programming the second phase is based on applying, to the read first portion of the data, a mapping from the first-level cell mode to the second-level cell mode. The mapping may be selected based on minimizing an average voltage change of the memory cells from the first to second phase while maintaining a balanced Gray code.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: August 31, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Mostafa El Gamal, Niranjay Ravindran, James Fitzpatrick
  • Patent number: 11101001
    Abstract: A non-volatile memory system includes a control circuit connected to non-volatile memory cells. The control circuit is configured to simultaneously program memory cells connected to different word lines that are in different sub-blocks of different blocks in different planes of a die.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: August 24, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Henry Chin, Zhenming Zhou
  • Patent number: 11100975
    Abstract: According to one embodiment, a semiconductor memory device includes a plurality of memory cells connected to a word line, a circuit configured to apply a voltage to the word line, a detection circuit configured to detect a first time difference from when a first signal of which a voltage is increased with a first slope is applied to the word line to when a current flows through the memory cells in response to applying the first signal, and a second time difference from when a second signal of which a voltage is increased with a second slope is applied to the word line to when a current flows through the memory cells in response to applying the second signal, the second slope being different from the first slope, and a determination circuit configured to determine a threshold voltage of the memory cells based on a difference between the first time difference and the second time difference.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: August 24, 2021
    Assignee: KIOXIA CORPORATION
    Inventors: Rui Ito, Makoto Morimoto, Yutaka Shimizu, Ryuichi Fujimoto
  • Patent number: 11100994
    Abstract: A content addressable memory cell includes a first floating body transistor and a second floating body transistor. The first floating body transistor and the second floating body transistor are electrically connected in series through a common node. The first floating body transistor and the second floating body transistor store complementary data.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: August 24, 2021
    Assignee: Zeno Semiconductor, Inc.
    Inventors: Benjamin S. Louie, Jin-Woo Han, Yuniarto Widjaja
  • Patent number: 11086790
    Abstract: A memory device and methods for operating the same are provided. The memory device includes an array of memory cells, a non-volatile memory, and a controller. The controller is configured to receive a read command to read a data word from an address of the array and decode the address to generate a decoded address. The controller is further configured to retrieve response data from the decoded address of the array, retrieve a location indicia corresponding to the decoded address from the non-volatile memory, and verify that the location indicia corresponds to the address. The controller can optionally be further configured to indicate an error if the location indicia does not correspond to the address.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: August 10, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Alberto Troia
  • Patent number: 11088158
    Abstract: The present invention discloses a SONOS memory in which two storage gates in a storage unit are self-aligned on the side of a selection gate, states of information stored in two storage gates in the same storage unit being opposite, the storage information of the storage unit being judged by comparing the magnitude of reading currents corresponding to two storage gates. The present invention further discloses a method for manufacturing a SONOS memory. The present invention can improve the reliability of the product and reduce the area of the device at the same time.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: August 10, 2021
    Assignee: Shanghai Huali Integrated Circuit Corporation
    Inventor: Xiaoliang Tang
  • Patent number: 11087849
    Abstract: A non-volatile memory system includes a control circuit connected to non-volatile memory cells. The control circuit is configured to simultaneously program memory cells connected to different word lines that are in different sub-blocks of different blocks in different planes of a die.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: August 10, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Henry Chin, Zhenming Zhou