Abstract: A semiconductor memory device of the present invention comprises, a semiconductor substrate, a drain region formed in the semiconductor substrate, a source region formed in the semiconductor substrate, a gate insulating film formed between the drain region and the source region on the semiconductor substrate, a floating gate electrode formed on the gate insulating film. The floating gate electrode has a projection portion on the end portion thereof.

Abstract: When two bits are stored per memory cell and the two bits are written or read, writing or reading operation has to be performed twice. When a memory array is constructed by using a memory cell, by the access of twice, read time or write time twice as long as conventional read or write time is required. It causes deterioration in speed of a system using the memory. To solve the problem, according to the invention, bit arrangement of a conventional memory cell array is changed according to a writing or reading method With the configuration, a plurality of bytes can be simultaneously written or read by a single access. In order to perform reading at higher speed, a sense amplifier requiring no precharging is also provided.

Abstract: A semiconductor memory includes a plurality of memory cells arranged along rows and columns, each cell having a floating gate, a drain region, a source region, a program gate terminal, and a select gate terminal. The program gate terminals of the cells along each row of cells are connected together forming a continuous program gate line. The select gate terminals of the cells along each row of cells are connected together forming a continuous select gate line. The source regions of the cells along each row of cells are connected together forming a continuous source line. The cells along each column are divided into a predesignated number of groups, and the drain regions of the cells in each group are connected to a local bitline extending across the cells in the group of cells. A global bitline extends along every two columns of cells, and is configured to selectively provide electrical connection to the local bitlines along the corresponding two columns of cells.

Abstract: A memory cell (400) used to store data in an integrated circuit. The memory cell (400) is static, nonvolatile, and programmable. The layout of the memory cell is compact. A logic high output from the memory cell (400) is about VDD and a logic low output is about VSS. The memory cell (400) of the present invention includes a programmable memory element (810). In one embodiment, the programmable memory element (810) is coupled between supply voltage (510) and an output node (405). A pull-down device (525) is coupled between another supply voltage (505) and the output node (405). The memory cell (400) may be used to store the configuration information for a programmable logic device (121).

Abstract: Embodiments relate to a non-volatile semiconductor memory device in which the interface state between the tunnel insulation layer and the floating gate and the interface state between the tunnel insulation layer and the control gate are lower, the operation characteristics are stable, and the data writing/erasing cycle life is long. A non-volatile semiconductor memory device (memory transistor) 400 may include a non-volatile semiconductor memory device with a split-gate structure having a source 16, a drain 14, a gate insulation layer 26, a floating gate 40, an intermediate insulation layer 50 that functions as a tunnel insulation layer, and a control gate 36. The intermediate insulation layer 50 is composed of at least three insulation layers 50a, 50b and 50c. The first and the second outermost layers 50a and 50c of the three insulation layers respectively contact the floating gate 40 and the control gate 36, and are composed of silicon oxide layers that are formed by a thermal oxidation method.

Abstract: A non-volatile memory cell and associated cell array and memory device having reduced program disturb, improved retention of programmed information, and reduced power consumption are disclosed. The memory cell includes a control device coupled to a switch device via a common floating gate, with the control device and the switch device formed on a common substrate, and the switch device formed at least in part in a tub region on the substrate. The tub region has a contact region formed therein. The contact region is adapted for application of a bias voltage to the tub region during a programming operation of the memory cell so as to reduce a programming voltage required to program the memory cell. In an illustrative embodiment, a drain-to-substrate voltage required to program the memory cell is reduced from a conventional value of about 6.5 volts to a value of about 3.5 volts, thus alleviating program disturb problems that can result, e.g.

Abstract: Disclosed is a semiconductor computing circuit achievable with simple circuitry and capable of performing analog computations at high speed to compute an absolute-value voltage representing the difference between a first signal voltage and a second signal voltage.

Abstract: A non-volatile memory device is disclosed which includes an erase device that is shared among an array of memory cells. Each of the memory cells in the array includes a control device coupled to a switch device via a common floating gate. Each of at least a subset of the memory cells further includes a portion of the shared erase device, the portion of the shared erase device associated with a given one of the memory cells being coupled to the switch device of that cell via the floating gate of that cell. The shared erase device is utilizable in performing an erase operation for each of the memory cells associated therewith. Advantageously, the use of the shared erase device substantially reduces the circuit area requirements of the memory array. The invention is particularly well suited for implementation in single-poly flash EEPROM embedded memory devices in integrated circuit applications.

Abstract: A programmable impedance element (204) is implemented using integrated circuit techniques and devices. An impedance of the programmable impedance element is adjusted by appropriately configuring the element. The programmable impedance element has a range of impedance values, and is configurable to be a value within this range. In an embodiment, the programmable impedance element is implemented using a floating gate device (230), and is nonvolatile.

Abstract: When two bits are stored per memory cell and the two bits are written or read, writing or reading operation has to be performed twice. When a memory array is constructed by using a memory cell, by the access of twice, read time or write time twice as long as conventional read or write time is required. It causes deterioration in speed of a system using the memory. To solve the problem, according to the invention, bit arrangement of a conventional memory cell array is changed according to a writing or reading method With the configuration, a plurality of bytes can be simultaneously written or read by a single access. In order to perform reading at higher speed, a sense amplifier requiring no precharging is also provided.

Abstract: In a semiconductor integrated circuit device including a third gate, the present invention improves miniaturization and operation speed and reduces a defect density of an insulator film. In a semiconductor integrated circuit device including a well of a first conductivity type formed in a semiconductor substrate, a source/drain diffusion layer of a second conductivity type inside the well, a floating gate formed over the semiconductor substrate through an insulator film, a control gate formed and isolated from the floating gate through an insulator film, word lines formed by connecting the control gates and a third gate formed and isolated from the semiconductor substrate, the floating gate and the control gate through an insulator film and different from the floating gate and the control gate, the third gate is buried into a space of the floating gates existing in a direction vertical to the word line and a channel.

Abstract: Nonvolatile memory device and a method of programming the same, is disclosed, wherein, for single level or multi-level programming of a cell, predetermined voltages are applied to a control gate, source and drain respectively for varying a charge amount in the floating gate. A channel in a transistor is turned off at an initial stage and then turned on thereafter, and at least one of the voltages applied to the control gate and the program/select gate is halted to stop the programming when a conductivity of the channel region reaches a reference value.

Abstract: A semiconductor device includes a first terminal for inputting and outputting data and a second terminal for inputting control data in synchronization with a strobe signal. The semiconductor device includes an equivalent circuit which is provided in the second terminal. Further, the equivalent circuit has a capacitance which is equivalent to that in an output circuit which is provided in the first terminal.

Abstract: A memory cell (400) used to store data in an integrated circuit. The memory cell (400) is static, nonvolatile, and programmable. The layout of the memory cell is compact. A logic high output from the memory cell (400) is about VDD and a logic low output is about VSS. The memory cell (400) of the present invention includes a programmable memory element (515). In one embodiment, the programmable memory element (515) is coupled between supply voltage (510) and an output node (405). A pull-down device (525) is coupled between another supply voltage (505) and the output node (405). The memory cell (400) may be used to store the configuration information for a programmable logic device (121).

Abstract: An electrically alterable, non-volatile memory cell has more than two memory states that can be programmed selectively. Programming of the cell is conducted by applying a plurality of programming signals having different characteristics to the cell. The programming signals include at least a first programming signals which programs the cell by a first increment and a subsequent programming signal which programs the cell by a second increment smaller than the first increment. As the cell is being programmed to a selected state, its programming status is verified independently of reference values bounding the memory states. For this purpose, a signal indicative of the programming status (e.g., the cell's bit line signal) is compared with a reference signal corresponding to the selected state but having a value different from the reference value or values bounding the selected state. The programming operation can thus be controlled without actually reading the memory state of the cell.

Abstract: A circuit for controlling a switching transistor in a reprogrammable FPGA device comprises first and second floating gate flash memory transistors. A first floating gate flash memory transistor has a drain electrically coupled to a first voltage potential, a floating gate, a control gate coupled to a control gate node, and a source coupled to an output node. A second floating gate flash memory transistor has a drain electrically coupled to the output node, a floating gate, a control gate coupled to the control gate node, and a source coupled to a second voltage potential. The output node is coupled to the gate of a switching transistor.

Abstract: The present invention discloses a single poly non-volatile memory structure including a semiconductor substrate with two active areas divided by isolation regions. A control gate doped with N-type impurities is embedded in the first active area, and a first floating gate is formed thereon. A second floating gate is formed on the substrate of the second active area, and two doped regions are implanted at opposite sides of the second active areas in the substrate. A floating gate line is employed to connect the first and second floating gate for making sure that the two floating gates are in the same potential. When the control gate is biased to a voltage level, the voltage level would be coupled to the first floating gate so as to keep the second floating gate in the same potential with the first floating gate. While one of the doped regions is biased to a voltage level, electrons would eject from the other doped region and trapped in the floating gates, thereby preserving information in this memory structure.

Abstract: A programmable impedance element (204) is implemented using integrated circuit techniques and devices. An impedance of the programmable impedance element is adjusted by appropriately configuring the element. The programmable impedance element has a range of impedance values, and is configurable to be a value within this range. In an embodiment, the programmable impedance element is implemented using a floating gate device (230), and is nonvolatile.

Abstract: A content addressable memory (CAM) includes non-volatile CAM cells that are in an array similar to a conventional Flash memory array. In the CAM, each word line connects to control gates of Flash memory cells in a row, each bit line connects to drains of Flash memory cells in a column, and each match line is a source line coupled to sources of Flash memory cells in a row. A 2-T CAM cell includes a pair of non-volatile devices coupled to the same word line and match line. Each non-volatile device can be a floating-gate transistor, a Flash memory cell, or a shared-floating-gate (SFG) device. An erase of a CAM word applies erase voltages to the word and match lines associated with the word. The erase does not depend on the bit line voltages. Accordingly, the CAM array can simultaneously perform a search and an erase. With SFG devices, the CAM array can also simultaneously perform a search and a program operation.

Abstract: A memory cell (400) used to store data in an integrated circuit. The memory cell (400) is static, nonvolatile, and programmable. The layout of the memory cell is compact. A logic high output from the memory cell (400) is about VDD and a logic low output is about VSS. The memory cell (400) of the present invention includes a programmable memory element (515). In one embodiment, the programmable memory element (515) is coupled between supply voltage (510) and an output node (405). A pull-down device (525) is coupled between another supply voltage (505) and the output node (405). The memory cell (400) may be used to store the configuration information for a programmable logic device (121).

Abstract: A non-volatile memory cell is formed in a semiconductor substrate and includes a control gate and a floating gate formed over said semiconductor substrate. A first active region and a second active region formed in said substrate. A first implant region formed in said substrate, said first implant region contiguous to said first active region and a second implant region formed in said substrate, said second implant region contiguous to said second active region. A channel region separates said first implant region and said second implant region. In a further aspect, a method of programming and erasing a non-volatile memory cell is disclosed. Programming of said cell is accomplished by injecting hot carriers into a floating gate through a first area of an oxide layer by capacitively coupling said floating gate to a substrate. Erasing said cell is accomplished by injecting oppositely charged hot carriers into said floating gate through a second area of said oxide layer.

Abstract: A flash memory cell in the form of a transistor capable of storing multi-bit binary data is disclosed. A pair of floating gates are provided beneath a control gate. The control gate is connected to a word line while source and drain regions are connected to respective digit lines. The floating gates are separately charged and read out by controlling voltages applied to the word line and digit lines. The read out charges are decoded into a multi-bit binary value. Methods of fabricating the memory cell and operating it are also disclosed.

Abstract: The charge injection circuit of this invention comprises at least one pair of floating gate MOS transistors having source and drain terminals which are coupled together and to an injection node, and at least one corresponding pair of generators of substantially step-like voltage signals having an initial value and a final value, and having outputs respectively coupled to the control terminals of said transistors. The signal generators are such that the initial value of a first of the signals is substantially the equal of the final value of a second of the signals, and that the final value of the first signal is substantially the equal of the initial value of the second signal.

Abstract: The present invention is directed to a wordline driving apparatus in semiconductor memory devices. The wordline driving apparatus comprises a CMOS distributed type sub-wordline driver for receiving an output signal of a row decoder through a main wordline having a wiring structure of a single output line and controlling enabling of the sub-wordline in accordance with the received output signal and a sub pull-down driver for receiving the inverted signals of boosting signals through a control signal supplying wiring and performing a sub pull-down function with respect to the voltage level of the sub-wordline. According to the present invention, it is possible to greatly improve an access time with enhancing a high voltage transfer efficiency and preventing a delay of signal.

Abstract: A memory cell (400) used to store data in an integrated circuit. The memory cell (400) is static, nonvolatile, and programmable. The layout of the memory cell is compact. A logic high output from the memory cell (400) is about VDD and a logic low output is about VSS. The memory cell (400) of the present invention includes a programmable memory element (515). In one embodiment, the programmable memory element (515) is coupled between supply voltage (510) and an output node (405). A pull-down device (525) is coupled between another supply voltage (505) and the output node (405). The memory cell (400) may be used to store the configuration information for a programmable logic device (121).

Abstract: An object of the present invention is to realize a memory cell including a single polysilicon layer so as to simplify the fabrication process, improve the productivity and lower the fabrication cost of the memory cell. Another object of the present invention is to realize a memory cell with a simple structure as well as to reduce the area of the memory cell so as to attain high integration. Still another object of the present invention is to form a fine memory cell by utilizing DHE (drain channel hot electrons) and GIDL (gate induced drain leakage). An EEPROM memory cell 10 includes a substrate 12; a source region 14 and a drain region 16 formed on a surface of the substrate 12; a channel region 18 defined on the surface of the substrate 12 between the source region 14 and the drain region 16; a gate oxide film 20 formed on the channel region 18 so as to partly overlap with the source region 14 and the drain region 16; and a gate 22 including polysilicon formed on the gate oxide film 20.

Abstract: A combination non-volatile latch circuit has a volatile latch circuit having a bit signal and an inverse bit signal. A first and a second non-volatile cell of the split gate floating gate type having a first terminal, a second terminal and a control gate is supplied. A first switch supplies the bit signal to the first terminal of the first cell and the inverse bit signal to the first terminal of the second cell. A second switch supplies the bit signal to the first terminal of the second cell and the inverse bit signal to the first terminal of the first cell. A first voltage can be supplied to the second terminal of the first and second cells and a second voltage supplies a voltage to the control gate of the first and second cells. In this manner, the latch can be operated independently of the non-volatile memory cells, the status of the latch can be restored by the status of the non-volatile memory cells, and the contents of the latch can be stored in the non-volatile memory cells.

Abstract: A method of determining a coupling ratio of a split-gate memory cell includes initializing the cell, placing the cell in a reverse operation mode, sweeping a control gate voltage of the cell, measuring a source voltage of the cell, and determining the coupling ratio of the memory cell. The initializing can include substantially fully charging a floating gate of the cell. In that case, the measuring occurs while the floating gate is substantially fully charged. The determining can include the determination of two coupling ratios of the split-gate memory cell. To determine the two coupling ratios, a first function is defined having three unknown variables, the two coupling ratios being two of the unknown variables, and a second function is defined where only the two coupling ratios are unknown variables. By solving for the first function and second function using the measurement, the two coupling ratios are determined.

Abstract: A non-volatile memory cell structure which includes a floating gate, a reverse breakdown element and a read transistor. The reverse breakdown element is at least partially formed in a first region of a first conductivity type in a semiconductor substrate, and underlies a portion of the floating gate; and the read transistor is at least partially formed in the first region and connected to the reverse breakdown element. In a further embodiment a control gate is capacitively coupled to the floating gate and is formed in a second region of the substrate, outside the well region.

Abstract: A programmable impedance element (204) is implemented using integrated circuit techniques and devices. An impedance of the programmable impedance element is adjusted by appropriately configuring the element. The programmable impedance element has a range of impedance values, and is configurable to be a value within this range. In an embodiment, the programmable impedance element is implemented using a floating gate device (230), and is nonvolatile.

Abstract: A flash memory cell in the form of a transistor capable of storing multi-bit binary data is disclosed. A pair of floating gates are provided beneath a control gate. The control gate is connected to a word line while active doped regions (source and drain regions) are connected to respective digit lines. The floating gates are separately charged and read out by controlling voltages applied to the word line and digit lines. The read out charges are decoded into a multi-bit binary value. One or both of the floating gates has a side insulator which connects through a conductor to an associated active doped region thereby forming a capacitor across the side insulator between the floating gate. This capacitor and active region facilitates operation of the transistor as a flash memory cell. Methods of fabricating the memory cell and operating it are also disclosed.